DS26503 ,T1/E1/J1 BITS ElementFEATURES Fast Transmitter Output Disable through Device Accepts 8kHz and 19.44MHz References ..
DS26503 ,T1/E1/J1 BITS ElementFEATURES The DS26503 is a building-integrated timing- G.703 2048kHz Synchronization Interface sup ..
DS26503L+ ,T1/E1/J1 BITS ElementFEATURES The DS26503 is a building-integrated timing- G.703 2048kHz Synchronization Interface Comp ..
DS26503LN+ ,T1/E1/J1 BITS ElementAPPLICATIONS Clock BITS Timing 8-Bit Parallel Control Port, Multiplexed or Rate Conversion Nonmul ..
DS26504 ,T1/E1/J1/64KCC BITS ElementGENERAL DESCRIPTION with Receive Message Change of State and The DS26504 is a building-integrated t ..
DS26504L+ ,T1/E1/J1/64KCC BITS ElementGENERAL DESCRIPTION with Receive Message Change of State and The DS26504 is a building-integrated t ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26503
T1/E1/J1 BITS Element
GENERAL DESCRIPTION The DS26503 is a building-integrated timing-
supply (BITS) clock-recovery element. The
receiver portion can recover a clock from T1,
E1, and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the Synchronization Status Message (SSM) can also
be recovered. The transmit portion can directly
interface to T1 or E1 interfaces as well as source
the SSM in T1 and E1 modes. The DS26503 can
translate between any of the supported inbound synchronization clock rates to any supported
outbound rate. A separate output is provided to
source a 6312kHz clock. The device is
controlled through a parallel, serial, or hardware
controller port.
APPLICATIONS BITS Timing
Rate Conversion
Basic Transceiver
ORDERING INFORMATION
FEATURES ��G.703 2048kHz Synchronization Interface
Compliant
��G.703 6312kHz Japanese Synchronization
Interface Compliant
��Interfaces to Standard T1/J1 (1.544MHz) and E1 (2.048MHz)
��Interface to CMI-Coded T1/J1 and E1
��Short- and Long-Haul Line Interface
��Transmit and Receive T1 and E1 SSM
Messages with Message Validation
��Crystal-Less Jitter Attenuator with Bypass
Mode
��Fully Independent Transmit and Receive
Functionality
��Internal Software-Selectable Receive- and Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω
��Monitor Mode for Bridging Applications
��Accepts 16.384MHz, 8.192MHz, 4.096MHz,
2.048MHz, or 1.544MHz (T1 Only) Master Clock
��8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
��Serial (SPI) Control Port
��Hardware Control Mode
��Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
��Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
��IEEE 1149.1 JTAG Boundary Scan
��3.3V Supply with 5V-Tolerant Inputs and
Outputs
DS26503
T1/E1/J1 BITS Element
DS26503 T1/E1/J1 BITS Element
TABLE OF CONTENTS
1. FEATURES.......................................................................................................................7 1.1 GENERAL........................................................................................................................7
1.2 LINE INTERFACE...............................................................................................................7 1.3 JITTER ATTENUATOR........................................................................................................7
1.4 FRAMER/FORMATTER.......................................................................................................8
1.5 TEST AND DIAGNOSTICS...................................................................................................8
1.6 CONTROL PORT...............................................................................................................8
2. SPECIFICATIONS COMPLIANCE...................................................................................9
3. BLOCK DIAGRAMS.......................................................................................................12
4. PIN FUNCTION DESCRIPTION.....................................................................................15 4.1 TRANSMIT PLL...............................................................................................................15
4.2 TRANSMIT SIDE..............................................................................................................15
4.3 RECEIVE SIDE................................................................................................................16 4.4 CONTROLLER INTERFACE................................................................................................17
4.5 JTAG...........................................................................................................................21
4.6 LINE INTERFACE.............................................................................................................21
4.7 POWER.........................................................................................................................22
5. PINOUT...........................................................................................................................23
6. HARDWARE CONTROLLER INTERFACE....................................................................26 6.1 TRANSMIT CLOCK SOURCE.............................................................................................26
6.2 INTERNAL TERMINATION..................................................................................................26
6.3 LINE BUILD-OUT.............................................................................................................27
6.4 RECEIVER OPERATING MODES........................................................................................27 6.5 TRANSMITTER OPERATING MODES..................................................................................28
6.6 MCLK PRE-SCALER......................................................................................................28
6.7 OTHER HARDWARE CONTROLLER MODE FEATURES.........................................................29
7. PROCESSOR INTERFACE............................................................................................30 7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION.....................................................................30
7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION.................................................30
7.2.1 Clock Phase and Polarity...................................................................................................30
7.2.2 Bit Order.............................................................................................................................30
7.2.3 Control Byte.......................................................................................................................30 7.2.4 Burst Mode.........................................................................................................................30
7.2.5 Register Writes...................................................................................................................31
7.2.6 Register Reads..................................................................................................................31 7.3 REGISTER MAP..............................................................................................................32
7.3.1 Power-Up Sequence..........................................................................................................34
7.3.2 Test Reset Register............................................................................................................34 7.3.3 Mode Configuration Register..............................................................................................35
7.4 INTERRUPT HANDLING....................................................................................................38
7.5 STATUS REGISTERS.......................................................................................................38
7.6 INFORMATION REGISTERS...............................................................................................39
DS26503 T1/E1/J1 BITS Element
8. T1 FRAMER/FORMATTER CONTROL REGISTERS....................................................40 8.1 T1 CONTROL REGISTERS...............................................................................................40
9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46 9.1 E1 CONTROL REGISTERS...............................................................................................46
9.2 E1 INFORMATION REGISTERS..........................................................................................48
10. I/O PIN CONFIGURATION OPTIONS............................................................................52
11. T1 SYNCHRONIZATION STATUS MESSAGE..............................................................55 11.1 T1 BIT-ORIENTED CODE (BOC) CONTROLLER................................................................55 11.2 TRANSMIT BOC.............................................................................................................55
11.3 RECEIVE BOC...............................................................................................................56
12. E1 SYNCHRONIZATION STATUS MESSAGE..............................................................64 12.1 SA/SI BIT ACCESS BASED ON CRC4 MULTIFRAME...........................................................64
12.2 ALTERNATE SA/SI BIT ACCESS BASED ON DOUBLE-FRAME...............................................74
13. LINE INTERFACE UNIT (LIU)........................................................................................77 13.1 LIU OPERATION............................................................................................................78
13.2 LIU RECEIVER..............................................................................................................78
13.2.1 Receive Level Indicator......................................................................................................78
13.2.2 Receive G.703 Section 10 Synchronization Signal.............................................................79 13.2.3 Monitor Mode.....................................................................................................................79
13.3 LIU TRANSMITTER.........................................................................................................79
13.3.1 Transmit Short-Circuit Detector/Limiter...............................................................................80 13.3.2 Transmit Open-Circuit Detector..........................................................................................80
13.3.3 Transmit BPV Error Insertion..............................................................................................80
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)..........................................80 13.4 MCLK PRE-SCALER......................................................................................................80
13.5 JITTER ATTENUATOR......................................................................................................80
13.6 CMI (CODE MARK INVERSION) OPTION...........................................................................81
13.7 LIU CONTROL REGISTERS.............................................................................................82 13.8 RECOMMENDED CIRCUITS..............................................................................................90
13.9 COMPONENT SPECIFICATIONS........................................................................................92
14. LOOPBACK CONFIGURATION.....................................................................................96
15. 6312KHZ SYNCHRONIZATION INTERFACE................................................................97 15.1 RECEIVE 6312KHZ SYNCHRONIZATION INTERFACE OPERATION........................................97 15.2 TRANSMIT 6312KHZ SYNCHRONIZATION INTERFACE OPERATION.......................................97
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................98 16.1 INSTRUCTION REGISTER...............................................................................................102
16.2 TEST REGISTERS.........................................................................................................103
16.3 BOUNDARY SCAN REGISTER.........................................................................................103 16.4 BYPASS REGISTER......................................................................................................103
16.5 IDENTIFICATION REGISTER............................................................................................103
DS26503 T1/E1/J1 BITS Element
17. FUNCTIONAL TIMING DIAGRAMS.............................................................................106 17.1 PROCESSOR INTERFACE...............................................................................................106
17.1.1 Parallel Port Mode............................................................................................................106
17.1.2 SPI Serial Port Mode........................................................................................................106
18. OPERATING PARAMETERS.......................................................................................109
19. AC TIMING PARAMETERS AND DIAGRAMS............................................................111 19.1 MULTIPLEXED BUS.......................................................................................................111 19.2 NONMULTIPLEXED BUS................................................................................................114
19.3 SERIAL BUS................................................................................................................117
19.4 RECEIVE SIDE AC CHARACTERISTICS...........................................................................119
19.5 TRANSMIT SIDE AC CHARACTERISTICS.........................................................................121
20. REVISION HISTORY....................................................................................................122
21. PACKAGE INFORMATION..........................................................................................123
DS26503 T1/E1/J1 BITS Element
LIST OF FIGURES Figure 3-1. Block Diagram.....................................................................................................................12
Figure 3-2. Loopback Mux Diagram.......................................................................................................13
Figure 3-3. Transmit PLL Clock Mux Diagram.......................................................................................13 Figure 3-4. Master Clock PLL Diagram..................................................................................................14
Figure 13-1. Basic Network Connection.................................................................................................77
Figure 13-2. Typical Monitor Application................................................................................................79 Figure 13-3. CMI Coding.......................................................................................................................81
Figure 13-4. Basic Interface...................................................................................................................90
Figure 13-5. Protected Interface Using Internal Receive Termination....................................................91 Figure 13-6. E1 Transmit Pulse Template.............................................................................................93
Figure 13-7. T1 Transmit Pulse Template..............................................................................................93 Figure 13-8. Jitter Tolerance (T1 Mode)................................................................................................94
Figure 13-9. Jitter Tolerance (E1 Mode)................................................................................................94
Figure 13-10. Jitter Attenuation (T1 Mode)............................................................................................95 Figure 13-11. Jitter Attenuation (E1 Mode)............................................................................................95
Figure 16-1. JTAG Functional Block Diagram........................................................................................98
Figure 16-2. TAP Controller State Diagram.........................................................................................101 Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0.............................................106
Figure 17-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0.............................................106
Figure 17-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1.............................................106 Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1.............................................107
Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0.............................................107
Figure 17-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0.............................................107 Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1.............................................108
Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1.............................................108 Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00).............................................................112
Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)..............................................................112
Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)................................................................113
Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)..............................................................115 Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)..............................................................115
Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01).......................................................116 Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01).......................................................116
Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10.................................................118
Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10.................................................118 Figure 19-10. Receive Timing, T1/E1..................................................................................................120
Figure 19-11. Transmit Timing, T1/E1.................................................................................................122
