DS26502 ,T1/E1/J1/64KCC BITS ElementBLOCK DIAGRAMS...... 11 4. PIN FUNCTION DESCRIPTION.. 14 4.1 TRANSMIT PLL ... 14 4.2 TRANSMIT SIDE ..
DS26502DK ,T1/E1/J1/64KCC Bits Element Design Kit DS26502DK T1/E1/J1/64KCC Bits Element Design Kit
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DS26502L+ ,T1/E1/J1/64KCC BITS ElementFEATURES The DS26502 is a building-integrated timing- G.703 2048kHz Synchronization Interface supp ..
DS26502LN ,T1/E1/J1/64KCC BITS ElementBLOCK DIAGRAMS ....11 4. PIN FUNCTION DESCRIPTION ....14 4.1 TRANSMIT PLL...14 4.2 TRANSMIT SIDE..1 ..
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EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26502-DS26503-DS26504
T1/E1/J1/64KCC BITS Element
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
GENERAL DESCRIPTION The DS26504 is a building-integrated timing-supply (BITS) clock-recovery element. It also functions as a
basic T1/E1 transceiver. The receiver portion can
recover a clock from T1, E1, 64kHz composite clock (64KCC), and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the Synchronization Status Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1, or
64KCC synchronization interfaces as well as source the SSM in T1 and E1 modes. The DS26504 can
translate between any of the supported inbound
synchronization clock rates to any supported outbound rate. The DS26504 can also accept an 8kHz
as well as a 19.44MHz reference clock. A separate
output is provided to source a 6312kHz clock. The device is controlled through a parallel, serial, or
hardware controller port.
APPLICATIONS BITS Timing Rate Conversion
FEATURES Accepts 8kHz and 19.44MHz References in
Addition to T1, E1, and 64kHz Composite Clock GR378 Composite Clock Compliant G.703 2048kHz Synchronization Interface
Compliant G.703 64kHz Option A & B Centralized Clock Synchronization Interface Compliant G.703 64kHz Japanese Composite Clock
Synchronization Interface Compliant G.703 6312kHz Japanese Synchronization
Interface Compliant Interfaces to Standard T1/J1 (1.544MHz) and E1 (2.048MHz) Interface to CMI-Coded T1/J1 and E1 T1/E1 Transmit Payload Clock Output Short- and Long-Haul Line Interface Transmit and Receive T1 BOC SSM Messages with Receive Message Change of State and
Validation Indication Transmit and Receive E1 Sa(n) Bit SSM
Messages with Receive Message Change of State
Indication Crystal-Less Jitter Attenuator with Bypass Mode
for T1 and E1 Operation Fully Independent Transmit and Receive Functionality Internal Software-Selectable Receive and
Transmit Side Termination for 75Ω/100Ω/110Ω/120Ω/133Ω Monitor Mode for Bridging Applications Accepts 16.384MHz, 12.8MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz Master
Clock 64kHz, 8kHz, and 400Hz Outputs in Composite Clock Mode 8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola Serial (SPI) Control Port and Hardware Control
Mode Provides LOS, AIS, and LOF Indications through
Hardware Output Pins Fast Transmitter Output Disable through Device Pin for Protection Switching IEEE 1149.1 JTAG Boundary Scan 3.3V Supply with 5V Tolerant Inputs and Outputs Pin and Software Compatible with the DS26502
and DS26503
ORDERING INFORMATION
DS26504
T1/E1/J1/64KCC BITS Element
DS26502 T1/E1/J1/64KCC BITS Element
TABLE OF CONTENTS
1. FEATURES............................................................................................................................7 1.1 GENERAL..................................................................................................................................7
1.2 LINE INTERFACE........................................................................................................................7
1.3 JITTER ATTENUATOR (T1/E1 MODES ONLY)................................................................................7 1.4 FRAMER/FORMATTER.................................................................................................................8
1.5 TEST AND DIAGNOSTICS.............................................................................................................8
1.6 CONTROL PORT.........................................................................................................................8
2. SPECIFICATIONS COMPLIANCE...............................................................................9
3. BLOCK DIAGRAMS.........................................................................................................11
4. PIN FUNCTION DESCRIPTION...................................................................................14 4.1 TRANSMIT PLL........................................................................................................................14 4.2 TRANSMIT SIDE.......................................................................................................................14
4.3 RECEIVE SIDE.........................................................................................................................15
4.4 CONTROLLER INTERFACE.........................................................................................................16 4.5 JTAG......................................................................................................................................20
4.6 LINE INTERFACE......................................................................................................................21 4.7 POWER...................................................................................................................................21
5. PINOUT.................................................................................................................................22
6. HARDWARE CONTROLLER INTERFACE............................................................25 6.1 TRANSMIT CLOCK SOURCE.......................................................................................................25
6.2 INTERNAL TERMINATION...........................................................................................................25
6.3 LINE BUILD-OUT......................................................................................................................26 6.4 RECEIVER OPERATING MODES.................................................................................................27
6.5 TRANSMITTER OPERATING MODES...........................................................................................27
6.6 MCLK PRE-SCALER................................................................................................................28 6.7 PAYLOAD CLOCK OUTPUT........................................................................................................28
6.8 OTHER HARDWARE CONTROLLER MODE FEATURES..................................................................29
7. PROCESSOR INTERFACE...........................................................................................30 7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION..............................................................................30 7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION..........................................................30
7.2.1 Clock Phase and Polarity.....................................................................................................................30 7.2.2 Bit Order...............................................................................................................................................30
7.2.3 Control Byte.........................................................................................................................................30 7.2.4 Burst Mode...........................................................................................................................................30
7.2.5 Register Writes.....................................................................................................................................31 7.2.6 Register Reads....................................................................................................................................31
7.3 REGISTER MAP........................................................................................................................32 7.3.1 Power-Up Sequence............................................................................................................................34
7.3.2 Test Reset Register.............................................................................................................................34 7.3.3 Mode Configuration Register...............................................................................................................35
7.4 INTERRUPT HANDLING..............................................................................................................37
7.5 STATUS REGISTERS.................................................................................................................37 7.6 INFORMATION REGISTERS........................................................................................................38
7.7 INTERRUPT INFORMATION REGISTERS.......................................................................................38
DS26504 T1/E1/J1/64KCC BITS Element
8. T1 FRAMER/FORMATTER CONTROL REGISTERS.........................................39 8.1 T1 CONTROL REGISTERS.........................................................................................................39
9. E1 FRAMER/FORMATTER CONTROL REGISTERS........................................45 9.1 E1 CONTROL REGISTERS.........................................................................................................45
9.2 E1 INFORMATION REGISTERS...................................................................................................48
10. I/O PIN CONFIGURATION OPTIONS.......................................................................52
11. T1 SYNCHRONIZATION STATUS MESSAGE.....................................................55 11.1 T1 BIT-ORIENTED CODE (BOC) CONTROLLER..........................................................................55 11.2 TRANSMIT BOC.......................................................................................................................55
11.3 RECEIVE BOC.........................................................................................................................56
12. E1 SYNCHRONIZATION STATUS MESSAGE.....................................................64 12.1 SA/SI BIT ACCESS BASED ON CRC4 MULTIFRAME....................................................................64 12.1.1 Sa Bit Change of State.........................................................................................................................65
12.2 ALTERNATE SA/SI BIT ACCESS BASED ON DOUBLE-FRAME........................................................76
13. LINE INTERFACE UNIT (LIU)......................................................................................79 13.1 LIU OPERATION.......................................................................................................................80
13.2 LIU RECEIVER.........................................................................................................................80
13.2.1 Receive Level Indicator........................................................................................................................80 13.2.2 Receive G.703 Section 10 Synchronization Signal.............................................................................81
13.2.3 Monitor Mode.......................................................................................................................................81 13.3 LIU TRANSMITTER...................................................................................................................81
13.3.1 Transmit Short-Circuit Detector/Limiter................................................................................................82 13.3.2 Transmit Open-Circuit Detector...........................................................................................................82
13.3.3 Transmit BPV Error Insertion...............................................................................................................82 13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)...........................................................82
13.4 MCLK PRE-SCALER................................................................................................................82
13.5 JITTER ATTENUATOR................................................................................................................82 13.6 CMI (CODE MARK INVERSION) OPTION.....................................................................................83
13.7 LIU CONTROL REGISTERS........................................................................................................84
13.8 RECOMMENDED CIRCUITS........................................................................................................92 13.9 COMPONENT SPECIFICATIONS..................................................................................................94
14. LOOPBACK CONFIGURATION..................................................................................98
15. 64KHZ SYNCHRONIZATION INTERFACE............................................................99 15.1 RECEIVE 64KHZ SYNCHRONIZATION INTERFACE OPERATION......................................................99
15.2 TRANSMIT 64KHZ SYNCHRONIZATION INTERFACE OPERATION..................................................100
16. 6312KHZ SYNCHRONIZATION INTERFACE.....................................................101 16.1 RECEIVE 6312KHZ SYNCHRONIZATION INTERFACE OPERATION................................................101
16.2 TRANSMIT 6312KHZ SYNCHRONIZATION INTERFACE OPERATION..............................................101
17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT..............102 17.1 INSTRUCTION REGISTER.........................................................................................................106 17.2 TEST REGISTERS...................................................................................................................107
DS26504 T1/E1/J1/64KCC BITS Element
17.5 IDENTIFICATION REGISTER.....................................................................................................107
18. FUNCTIONAL TIMING DIAGRAMS.........................................................................110 18.1 PROCESSOR INTERFACE........................................................................................................110 18.1.1 Parallel Port Mode..............................................................................................................................110
18.1.2 SPI Serial Port Mode..........................................................................................................................110
19. OPERATING PARAMETERS.....................................................................................113
20. AC TIMING PARAMETERS AND DIAGRAMS....................................................115 20.1 MULTIPLEXED BUS.................................................................................................................115 20.2 NONMULTIPLEXED BUS..........................................................................................................118
20.3 SERIAL BUS...........................................................................................................................121
20.4 RECEIVE SIDE AC CHARACTERISTICS.....................................................................................123 20.5 TRANSMIT SIDE AC CHARACTERISTICS...................................................................................125
21. REVISION HISTORY......................................................................................................127
22. PACKAGE INFORMATION.........................................................................................128
DS26504 T1/E1/J1/64KCC BITS Element
LIST OF FIGURES Figure 3-1. Block Diagram.........................................................................................................................................11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only).........................................................................................12 Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................................12
Figure 3-4. Master Clock PLL Diagram.....................................................................................................................13 Figure 13-1. Basic Network Connection....................................................................................................................79
Figure 13-2. Typical Monitor Application...................................................................................................................81 Figure 13-3. CMI Coding...........................................................................................................................................83
Figure 13-4. Basic Interface.......................................................................................................................................92 Figure 13-5. Protected Interface Using Internal Receive Termination......................................................................93
Figure 13-6. E1 Transmit Pulse Template.................................................................................................................95 Figure 13-7. T1 Transmit Pulse Template.................................................................................................................95
Figure 13-8. Jitter Tolerance (T1 Mode)....................................................................................................................96 Figure 13-9. Jitter Tolerance (E1 Mode)....................................................................................................................96
Figure 13-10. Jitter Attenuation (T1 Mode)................................................................................................................97 Figure 13-11. Jitter Attenuation (E1 Mode)...............................................................................................................97
Figure 15-1. 64kHz Composite Clock Mode Signal Format......................................................................................99 Figure 17-1. JTAG Functional Block Diagram.........................................................................................................102
Figure 17-2. TAP Controller State Diagram.............................................................................................................105 Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0...............................................................110
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0...............................................................110 Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1...............................................................110
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1...............................................................111 Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0...............................................................111
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0...............................................................111 Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1...............................................................112
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1...............................................................112 Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)...............................................................................116
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)................................................................................116 Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)...................................................................................117
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)................................................................................119 Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)................................................................................119
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01).........................................................................120 Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01).........................................................................120
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10....................................................................122 Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10....................................................................122
Figure 20-10. Receive TimingT1, E1, 64KCC Mode............................................................................................124 Figure 20-11. Transmit TimingT1, E1, 64KCC Mode...........................................................................................126
