DS26401 ,Octal T1/E1/J1 FramerAPPLICATIONS One HDLC Controller per Framer Line Cards Routers RAI-CI and AIS-CI Support Add- ..
DS26401+ ,Octal T1/E1/J1 FramerAPPLICATIONS One HDLC Controller per Framer Line Cards Routers RAI-CI and AIS-CI Support Add- ..
DS26401DK ,Octal T1/E1/J1 Framer Design Kit Daughter CardFEATURES The DS26401DK is an easy-to-use evaluation board Demonstrates Key Functions of the DS264 ..
DS26401N ,Octal T1/E1/J1 FramerAPPLICATIONS One HDLC Controller per Framer Line Cards Routers RAI-CI and AIS-CI Support Add- ..
DS26502 ,T1/E1/J1/64KCC BITS ElementBLOCK DIAGRAMS...... 11 4. PIN FUNCTION DESCRIPTION.. 14 4.1 TRANSMIT PLL ... 14 4.2 TRANSMIT SIDE ..
DS26502DK ,T1/E1/J1/64KCC Bits Element Design Kit DS26502DK T1/E1/J1/64KCC Bits Element Design Kit
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26401
Octal T1/E1/J1 Framer
GENERAL DESCRIPTION The DS26401 is an octal, software-selectable T1, E1
or J1 framer. It is composed of eight framer/formatters
and a system (backplane) interface. Each framer has
an HDLC controller that can be mapped to any DS0
or FDL (T1)/Sa (E1) bit. The DS26401 also includes a
full-feature BERT device, which can be used with any
of the eight T1/E1 ports, and an internal clock adapter
useful for creating synchronous, high frequency
backplane timing. The DS26401 is controlled through
an 8-bit parallel port that can be configured for
nonmultiplexed Intel or Motorola operation.
APPLICATIONS Line Cards Routers
Add-Drop Multiplexers IMA
DSLAMs ATM
Timing Systems WAN Interface
PBXs
Switches
Customer-Premise
Equipment
Central Office Equipment
Go to /telecom for a complete list of
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
FEATURES 8 Independent, Full-Featured T1/E1/J1
Framers/Formatters Independent Transmit and Receive Paths Flexible Signaling Extraction and Insertion Alarm Detection and Insertion Transmit Synchronizer AMI, B8ZS, HDB3, NRZ Line Coding Performance Monitor Counters BOC Message Controller (T1) Two-Frame Elastic Store Buffers for Each
Transmitter and Receiver One HDLC Controller per Framer RAI-CI and AIS-CI Support Full-Feature BERT can be Mapped to Any Port Flexible TDM Backplane Supports Bus Rates
from 1.544MHz to 16.384MHz Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz JTAG Test Port Single 3.3V Supply with 5V Tolerant Inputs 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS26401 0°C to +70°C 256 BGA
DS26401N -40°C to +85°C 256 BGA
DS26401
Octal T1/E1/J1 Framer
DS26401 Octal T1/E1/J1 Framer
TABLE OF CONTENTS
1. APPLICABLE STANDARDS........................................................................................................7
2. FEATURES..................................................................................................................................8 2.1 FRAMER/FORMATTER.....................................................................................................................................8
2.2 SYSTEM INTERFACE........................................................................................................................................8
2.3 HDLC CONTROLLERS....................................................................................................................................9
2.4 TEST AND DIAGNOSTICS.................................................................................................................................9
2.5 CONTROL PORT..............................................................................................................................................9
3. BLOCK DIAGRAMS...................................................................................................................10
4. SIGNAL LIST (SORTED BY SIGNAL NAME)............................................................................13
5. SIGNAL DESCRIPTIONS...........................................................................................................17 5.1 RECEIVE FRAMER SIGNALS...........................................................................................................................17
5.2 TRANSMIT FRAMER SIGNALS.........................................................................................................................19
5.3 PARALLEL CONTROL PORT............................................................................................................................20
5.4 SYSTEM INTERFACE......................................................................................................................................21
5.5 TEST............................................................................................................................................................22
6. REGISTER MAP.........................................................................................................................23
7. GLOBAL FUNCTIONS...............................................................................................................24 7.1 GLOBAL REGISTERS.....................................................................................................................................24
7.2 GLOBAL REGISTER DESCRIPTION AND OPERATION........................................................................................25
7.3 IBO MULTIPLEXER........................................................................................................................................27
7.4 INTERRUPT TREE..........................................................................................................................................37
8. T1 RECEIVER............................................................................................................................38 8.1 T1 RECEIVER REGISTER MAP.......................................................................................................................38
8.2 T1 RECEIVE FRAMER DESCRIPTION AND OPERATION.....................................................................................43
8.3 RECEIVE MASTER-MODE REGISTER..............................................................................................................44
8.4 INTERRUPT INFORMATION REGISTER.............................................................................................................44
8.5 T1 RECEIVE CONTROL REGISTERS...............................................................................................................45
8.6 H.100 (CT BUS) COMPATIBILITY...................................................................................................................50
8.7 T1 RECEIVE STATUS AND INFORMATION........................................................................................................52
8.8 T1 RECEIVE-SIDE DIGITAL MILLIWATT CODE GENERATION............................................................................63
8.9 T1 ERROR COUNT REGISTERS......................................................................................................................64
8.10 DS0 MONITORING FUNCTION....................................................................................................................69
8.11 T1 RECEIVE SIGNALING OPERATION..........................................................................................................70
8.12 T1 RECEIVE PER-CHANNEL IDLE CODE INSERTION....................................................................................76
8.13 RECEIVE-CHANNEL BLOCKING OPERATION................................................................................................77
8.14 RECEIVE ELASTIC STORES OPERATION.....................................................................................................78
8.15 FRACTIONAL T1 SUPPORT (GAPPED-CLOCK MODE)...................................................................................82
8.16 T1 BIT-ORIENTED CODE (BOC) CONTROLLER...........................................................................................83
8.17 RECEIVE SLC-96 OPERATION...................................................................................................................85
8.18 RECEIVE FDL...........................................................................................................................................86
8.19 PROGRAMMABLE IN-BAND LOOP-CODE DETECTION...................................................................................87
8.20 RECEIVE HDLC CONTROLLER...................................................................................................................92
8.21 INTERLEAVED PCM BUS OPERATION (IBO).............................................................................................100
8.22 INTERFACING THE T1 RX FRAMER TO THE BERT.....................................................................................102
9. T1 TRANSMIT..........................................................................................................................104
DS26401 Octal T1/E1/J1 Framer
9.2 T1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION...........................................................................108
9.3 TRANSMIT-MASTER MODE REGISTER..........................................................................................................109
9.4 INTERRUPT INFORMATION REGISTERS.........................................................................................................109
9.5 T1 TRANSMIT CONTROL REGISTERS...........................................................................................................110
9.6 T1 TRANSMIT STATUS AND INFORMATION....................................................................................................115
9.7 T1 PER-CHANNEL LOOPBACK.....................................................................................................................118
9.8 T1 TRANSMIT DS0 MONITORING FUNCTION................................................................................................119
9.9 T1 TRANSMIT SIGNALING OPERATION.........................................................................................................120
9.10 T1 TRANSMIT PER-CHANNEL IDLE CODE INSERTION................................................................................123
9.11 T1 TRANSMIT CHANNEL BLOCKING REGISTERS........................................................................................124
9.12 T1 TRANSMIT ELASTIC STORES OPERATION............................................................................................125
ELASTIC STORE DELAY AFTER INITIALIZATION........................................................................................................126
9.13 FRACTIONAL T1 SUPPORT (GAPPED CLOCK MODE).................................................................................129
9.14 T1 TRANSMIT BIT ORIENTED CODE (BOC) CONTROLLER.........................................................................130
9.15 T1 TRANSMIT FDL..................................................................................................................................131
9.16 TRANSMIT SLC96 OPERATION..............................................................................................................132
9.17 TRANSMIT HDLC CONTROLLER...............................................................................................................133
9.18 HDLC TRANSMIT EXAMPLE.....................................................................................................................141
9.19 PROGRAMMABLE IN-BAND LOOP-CODE GENERATOR................................................................................142
9.20 INTERLEAVED PCM BUS OPERATION (IBO).............................................................................................144
9.21 INTERFACING THE T1 TX FORMATTER TO THE BERT................................................................................146
9.22 T1 TRANSMIT SYNCHRONIZER.................................................................................................................148
10. E1 RECEIVER..........................................................................................................................150 10.1 E1 RECEIVER REGISTER MAP.................................................................................................................150
10.2 E1 RECEIVE FRAMER DESCRIPTION AND OPERATION...............................................................................155
10.3 RECEIVE MASTER MODE REGISTER.........................................................................................................156
10.4 INTERRUPT INFORMATION REGISTERS......................................................................................................157
10.5 E1 RECEIVE CONTROL REGISTERS.........................................................................................................158
10.6 H.100 (CT BUS) COMPATIBILITY.............................................................................................................162
10.7 E1 RECEIVE STATUS AND INFORMATION..................................................................................................164
10.8 E1 ERROR COUNT REGISTERS................................................................................................................175
10.9 DS0 MONITORING FUNCTION..................................................................................................................181
10.10 E1 RECEIVE SIGNALING OPERATION........................................................................................................182
10.11 E1 RECEIVE PER-CHANNEL IDLE CODE INSERTION..................................................................................187
10.12 RECEIVE CHANNEL BLOCKING OPERATION...............................................................................................188
10.13 RECEIVE ELASTIC STORES OPERATION...................................................................................................189
ELASTIC STORE DELAY AFTER INITIALIZATION........................................................................................................192
10.14 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE).................................................................................193
10.15 ADDITIONAL SA-BIT AND SI-BIT RECEIVE OPERATION (E1 MODE).............................................................194
10.16 RECEIVE HDLC CONTROLLER.................................................................................................................200
HDLC RECEIVE EXAMPLE.....................................................................................................................................207
10.17 INTERLEAVED PCM BUS OPERATION (IBO).............................................................................................208
10.18 INTERFACING THE E1 RX FRAMER TO THE BERT.....................................................................................210
11. E1 TRANSMIT..........................................................................................................................212 11.1 E1 TRANSMIT REGISTER MAP.................................................................................................................212
11.2 E1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION.......................................................................216
11.3 TRANSMIT MASTER MODE REGISTER.......................................................................................................217
11.4 INTERRUPT INFORMATION REGISTERS......................................................................................................218
11.5 E1 TRANSMIT CONTROL REGISTERS.......................................................................................................219
11.6 AUTOMATIC ALARM GENERATION............................................................................................................221
11.7 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)......................................................................223
11.8 E1 TRANSMIT STATUS AND INFORMATION................................................................................................225
11.9 PER-CHANNEL LOOPBACK.......................................................................................................................228
11.10 E1 TRANSMIT DS0 MONITORING FUNCTION.............................................................................................229
DS26401 Octal T1/E1/J1 Framer
11.13 E1 TRANSMIT CHANNEL BLOCKING REGISTERS.......................................................................................234
11.14 E1 TRANSMIT ELASTIC STORES OPERATION............................................................................................235
ELASTIC STORE DELAY AFTER INITIALIZATION........................................................................................................236
11.15 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE).................................................................................239
11.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 MODE)....................................................240
11.17 TRANSMIT HDLC CONTROLLER...............................................................................................................247
11.18 HDLC TRANSMIT EXAMPLE.....................................................................................................................255
11.19 INTERLEAVED PCM BUS OPERATION (IBO).............................................................................................256
11.20 INTERFACING THE E1 TRANSMITTER TO THE BERT..................................................................................258
11.21 E1 TRANSMIT SYNCHRONIZER.................................................................................................................260
12. BERT........................................................................................................................................262 12.1 BERT REGISTERS..................................................................................................................................262
12.2 BERT DESCRIPTION AND OPERATION.....................................................................................................263
12.3 PATTERN GENERATION...........................................................................................................................264
12.4 PATTERN SYNCHRONIZATION...................................................................................................................265
12.5 BER CALCULATION.................................................................................................................................265
12.6 ERROR GENERATION..............................................................................................................................265
12.7 BERT CONTROL REGISTERS..................................................................................................................267
12.8 BERT STATUS REGISTER.......................................................................................................................271
12.9 PSEUDORANDOM PATTERN REGISTERS...................................................................................................272
12.10 COUNT REGISTERS.................................................................................................................................274
12.11 RAM ACCESS.........................................................................................................................................275
13. FUNCTIONAL TIMING.............................................................................................................276 13.1 DELAYS..................................................................................................................................................276
13.2 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS.........................................................................................277
13.3 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS...................................................................................282
13.4 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS.........................................................................................286
13.5 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS...................................................................................288
14. OPERATING PARAMETERS...................................................................................................291
15. TIMING.....................................................................................................................................292 15.1 MICROPROCESSOR BUS AC CHARACTERISTICS.......................................................................................292
15.2 RECEIVER AC CHARACTERISTICS............................................................................................................295
15.3 TRANSMIT AC CHARACTERISTICS............................................................................................................298
15.4 JTAG INTERFACE TIMING.......................................................................................................................301
15.5 SYSTEM CLOCK AC CHARACTERISTICS...................................................................................................301
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................302 16.1 TAP CONTROLLER STATE MACHINE........................................................................................................303
16.2 INSTRUCTION REGISTER..........................................................................................................................306
16.3 TEST REGISTERS....................................................................................................................................307
17. PACKAGE INFORMATION......................................................................................................308
18. THERMAL INFORMATION......................................................................................................309
19. REVISION HISTORY................................................................................................................309 DS26401 Octal T1/E1/J1 Framer
LIST OF FIGURES Figure 3-1. Block Diagram........................................................................................................................................10
Figure 3-2. Typical PLL Connection..........................................................................................................................11
Figure 3-3. Typical Bipolar Network-Side Interface to Framers................................................................................11
Figure 3-4. Typical NRZ Network-Side Interface to Framers....................................................................................12
Figure 7-1. Internal IBO Multiplexer Equivalent Circuit4.096MHz.........................................................................28
Figure 7-2. Internal IBO Multiplexer Equivalent Circuit8.192MHz.........................................................................29
Figure 7-3. Internal IBO Multiplexer Equivalent Circuit16.394MHz......................................................................30
Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode..................................................................................................50
Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode................................................................................................51
Figure 8-3. Receive HDLC Example........................................................................................................................99
Figure 9-1. HDLC Message Transmit Example.....................................................................................................141
Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode..............................................................................................162
Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode............................................................................................163
Figure 10-3. Receive HDLC Example....................................................................................................................207
Figure 11-1. HDLC Message Transmit Example....................................................................................................255
Figure 12-1. Shared BERT Block Diagram.............................................................................................................266
Figure 13-1. T1 Receive-Side D4 Timing...............................................................................................................277
Figure 13-2. T1 Receive-Side ESF Timing.............................................................................................................277
Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled).............................................................278
Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................278
Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................279
Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode...................................................................280
Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode................................................................281
Figure 13-8. T1 Transmit-Side D4 Timing..............................................................................................................282
Figure 13-9. T1 Transmit-Side ESF Timing............................................................................................................282
Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................283
Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..........................................283
Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..........................................284
Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode................................................................284
Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode.....................................................................285
Figure 13-15. E1 Receive-Side Timing...................................................................................................................286
Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................286
Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................287
Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................287
Figure 13-19. E1 Transmit-Side Timing..................................................................................................................288
Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................288
Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled).........................................289
Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..........................................289
Figure 13-23. E1 G.802 Timing...............................................................................................................................290
Figure 15-1. Intel Bus Read Timing (BTS = 0).......................................................................................................293
Figure 15-2. Intel Bus Write Timing (BTS = 0).......................................................................................................293
Figure 15-3. Motorola Bus Read Timing (BTS = 1)...............................................................................................294
Figure 15-4. Motorola Bus Write Timing (BTS = 1)...............................................................................................294
Figure 15-5. Receive Framer TimingBackplane (T1 Mode)...............................................................................295
Figure 15-6. Receive-Side TimingElastic Store Enabled (T1 Mode)..................................................................296
Figure 15-7. Receive Framer TimingLine Side..................................................................................................297
Figure 15-8. Transmit Formatter TimingBackplane...........................................................................................299
Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled...........................................................................300
Figure 15-10. Transmit Formatter TimingLine Side...........................................................................................300
Figure 15-11. JTAG Interface Timing Diagram.......................................................................................................301
Figure 16-1. JTAG Functional Block Diagram........................................................................................................302
Figure 16-2. Tap Controller State Diagram............................................................................................................303
