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EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
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EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26334-DS26334G-DS26334GN
3.3V, 16-Channel, E1/T1/J1 Short and Long-Haul Line Interface Unit
GENERAL DESCRIPTION The DS26334 is a 16-channel short/long-haul line interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A single bill of material can support E1/T1/J1 with minimum external
components. Redundancy is supported through nonintrusive monitoring, optimal high impedance
modes and configurable 1:1 or 1+1 backup enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of various frequencies. Two clock output references are
also offered. The device is offered in a 256-pin TEBGA, the smallest package available for a 16-
channel LIU.
APPLICATIONS T1 Digital Cross-Connects
ATM and Frame Relay Equipment Wireless Base Stations
ISDN Primary Rate Interface E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
FEATURES ��16 E1, T1, or J1 Short/Long-Haul Line Interface
Units
��Independent E1, T1 or J1 Selections
��Software-Selectable Transmit and Receive-Side Impedance Matching
��Crystal Less Jitter Attenuator
��Selectable Single-Rail and Dual-Rail Mode and AMI or HDB3/ B8ZS Line Encoding and
Decoding
��Detection and Generation of AIS
��Digital/Analog Loss of Signal Detection as per T1.231, G.775 and ETSI 300233
��External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1 Operation. This Clock will be Internally Adapted
for T1 or E1 Usage.
��Receiver Signal Level Indicator from -2.5dB to -38dB in T1 Mode and 3dB to 43dB in E1
Mode in 2.5dB Increments ��Two Built-In BERT Testers for Diagnostics
��8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
��Transmit Short Circuit Protection
��G.772 Nonintrusive Monitoring
��Receive Monitor Mode Handles Combinations of 14dB to 30dB of Resistive Attenuation Along with
12dB to 30dB of Cable Attenuation ��Specification Compliance to the Latest T1 and
E1 StandardsANSI T1.102, AT&T Pub 62411,
T1.231, T1.403, ITU G.703, G.742, G.775, G.823, ETSI 300 166, and ETSI 300 233
��Single 3.3V Supply with 5V Tolerant I/O
��JTAG Boundary Scan as per IEEE 1149.1
ORDERING INFORMATION
DS26334
3.3V, 16-Channel, E1/T1/J1 Short-
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
TABLE OF CONTENTS
1 STANDARDS COMPLIANCE........................................................................................................6 1.1 TELECOM SPECIFICATIONS COMPLIANCE.......................................................................................6
2 DETAILED DESCRIPTION............................................................................................................7
3 BLOCK DIAGRAMS......................................................................................................................8
4 PIN DESCRIPTION......................................................................................................................10
5 FUNCTIONAL DESCRIPTION.....................................................................................................18 5.1 PORT OPERATION......................................................................................................................18
5.1.1 Serial Port Operation..............................................................................................................................18 5.1.2 Parallel Port Operation...........................................................................................................................19
5.1.3 Interrupt Handling...................................................................................................................................19 5.2 POWER-UP AND RESET..............................................................................................................20
5.3 MASTER CLOCK.........................................................................................................................20 5.4 TRANSMITTER............................................................................................................................21
5.4.1 Transmit Line Templates........................................................................................................................23
5.4.2 LIU Transmit Front End..........................................................................................................................26 5.4.3 Dual Rail.................................................................................................................................................27
5.4.4 Single-Rail Mode....................................................................................................................................27 5.4.5 Zero SuppressionB8ZS or HDB3.......................................................................................................27
5.4.6 Transmit Power-Down............................................................................................................................27 5.4.7 Transmit All Ones...................................................................................................................................28 5.4.8 Drive Failure Monitor..............................................................................................................................28
5.5 RECEIVER..................................................................................................................................28
5.5.1 Receiver Monitor Mode..........................................................................................................................28 5.5.2 Peak Detector and Slicer.......................................................................................................................28
5.5.3 Receive Level Indicator..........................................................................................................................28 5.5.4 Clock and Data Recovery......................................................................................................................29
5.5.5 Loss of Signal.........................................................................................................................................29 5.5.6 AIS..........................................................................................................................................................30
5.5.7 Bipolar Violation and Excessive Zero Detector......................................................................................31 5.6 JITTER ATTENUATOR..................................................................................................................31
5.7 G.772 MONITOR........................................................................................................................32
5.8 LOOPBACKS...............................................................................................................................32 5.8.1 Analog Loopback....................................................................................................................................32
5.8.2 Digital Loopback.....................................................................................................................................33 5.8.3 Remote Loopback..................................................................................................................................34
5.9 BERT........................................................................................................................................34 5.9.1 General Description................................................................................................................................34
5.9.2 Configuration and Monitoring.................................................................................................................35 5.9.3 Receive Pattern Detection.....................................................................................................................36
5.9.4 Transmit Pattern Generation..................................................................................................................38
6 REGISTER MAPS AND DEFINITION..........................................................................................39 6.1 REGISTER DESCRIPTION.............................................................................................................48
6.1.1 Primary Register Bank...........................................................................................................................48 6.1.2 Secondary Register Bank......................................................................................................................61
6.1.3 Individual LIU Register Bank..................................................................................................................64 6.1.4 BERT Registers......................................................................................................................................81
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT.................................88 7.1 TAP CONTROLLER STATE MACHINE............................................................................................89
7.2 INSTRUCTION REGISTER.............................................................................................................92
7.3 TEST REGISTERS.......................................................................................................................93
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DC ELECTRICAL CHARACTERIZATION...................................................................................94
9 AC TIMING CHARACTERISTICS................................................................................................95 9.1 LINE INTERFACE CHARACTERISTICS............................................................................................95 9.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS...............................................................96
9.3 SERIAL PORT...........................................................................................................................108 9.4 SYSTEM TIMING.......................................................................................................................109
9.5 JTAG TIMING..........................................................................................................................111
10 PIN ASSIGNMENT.....................................................................................................................112
11 PACKAGE INFORMATION........................................................................................................113
12 THERMAL INFORMATION........................................................................................................114
13 REVISION HISTORY..................................................................................................................115
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
LIST OF FIGURES Figure 3-1. Block Diagram...........................................................................................................................................8
Figure 3-2. Receive Logic Detail..................................................................................................................................9 Figure 3-3. Transmit Logic Detail.................................................................................................................................9
Figure 5-1. Serial Port Operation for Write Access...................................................................................................18 Figure 5-2. Serial Port Operation for Read Access with CLKE = 0...........................................................................18
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1...........................................................................19 Figure 5-4. Interrupt Handling Flow Diagram............................................................................................................20
Figure 5-5. Pre-Scaler PLL and Clock Generator......................................................................................................21 Figure 5-6. T1 Transmit Pulse Templates.................................................................................................................24
Figure 5-7. E1 Transmit Pulse Templates.................................................................................................................25 Figure 5-8. LIU Front End..........................................................................................................................................26
Figure 5-9. Jitter Attenuation.....................................................................................................................................32 Figure 5-10. Analog Loopback...................................................................................................................................33
Figure 5-11 Digital Loopback.....................................................................................................................................33 Figure 5-12. Remote Loopback.................................................................................................................................34
Figure 5-13. PRBS Synchronization State Diagram..................................................................................................36 Figure 5-14. Repetitive Pattern Synchronization State Diagram...............................................................................37
Figure 7-1. JTAG Functional Block Diagram.............................................................................................................88 Figure 7-2. TAP Controller State Diagram.................................................................................................................91
Figure 9-1. Intel Nonmuxed Read Cycle...................................................................................................................97 Figure 9-2. Intel Mux Read Cycle..............................................................................................................................98
Figure 9-3. Intel Nonmux Write Cycle......................................................................................................................100 Figure 9-4. Intel Mux Write Cycle............................................................................................................................101
Figure 9-5. Motorola Nonmux Read Cycle..............................................................................................................103 Figure 9-6. Motorola Mux Read Cycle.....................................................................................................................104
Figure 9-7. Motorola Nonmux Write Cycle..............................................................................................................106 Figure 9-8. Motorola Mux Write Cycle.....................................................................................................................107
Figure 9-9. Serial Bus Timing Write Operation........................................................................................................108 Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0..............................................................................108
Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1..............................................................................108 Figure 9-12. Transmitter Systems Timing................................................................................................................109
Figure 9-13. Receiver Systems Timing...................................................................................................................110 Figure 9-14. JTAG Timing.......................................................................................................................................111
Figure 10-1. 256-Ball TEBGA..................................................................................................................................112
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
LIST OF TABLES Table 4-1. Pin Descriptions........................................................................................................................................10
Table 5-1. Parallel Port Mode Selection and Pin Functions......................................................................................19 Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters............................................22
Table 5-3. Registers Related to Control of DS26334 Transmitters...........................................................................22 Table 5-4. Template Selections for Short-Haul Mode...............................................................................................23
Table 5-5. Template Selections for Long-Haul Mode................................................................................................23 Table 5-6. LIU Front-End Values...............................................................................................................................27
Table 5-7. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications...............................................................29 Table 5-8. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications.................................................................30
Table 5-9. AIS Detection and Reset Criteria for DS26334........................................................................................30 Table 5-10. Registers Related to AIS Detection........................................................................................................30
Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting...................................................................31 Table 5-12. Pseudorandom Pattern Generation........................................................................................................35
Table 5-13. Repetitive Pattern Generation................................................................................................................35 Table 6-1. Primary Register Set................................................................................................................................40
Table 6-2. Secondary Register Set............................................................................................................................41 Table 6-3. Individual LIU Register Set.......................................................................................................................42
Table 6-4. BERT Register Set...................................................................................................................................43 Table 6-5. Primary Register Set Bit Map...................................................................................................................44
Table 6-6. Secondary Register Set Bit Map..............................................................................................................45 Table 6-7. Individual LIU Register Set Bit Map..........................................................................................................46
Table 6-8. BERT Register Bit Map............................................................................................................................47 Table 6-9. G.772 Monitoring Control (LIU 1).............................................................................................................53
Table 6-10. G.772 Monitoring Control (LIU 9)...........................................................................................................53 Table 6-12. TST Template Select Transmitter Register............................................................................................57
Table 6-13. TST Template Select Transmitter Register............................................................................................57 Table 6-14. Template Selection.................................................................................................................................58
Table 6-15. Address Pointer Bank Selection.............................................................................................................61 Table 6-16. DS26334 MCLK Selections....................................................................................................................67
Table 6-17. Receiver Sensitivity/Monitor Mode Gain Selection................................................................................72 Table 6-18. Receiver Signal Level.............................................................................................................................73
Table 6-19. Bit Error Rate Transceiver Select for Channels 18..............................................................................76 Table 6-20. Bit Error Rate Transceiver Select for Channels 916............................................................................76
Table 6-21. PLL Clock Select....................................................................................................................................78 Table 6-22. Clock A Select........................................................................................................................................79
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture.......................................................................................92 Table 7-2. ID Code Structure.....................................................................................................................................93
Table 7-3. Device ID Codes.......................................................................................................................................93 Table 8-1. DC Pin Logic Levels.................................................................................................................................94
Table 8-2. Pin Capacitance.......................................................................................................................................94 Table 8-3. Supply Current and Output Voltage.........................................................................................................94
Table 9-1. Transmitter Characteristics.......................................................................................................................95 Table 9-2. Receiver Characteristics...........................................................................................................................95
Table 9-3. Intel Read Mode Characteristics..............................................................................................................96 Table 9-4. Intel Write Cycle Characteristics..............................................................................................................99
Table 9-5. Motorola Read Cycle Characteristics.....................................................................................................102 Table 9-6. Motorola Write Cycle Characteristics.....................................................................................................105
Table 9-7. Serial Port Timing Characteristics..........................................................................................................108 Table 9-8. Transmitter System Timing.....................................................................................................................109
Table 9-9. Receiver System Timing.........................................................................................................................109 Table 9-10. JTAG Timing Characteristics................................................................................................................111
Table 12-1. Thermal Characteristics........................................................................................................................114
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
1 STANDARDS COMPLIANCE
1.1 Telecom Specifications compliance The DS26334 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1 and E1 Specifications and relevant sections that are applicable to the DS26334.
T1-Related Telecommunications Specifications ANSI T1.102- Digital Hierarchy Electrical Interface ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Pub 62411 High Capacity Terrestrial Digital Service ITUT G.772 Protected monitoring points provided on digital transmission systems
E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048 Kbit/s ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448 Kbit/s ITUT G.772 Protected monitoring points provided on digital transmission systems ITUT G.775 Loss of signal (LOS) and alarm indication signal (AIS) defect detection and clearance criteria ETSI 300 166 Physical and electrical characteristics of hierarchical digital interfaces for equipment using
the 2,048 kbit/s-based plesiosynchronous or synchronous digital hierarchies ETSI 300 233 Integrated Services Digital Network (ISDN) G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Pub 62411 High Capacity Terrestrial Digital Service
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
2 DETAILED DESCRIPTION The DS26334 is a single-chip, 16-channel, long-haul and short-haul line interface unit for T1 (1.544Mbps) and E1
(2.048Mbps) applications. Sixteen independent receivers and transmitters are provided in a single TEBGA package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single master
reference clock. This clock can be either 1.544MHz or 2.048MHz or multiples thereof, and either frequency can be internally adapted for T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive
paths reduces external component count. The transmit waveforms are compliant to G.703 and T1.102
specification. The DS26324 provides software-selectable internal transmit termination for 100� T1 twisted pair,
110� J1 twisted pair, 120� E1 twisted pair, and 75� E1 coaxial applications. The transmitters have fast high-
impedance capability and can be individually powered down.
The receivers can function with up to a receive signal attenuation of 36dB for T1 mode, or 43dB for E1 mode. A
monitor gain setting also can be enabled to provide 14dB, 20dB, 26dB, and 32dB of resistive gain. The DS26334 can be configured as a 14-channel LIU with channel 1 and 9 used for nonintrusive monitoring in accordance with
G.772. The receivers and transmitters can be programmed into single or dual-rail mode. AMI or HDB3/B8ZS encoding and decoding is selectable in single-rail mode. A 128-bit crystal-less on-board jitter attenuator for each
LIU can be placed in receive or transmit directions. The jitter attenuator meets the ETSI CTR12/13 ITU G.736, G.742, G.823, and AT&T PUB62411 specifications.
The DS26334 detects and generates AIS in accordance with T1.231, G.775, and ETSI 300233. Loss of signal is detected in accordance with T1.231, G.775, and ETSI 300233. The DS26334 can perform digital, analog, remote,
and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.
The DS26334 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial
port selection is also available for configuration and monitoring of the device. .
The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled
into the RTIP and RRING pins of the DS26334. The user has the option to select internal impedance matching to
75�, 100�, 110�, or 120� with the use of a single external resistor. The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator outputting the received line clock at RCLK and
data at RPOS and RNEG.
The DS26334 receivers can recover data and clock for up to 36dB of attenuation of the transmitted signals in T1
mode and 43dB for E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8. Receiver 9 can monitor the performance of receivers 10 to 16 or transmitters 10 to 16.
The DS26334 contains 16 identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to TCLK. The data at these pins can be single rail or dual rail. This data is processed by waveshaping circuitry and
the line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.
The DS26334 drives the E1 or T1 line from the TTIP and TRING pins by a 1:2 coupling transformer. The DS26334
supports the use of either a 1:1 or a 1:2 transformer on the receive side through the receiver turns ratio (RTR) bit. For long-haul applications, a 1:1 transformer is preferred. Receive internal impedance matching allows one
external resistance value to work for all T1/J1/E1 modes.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
3 BLOCK DIAGRAMS
Figure 3-1. Block Diagram DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 3-2. Receive Logic Detail
Figure 3-3. Transmit Logic Detail
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
4 PIN DESCRIPTION
Table 4-1. Pin Descriptions
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5 FUNCTIONAL DESCRIPTION
5.1 Port Operation
5.1.1 Serial Port Operation Setting MODESEL = low enables the serial bus interface on the DS26334. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 9.3 for the
AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when BSWP is low. Figure 5-1 to Figure 5-3 show operation with LSB first.
This port is compatible with the SPI interface defined for Motorola Processors. An example of this is the MMC2107 from Motorola.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next 6 bits identify the register address (A1 to A6) (A7 is ignored).
All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising
edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO
is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.
Figure 5-1. Serial Port Operation for Write Access
Figure 5-2. Serial Port Operation for Read Access with CLKE = 0
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1
5.1.2 Parallel Port Operation When using the parallel interface on the DS26334 the user has the option for either multiplexed bus operation or
nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26334 can operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.
Table 5-1. Parallel Port Mode Selection and Pin Functions
5.1.3 Interrupt Handling There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows: When status changes on an interruptible event, INTB pin will go low if the event is enabled through the
corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10k� resister for wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when
not active by setting register GISC.INTM. When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The
Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a 1 to
its bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a register without clearing them on all bits. Subsequently the host processor can read the corresponding Status Register to check the real-time status of
the event.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-4. Interrupt Handling Flow Diagram
5.2 Power-Up and Reset Internal Power_On_Reset circuitry generates a reset during power-up. All Registers are reset to the default values.
Writing to the Software Reset Register generates at least 1�s reset cycle, which has the same effect as the power-up reset.
The DS26334 can be reset by a low going pulse on the RSTB pin (see Table 4-1). A reset can also be performed in software by writing any value to the SWR register.
5.3 Master Clock The DS26334 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS Transmission uses
MCLK for Transmit All Ones Condition. See register MC to set desired incoming frequency. When the PLLE bit is set, the master clock adapter will generate both 2.048MHz (E1) and 1.544MHz (T1) clocks. If the PLLE bit is clear,
both internal reference clocks will track MCLK.
MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register CCR is used to select the clock
generated for CLKA and the TECLK. Any RCLK can also be selected as an input to the clock generator using this same register. For a detailed description of selections available see Figure 5-5.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-5. Pre-Scaler PLL and Clock Generator
5.4 Transmitter NRZ data arrives on TPOS and TNEG on the Transmit System Side. The TPOS and TNEG data is sampled on the falling edge of TCLK.
The data is encoded with HDB3 or B8ZS or NRZ encoding when single-rail mode is selected (only TPOS as the data source). When in single-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Pre-
encoded data is expected when dual-rail mode is selected. The encoded data passes through a jitter attenuator if it is enabled for the Transmit path. A digital sequencer and DAC are used to generate Transmit waveforms compliant
with T1.102 and G.703 Pulse Masks.
The line driver supports internal impedance matching for 75�, 100�, 110�, and 120� modes.
The DS26334 drivers have short and open circuit driver fail monitor detection. There is an OE pin that can high impedance the transmitter outputs for Protection Switching when low. The individual transmitters are by default in
high impedance. Register OE is used to enable the transmitters individually when the OE pin is high. The DS26334 has to have the transmitters enabled by setting the register and then pulling the OE pin high. The registers that
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters
Table 5-3. Registers Related to Control of DS26334 Transmitters DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.4.1 Transmit Line Templates The DS26334 transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse mask is shown in the Transmit Pulse Template and can be configured on an individual LIU basis. The
transmit template is selected via the TS2-TS0 bits in the TS register. Transmit impedance matching is selected using the TIMPOFF and the TIMPRM bits of the same register. When transmit impedance matching is enabled
TIMPRM will select between 75� and 120� impedance if an E1 template is selected, and between 100� and
110� impedance if a T1/J1 template is selected. In E1 mode, if 75��is selected via the TIMPRM bit, the output
pulse amplitude will be 2.37V, if 120��is selected via the TIMPRIM bit, the output pulse amplitude will be 3.0V.
The E1 pulse template is shown in Figure 5-7 and the T1 pulse template is shown in Figure 5-6.
Table 5-4. Template Selections for Short-Haul Mode
Table 5-5. Template Selections for Long-Haul Mode DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-6. T1 Transmit Pulse Templates
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-7. E1 Transmit Pulse Templates DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.4.2 LIU Transmit Front End It is recommended that the LIU for the transmitter be configured as described in Figure 5-8 and in Table 5-6.
Figure 5-8. LIU Front End
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 5-6. LIU Front-End Values Only use if necessary for application.
5.4.3 Dual Rail Dual-rail mode consists of TPOS, TNEG and TCLK pins on the system side. NRZ data is sampled on the falling edge of TCLK as shown in Figure 9-12.
Figure 9-12 The Zero substitution B8ZS or HDB3 is not allowed. The data that appears on the TPOS pin will be output on TTIP and data on the TNEG will be output on TRING after pulse shaping. Single-Rail Select Register
(SRMS) is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS and TNEG can be overwritten in the maintenance mode by setting the BERT Control Register (BTCR).
5.4.4 Single-Rail Mode Single-rail mode consists of TPOS, TNEG and TCLK pins on the System side. NRZ data is sampled on the falling
edge of TCLK as shown in Figure 9-12. The Zero substitution B8ZS or HDB3 is allowed. The TPOS data will be encoded in AMI or B8ZS/HDB3 format on the TTIP and TRING pins after pulse shaping. Single-Rail Mode Select
(SRMS) is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS can be overwritten in the maintenance mode by setting in BERT Control Register (BTCR).
5.4.5 Zero SuppressionB8ZS or HDB3 B8ZS coding is available when the device is in T1 mode (selected by TS2, TS1 and TS0 bits in the TS register). B8ZS/HDB3 coding are enabled by default in single-rail mode. Setting the LCS bit in the LCS Register disables
B8ZS/HDB3. Note that if the individual LIU is configured in E1 mode then HDB3 code substitution will be selected. Bipolar violations can be inserted via the BEIR register or Transmit Maintenance Register settings only if B8ZS or
HDB3 coding is turned off.
B8ZS substitution is defined in ANSI T1.102 and HDB3 in ITUT G.703 standards.
5.4.6 Transmit Power-Down The transmitter will be powered down if the relevant bits in the TPDE are set. The TTIP/TRING outputs will be high
impedance when TPDE is set.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.4.7 Transmit All Ones When Transmit All Ones is invoked continuous Ones are transmitted using MCLK as the Timing Reference. Data input at TPOS and TNEG is ignored.
Transmit All ones can be sent by setting bits in the TAOE Register. Also Transmit All ones will be enabled if bits in Register ATAOS are set and the corresponding receiver goes into LOS state in status register LOSS.
5.4.8 Drive Failure Monitor The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short or Open Circuit on the Secondary side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected.
The DFMS status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver failure.
5.5 Receiver The 16 receivers of DS26334 are all identical. Either a 2:1 or 1:1 transformer can be used on the receive side
(selected by the RTR bit). The DS26334 is designed to be fully software-selectable for E1 and T1/J1 without the need to change any external resistors for the receive-side. The receive impedance match settings are controlled by
the transmit template/impedance selection. See Figure 5-8 and Table 5-6 for external component values. All internal impedance matching is enabled via the RIMPON bit.
The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery
system derives E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form an 16 times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding
performance to meet jitter tolerance specifications. Dependent on selection options B8ZS/HDB3/AMI decoding is performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection
of single rail or dual rail is done by settings in the SRMS register.
The receiver is capable of recovering signals up to 36dB worth of attenuation for T1 mode, and up to 43dB for E1
mode. The receiver contains functionality to provide resistive gain up to 32 dB for monitor mode.
5.5.1 Receiver Monitor Mode The receive equalizer is equipped with monitor mode function that allows for resistive gain up to 32dB, along with cable attenuation of 6dB to 24dB as shown in the RSMM14 register.
5.5.2 Peak Detector and Slicer The Slicer determines the polarity and presence of the received data. The output of the Slicer is sent to the Clock and Data Recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for
determination of the slicing threshold.
5.5.3 Receive Level Indicator The DS26334 will report the signal strength at RTIP and RRING in increments described in Table 6-18. via register bits CnRL3-CnRL0 located in the RSL14 register.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.5.4 Clock and Data Recovery The resultant E1 or T1 clock derived from the 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16
times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding performance to meet jitter tolerance specifications.
5.5.5 Loss of Signal The DS26334 uses both the Digital and Analog loss detection method in compliance with the latest T1.231 for T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation.
LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively this can be termed as having received zeros for certain duration. The signal level and timing duration are defined in accordance with the T1.231 or G.775 or ETSI 300 233 specifications.
For short-haul mode, the Loss Detection Thresholds are based on cable loss of 18dB for both T1 and E1 modes.
For long-haul mode, the LOS Detection Threshold is based on cable loss of 38dB for T1 mode and 45dB for E1 mode.
RCLK is replaced by MCLK when the receiver detects a Loss of signal. If the AISEL bit is set in the GC register or the IAISEL bit is set, the RPOS/RNEG data is replaced by AIS. The loss state is exited when the receiver detects a certain number of ones density at a higher signal level than the loss detection level. The loss detection signal level
and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between LOS and
no LOS states.
The following table outlines the specifications governing the loss function:
Table 5-7. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications
5.5.5.1 4.5.3.1 ANSI T1.231 for T1 and J1 Modes For short-haul mode, loss is detected if the received signal level is less than 200mV for duration of 192 bit periods. LOS is reset if the all of the following criteria are met: 24 or more ones are detected in 192-bit period with a detection threshold of 300mV measured at RTIP and RRING. During the 192 bits less than 100 consecutive zeros are detected. 8 consecutive zeros are not detected if B8ZS is set.
For long-haul mode, loss is detected if the received signal level is less than 30mV for duration of 192 bit periods. LOS is reset if the all of the following criteria are met: 24 or more ones are detected in 192-bit period with a detection threshold of 40mV measured at RTIP and RRING.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.5.5.2 4.5.3.1 ITU G.775 for E1 Modes For short-haul mode, LOS is detected if the received signal level is less than 200mV for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.
For long-haul mode, LOS is detected if the received signal level is less than 12mV for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 20mV for a duration of 192 bit periods.
5.5.5.3 4.5.3.1 ETSI 200 233 for E1 Modes For short-haul mode, LOS is detected if the received signal level is less than 200mV for a continuous duration of
2048 (1ms) bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.
For long-haul mode, LOS is detected if the received signal level is less than 12mV for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 20mV for a duration of 192 bit periods.
5.5.6 AIS Table 5-8 outlines the DS26334 AIS related specifications. Table 5-9 states the AIS functionality in the DS26334.
The registers related to the AIS detection are shown in Table 5-10.
Table 5-8. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications
Table 5-9. AIS Detection and Reset Criteria for DS26334
Table 5-10. Registers Related to AIS Detection DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.5.7 Bipolar Violation and Excessive Zero Detector DS26334 detects code violations, BPV and excessive zero errors. The reporting of the errors is done through the pin RNEGn/CVn.
Excessive zeros are detected if eight consecutive zeros are detected with B8ZS enabled and four consecutive zeros are detected with HDB3 enabled. Excessive Zero detection is selectable when single-rail mode and
HDB3/B8ZS encoding/decoding is selected.
The bits in EZDE and CVDEB registers determine the combinations that are reported. Table 5-11 outlines the
functionality:
Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting
5.6 Jitter Attenuator The DS26334 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS
bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register.
The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay sensitive applications. The characteristics of the attenuation are shown in Figure 5-9. The jitter attenuator can be placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE
bits in register GC. These selections can be changed on an individual LIU basis by settings in the IJAPS and IJAE.
In order for the jitter attenuator to operate properly, a 2.048MHz or multiple thereof or 1.544MHz clock or multiple
thereof must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1 Applications. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board circuitry
adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
jittery clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer depth is 32 bits), then the DS26334 will divide the internal
nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JFLT) bits
in the IJAFLT register described.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-9. Jitter Attenuation
5.7 G.772 Monitor In this application, only 14 transceivers are functional and two transceivers are used for nonintrusive monitoring of
input and output of the other 14 channels. Channel 9 is used for 10 to 16 channels and Channel 1 is used for 2 to 8 channels. G.772 monitoring is configured by GMC Registers (Table 6-9). While monitoring channel 1 can be
configured in remote loopback and the monitored signal can be output on TTIP1 and TRING1. While monitoring channel 9 can be configured in remote loopback and the monitored signal can be output on TTIP9 and TRING9.
5.8 Loopbacks The DS26334 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote loopback, and dual loopback. Dual loopback is accomplished by turning on digital loopback and remote loopback at
the same time.
5.8.1 Analog Loopback The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at RTIP and ring is ignored in analog loopback. This is shown in Figure 5-10.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Figure 5-10. Analog Loopback
5.8.2 Digital Loopback The transmit system data TPOS and TNEG and TCLK will be looped back to output on RCLK, RPOS, and RNEG.
The data input at TPOS and TNEG will be encoded and output on TTIP and TRING. Signals at RTIP and RRING will be ignored. This loopback is conceptually shown in Figure 5-11.
Figure 5-11 Digital Loopback DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.8.3 Remote Loopback The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS and TNEG are ignored during a remote loopback. This loopback is conceptually shown in Figure 5-12.
Note: Remote loopback does not take precedence over transmit power-down and requires TCLK to operate. The transmitters will use the recovered RCLK in remote loopback. TCLK is still required because if it is removed the
transmitters will power-down (TCLK held low) or transmit all ones (TCLK held high).
Figure 5-12. Remote Loopback
5.9 BERT There are two bit error rate testers available on the DS26334. One BERT can be mapped into LIUs 18 and the other into LIUs 9-16 via the BTCR registers. The two BERTs operate independently of each other.
5.9.1 General Description The BERT is a software programmable test pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random patterns with a generation polynomial of the form xn + xy + 1, where n and y can take on values from 1 to 32 and to
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern.
Features
Programmable PRBS pattern The Pseudo Random Bit Sequence (PRBS) polynomial (xn + xy + 1) and seed are programmable (length n = 1 to 32, tap y = 1 to n 1, and seed = 0 to 2n 1).
Programmable repetitive pattern The repetitive pattern length and pattern are programmable (the length n = 1 to 32 and pattern = 0 to 2n 1).
24-bit error count and 32-bit bit count registers Programmable bit error insertion Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10n is programmable (n = 1 to 7).
Pattern synchronization at a 10-3 BER Pattern synchronization will be achieved even in the presence of a random Bit Error Rate (BER) of 10-3.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.9.2 Configuration and Monitoring Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send and receive common patterns.
Table 5-12. Pseudorandom Pattern Generation
Table 5-13. Repetitive Pattern Generation After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BCR.TNPL and BCR.RNPL
Monitoring the BERT requires reading the BSR register, which contains the Bit Error Count (BEC) bit and the Out
of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it
receives a minimum 6 bit errors within a 64-bit window. The Receive BERT Bit Count Register (RBCR) and the Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor
Update signal (e.g. BCR.LPMU). This signal will update the registers with the values of the counters since the last update and will reset the counters.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.9.3 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial xn + xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if
the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection
performs either PRBS synchronization or repetitive pattern synchronization.
5.9.3.1 Receive PRBS Synchronization PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern re-synchronization can be disabled.
See Figure 5-13 for the PRBS synchronization diagram.
Figure 5-13. PRBS Synchronization State Diagram DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.9.3.2 Receive Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be disabled.
See Figure 5-14 for the repetitive pattern synchronization state diagram.
Figure 5-14. Repetitive Pattern Synchronization State Diagram
5.9.3.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out Of Synchronization (OOS) condition is declared when the synchronization state machine
is not in the Sync state. An OOS condition is terminated when the synchronization state machine is in the Sync state.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit
count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5.9.4 Transmit Pattern Generation Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial xn + xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all
zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value
before pattern generation starts. The seed/pattern value is programmable (0 2n 1).
5.9.4.1 Transmit Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of one out of every 10n bits. The value of n is programmable (1 to 7 or off). Single bit error insertion can be initiated
from the microprocessor interface, or by the manual error insertion input (TMEI). The method of single error insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the
overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
REGISTER MAPS AND DEFINITION Six address bits are used to control the settings of the registers. In the parallel nonmultiplexed mode address [5:0]
is used. In multiplexed mode AD [5:0] is used and A [6:1] is used in the serial mode. The register space contains two independent sets of registers. The lower set of registers (LIUs 1-8) is located from address 00 hex to 1F hex
and contains controls for LIUs 1-8. The upper set of registers (LIUs 9-16) is a duplicate of the lower set, located from address 20 hex to 3F hex that controls LIUs 9-16. Each of these sets of registers consists of 4 banks
(Primary, Secondary, Individual LIU, and BERT). The ADDP register for the lower set of registers (LIUs 1-8) is located at address 1F hex. This register is used as a pointer to access the 4 banks of registers in the lower (LIUs 1-
8) register set. Similarly, the ADDP register for the upper set of registers (LIUs 9-16) is located at address 3F hex. This register is used as a pointer to access the 4 banks of registers in the upper (LIUs 9-16) register set. Setting an
ADDP register to AA hex will access the Secondary bank of registers, 01 hex will access the Individual LIU bank of registers, 02 hex will access the BERT bank of registers, and 00 hex (default on power-up) will access the Primary
bank of registers. Note that bank selection for the lower set of registers (LIUs 1-8) is controlled only by the ADDP at 1F hex and that bank selection for the upper set of registers (LIUs 9-16) is controlled only by the ADDP at 3F hex.
DS26
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40 of
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DS26
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41 of
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Register
Set
DS26
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42 of
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DS26
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43 of
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DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 6-5. Primary Register Set Bit Map DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 6-6. Secondary Register Set Bit Map DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 6-7. Individual LIU Register Set Bit Map DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 6-8. BERT Register Bit Map
Note: Underlined bits are read only. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
6.1 Register Description This is the detailed register description of each bit. Whenever the variable n in italics is used in any of the register
descriptions, it represents 116. Note that in the register descriptions, there are duplicate registers for LIUs 18 and LIUs 916. There are registers in LIUs 18 that do not have a duplicate in the register set for LIUs 916. For
these registers, only one address is listed. All other registers list two addresses, one for LIUs 18 and one for LIUs 916.
6.1.1 Primary Register Bank The ADDP register must be set to 00h to access this bank.
Register Name:
ID Register Description:
ID Register Register Address:
00h Bit # 7 6 5 4 3 2 1 0
Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Bits 7: Device CODE ID Bit 7 (ID7). This bit is one for long-haul operation.
Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device contains.
Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID2 to ID0). These bits tell the user the revision of the part. Contact the factory for details.
Register Name:
ALBC Register Description:
Analog Loopback Control Register Address (LIUs 1-8):
01h Bit # 7 6 5 4 3 2 1 0
Name
Default Register Address (LIUs 9-16):
21h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in Analog Loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. LOS
Detector is still in operation. The jitter attenuator is in use if enabled for the Transmitter or Receiver.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
RLBC Register Description:
Remote Loopback Control Register Address (LIUs 1-8):
02h Bit # 7 6 5 4 3 2 1 0
Name
Default
Register Address (LIUs 9-16):
22h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, Remote Loopback is
enabled on LIUn. The Analog Received Signal goes through the Receive Digital and is looped back to the Transmitter. The data at TPOS and TNEG is ignored. The jitter attenuator is in use if enabled.
Register Name:
TAOE Register Description:
Transmit All Ones Enable Register Address (LIUs 1-8):
03h Bit # 7 6 5 4 3 2 1 0
Name
Default Register Address (LIUs 9-16):
23h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Transmit All Ones Enable Channel n (TAOEn). When this bit is set, continuous stream of All ones on TTIP and TRING are sent on Channel n. MCLK is used as a reference clock for Transmit All Ones Signal. The data
arriving at TPOS and TNEG is ignored.
Register Name:
LOSS Register Description:
Loss of Signal Status Register Address (LIUs 1-8):
04h Bit # 7 6 5 4 3 2 1 0
Name LOS8 LOS7 LOS6 LOS5 LOS4 LOS3 LOS2 LOS1
Default
Register Address (LIUs 9-16):
24h Bit # 7 6 5 4 3 2 1 0
Name LOS16 LOS15 LOS14 LOS13 LOS12 LOS11 LOS10 LOS9
Default
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
DFMS Register Description:
Driver Fault Monitor Status Register Address (LIUs 1-8):
05h Bit # 7 6 5 4 3 2 1 0
Name DFMS8 DFMS7 DFMS6 DFMS5 DFMS4 DFMS3 DFMS2 DFMS1
Default Register Address (LIUs 9-16):
25h Bit # 7 6 5 4 3 2 1 0
Name DFMS16 DFMS15 DFMS14 DFMS13 DFMS12 DFMS11 DFMS10 DFMS9
Default
Bit 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short or open circuit at the Transmit Driver for LIUn.
Register Name:
LOSIE Register Description:
Loss of Signal Interrupt Enable Register Address (LIUs 1-8):
06h Bit # 7 6 5 4 3 2 1 0
Name
Default Register Address (LIUs 9-16):
26h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Loss of Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in LOS Status for LIUn can generate an Interrupt.
Register Name:
DFMIE Register Description:
Driver Fault Monitor Interrupt Enable Register Address (LIUs 1-8):
07h Bit # 7 6 5 4 3 2 1 0
Name
Default Register Address (LIUs 9-16):
27h Bit # 7 6 5 4 3 2 1 0
Name
Default
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
LOSIS Register Description:
Loss of Signal Interrupt Status Register Address (LIUs 1-8):
08h Bit # 7 6 5 4 3 2 1 0
Name LOSIS8 LOSIS7 LOSIS6 LOSIS5 LOSIS4 LOSIS3 LOSIS2 LOSIS1
Default Register Address (LIUs 9-16):
28h Bit # 7 6 5 4 3 2 1 0
Name LOSIS16 LOSIS15 LOSIS14 LOSIS13 LOSIS12 LOSIS11 LOSIS10 LOSIS9
Default
Bit 7 to 0: Loss of Signal Interrupt Status Channel n (LOSISn). When this bit is set, it indicates a LOS status has transition from a 0 to 1 or 1 to 0 and was detected for LIUn. The bit for LIUn is enabled by register LOSIE
(06h). This bit when latched is cleared on a read operation.
Register Name:
DFMIS Register Description:
Driver Fault Monitor Interrupt Status Register Address (LIUs 1-8):
09h Bit # 7 6 5 4 3 2 1 0
Name DFMIS8 DFMIS7 DFMIS6 DFMIS5 DFMIS4 DFMIS3 DFMIS2 DFMIS1
Default
Register Address (LIUs 9-16):
29h Bit # 7 6 5 4 3 2 1 0
Name DFMIS16 DFMIS15 DFMIS14 DFMIS13 DFMIS12 DFMIS11 DFMIS10 DFMIS9
Default
Bit 7 to 0: Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has transitioned from 0 to 1 or 1 to 0 and was detected for LIUn. The bit for LIUn is enabled by register DFMIE (07h). This bit when latched is cleared on a read operation.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
SWR Register Description:
Software Reset Register Address (LIUs 1-8):
0Ah Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be
generated that resets the lower set of registers (LIUs 1-8). All the registers will be restored to their default values. A read operation will always read back all zeros.
Register Address (LIUs 9-16):
2Ah Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be
generated that resets the upper set of registers (LIUs 9-16). All the registers will be restored to their default values. A read operation will always read back all zeros.
Register Name:
GMC Register Description:
G.772 Monitoring Control Register Address (LIUs 1-8):
0Bh Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive monitoring. Receiver 1 is used to monitor channels 2 to 8 of one receiver from RTIP2-8/RRING2-8 or of one transmitter from TTIP2-8/TRING2-8. See Table 6-9.
Register Address (LIUs 9-16):
2Bh Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive monitoring. Receiver 9 is used to monitor channels 10 to 16 of one receiver from RTIP10-16/RRING10-16 or of one
transmitter from TTIP10-16/TRING10-16. See Table 6-10
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Table 6-9. G.772 Monitoring Control (LIU 1)
Table 6-10. G.772 Monitoring Control (LIU 9) DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
DLBC Register Description:
Digital Loopback Control Register Address (LIUs 1-8):
0Ch Bit # 7 6 5 4 3 2 1 0
Name
Default
Register Address (LIUs 9-16):
2Ch Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: Digital Loopback Control Channel n (DLBCn). When this bit is set the LIUn is placed in Digital Loopback. The data at TPOS/TNEG is encoded and looped back to the decoder and output on RPOS/RNEG. The Jitter Attenuator can optionally be included in the Transmit or Receive Paths.
Register Name:
LASCS Register Description:
LOS/AIS Criteria Selection Register Address (LIUs 1-8):
0Dh Bit # 7 6 5 4 3 2 1 0
Name
Default Register Address (LIUs 9-16):
2Dh Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). This bit is used for LOS/AIS Selection Criteria for LIUn. In E1 mode, if set it uses ETSI (300233) mode selections. If reset it uses G.775 criteria. In T1/J1 mode
T1.231 criteria is selected.
Register Name:
ATAOS Register Description:
Automatic Transmit All Ones Select Register Address (LIUs 1-8):
0Eh Bit # 7 6 5 4 3 2 1 0
Name
Default
Register Address (LIUs 9-16):
2Eh Bit # 7 6 5 4 3 2 1 0
Name
Default
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
GC Register Description:
Global Configuration Register Address (LIUs 1-8):
0Fh Bit # 7 6 5 4 3 2 1 0
Name -
Default RIMPMS and RTCTL control all 16 LIUs. All other bits are for LIUs 1-8 only.
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting LOS for each channel. The individual LIU Register IAISEL settings will be ignored when this bit is set. When reset, the IAISEL register will have control.
Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the transmitters. The individual LIU Register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD
register will have control.
Bit 4: Code. If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored when this bit is set. If reset, the LCS register will have control.
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.
Bit 2: Receive Termination Control (RTCTL). If this bit is set the OE pin has been granted control over all the internal impedance matching of all the LIU Receivers. Otherwise, see the RIMPON bit.
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA will be in the Receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU by settings in Register IJAPS. Note that when bit JAE is set, the settings in Register IJAPS will be ignored.
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the IJAE register will be ignored if this register is set. If reset, the IJAE register will have control.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Address (LIUs 9-16):
2Fh Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting LOS for each channel. The individual LIU Register IAISEL settings will be ignored when this bit is set. When reset, the IAISEL register will have control.
Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the transmitters. The individual LIU Register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD
register will have control.
Bit 4: Code. If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored when this bit is set. If reset, the LCS register will have control.
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA will be in the Receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU by settings in Register IJAPS. Note that when bit JAE is set, the settings in Register IJAPS will be ignored.
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the IJAE register will be ignored if this register is set. If reset, the IJAE register will have control.
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Register Name:
TST Register Description:
Template Select Transmitter Register Register Address (LIUs 1-8):
10h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the Transceiver that the Transmit Template Select Register (hex 11) applies to for LIUs 1-8. See .
Register Address (LIUs 9-16):
30h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the Transceiver that the Transmit Template Select Register (hex 11) applies to LIUs 9-16. See Table 6-13.
Table 6-12. TST Template Select Transmitter Register
Table 6-13. TST Template Select Transmitter Register Register Name:
TS Register Description:
Template Select Register Register Address (LIUs 1-8):
11h Register Address (LIUs 9-16):
31h Bit # 7 6 5 4 3 2 1 0
Name RIMPON
Default
Bit 7: Receive Impedance Match On (RIMPON). If this bit is set Receive Impedance matching is turned ON. Otherwise the receiver is in High Z. Note that the OE pin can have control instead of this bit when the GC.RTCTL
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set all the internal Transmit Terminating Impedance is turned Off.
Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal Transmit Termination
impedance and Receive Impedance Match for E1 mode and T1/J1 mode.
0 = 75 � for E1 mode or 100 � for T1 mode.
1 = 120 � for E1 mode or 110 � for J1 mode.
Bit 2 to 0: Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the template, and the settings for various cable lengths. The impedance termination for the transmitter and impedance match for
the receiver are specified by bit TIMPRM. Short-haul or long-haul operation is selected by the SHLHS bit in the individual registers SHLHS (07). See Table 6-14 for bit selection of TS[2:0].
Table 6-14. Template Selection
