DS26303L-120+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitAPPLICATIONS 2.048MHz or 1.544MHz for T1/J1 or E1 T1 Digital Cross-Connects Operation; This Clock w ..
DS26303L-120+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitFEATURES 8 Complete E1, T1, or J1 Short-Haul Line The DS26303 is an 8-channel short-haul line Inte ..
DS26303L-75+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitBLOCK DIAGRAMS ....9 4
DS26303LN-120+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitTABLE OF CONTENTS 1 DETAILED DESCRIPTION ...6 2 TELECOM SPECIFICATIONS COMPLIANCE7 3
DS26303LN-75+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitPIN DESCRIPTION ....11 4.1 HARDWARE AND HOST PORT OPERATION .....20 4.1.1 Hardware Mode..... 20 4.1 ..
DS26324 ,3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface UnitAPPLICATIONS -20dB in 2.5dB Increments T1 Digital Cross-Connects Two Built-In BERT Testers for Di ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26303L-120+-DS26303L-75+-DS26303LN-120+-DS26303LN-75+
3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
GENERAL DESCRIPTION The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
APPLICATIONS T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM TNEG
RCLK
TPOS
TCLK
RPOS
RNEG
Software Control,
Hardware Control
and JTAG
Transmitter
Receiver
RLOS
RTIP
RRING
MODESELJtag
TTTIP
TRING
FEATURES � 8 Complete E1, T1, or J1 Short-Haul Line
Interface Units � Independent E1, T1, or J1 Selections � Internal Software-Selectable Transmit and
Receive-Side Termination � Crystal-Less Jitter Attenuator � Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding � Detection and Generation of AIS � Digital/Analog Loss-of-Signal Detection as
per T1.231, G.775, and ETS 300 233 � External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally
Adapted for T1 or E1 Use � Built-In BERT Tester for Diagnostics � 8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface � Hardware Mode Interface Support � Transmit Short-Circuit Protection � G.772 Nonintrusive Monitoring � Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
G.775, G.823, ETS 300 166, and ETS 300 233 � Single 3.3V Supply with 5V Tolerant I/O � JTAG Boundary Scan as per IEEE 1149.1 � 144-Pin eLQFP Package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS26303L-XXX 0°C to +70°C 144 eLQFP
DS26303L-XXX+ 0°C to +70°C 144 eLQFP
DS26303LN-XXX -40°C to +85°C 144 eLQFP
DS26303LN-XXX+ -40°C to +85°C 144 eLQFP
Note: When XXX is 075, the part defaults to 75Ω impedance in E1 mode; when XXX is 120, the part defaults to 120Ω impedance.
+ Denotes a lead-free/RoHS-compliant package.
e = Exposed Pad.
DS26303
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
DS26303
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TABLE OF CONTENTS DETAILED DESCRIPTION...............................................................................................................6 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7 BLOCK DIAGRAMS.........................................................................................................................9 PIN DESCRIPTION.........................................................................................................................11 4.1 HARDWARE AND HOST PORT OPERATION......................................................................................20
4.1.1 Hardware Mode...................................................................................................................................20
4.1.2 Serial Port Operation..........................................................................................................................21
4.1.3 Parallel Port Operation........................................................................................................................22
4.1.4 Interrupt Handling...............................................................................................................................22
REGISTERS....................................................................................................................................24 5.1 REGISTER DESCRIPTION...............................................................................................................29
5.1.1 Primary Registers................................................................................................................................29
5.1.2 Secondary Registers...........................................................................................................................38
5.1.3 Individual LIU Registers......................................................................................................................40
5.1.4 BERT Registers..................................................................................................................................47
FUNCTIONAL DESCRIPTION........................................................................................................54 6.1 POWER-UP AND RESET.................................................................................................................54
6.2 MASTER CLOCK............................................................................................................................54
6.3 TRANSMITTER...............................................................................................................................55
6.3.1 Transmit Line Templates....................................................................................................................56
6.3.2 LIU Transmit Front-End......................................................................................................................58
6.3.3 Dual-Rail Mode...................................................................................................................................59
6.3.4 Single-Rail Mode.................................................................................................................................59
6.3.5 Zero Suppression—B8ZS or HDB3....................................................................................................59
6.3.6 Transmit Power-Down........................................................................................................................59
6.3.7 Transmit All Ones................................................................................................................................59
6.3.8 Driver Fail Monitor...............................................................................................................................59
6.4 RECEIVER.....................................................................................................................................59
6.4.1 Peak Detector and Slicer....................................................................................................................59
6.4.2 Clock and Data Recovery...................................................................................................................59
6.4.3 Loss of Signal......................................................................................................................................60
6.4.4 AIS......................................................................................................................................................60
6.4.5 Bipolar Violation and Excessive Zero Detector...................................................................................62
6.4.6 LIU Receiver Front-End......................................................................................................................62
6.5 HITLESS-PROTECTION SWITCHING (HPS)......................................................................................62
6.6 JITTER ATTENUATOR.....................................................................................................................64
6.7 G.772 MONITOR...........................................................................................................................65
6.8 LOOPBACKS..................................................................................................................................65
6.8.1 Analog Loopback................................................................................................................................65
6.8.2 Digital Loopback..................................................................................................................................65
6.8.3 Remote Loopback...............................................................................................................................66
6.8.4 Dual Loopback....................................................................................................................................67
6.9 BERT...........................................................................................................................................68
6.9.1 Configuration and Monitoring..............................................................................................................68
6.9.2 BERT Interrupt Handling.....................................................................................................................69
6.9.3 Receive Pattern Detection..................................................................................................................69
6.9.4 Transmit Pattern Generation...............................................................................................................71
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................................72 7.1 TAP CONTROLLER STATE MACHINE..............................................................................................73
7.1.1 Test-Logic-Reset.................................................................................................................................73
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.1.5 Shift-DR...............................................................................................................................................73
7.1.6 Exit1-DR..............................................................................................................................................73
7.1.7 Pause-DR............................................................................................................................................73
7.1.8 Exit2-DR..............................................................................................................................................73
7.1.9 Update-DR..........................................................................................................................................73
7.1.10 Select-IR-Scan....................................................................................................................................74
7.1.11 Capture-IR...........................................................................................................................................74
7.1.12 Shift-IR................................................................................................................................................74
7.1.13 Exit1-IR...............................................................................................................................................74
7.1.14 Pause-IR.............................................................................................................................................74
7.1.15 Exit2-IR...............................................................................................................................................74
7.1.16 Update-IR............................................................................................................................................74
7.2 INSTRUCTION REGISTER................................................................................................................76
7.2.1 EXTEST..............................................................................................................................................76
7.2.2 HIGHZ.................................................................................................................................................76
7.2.3 CLAMP................................................................................................................................................76
7.2.4 SAMPLE/PRELOAD...........................................................................................................................76
7.2.5 IDCODE..............................................................................................................................................76
7.2.6 BYPASS..............................................................................................................................................76
7.3 TEST REGISTERS..........................................................................................................................77
7.3.1 Boundary Scan Register.....................................................................................................................77
7.3.2 Bypass Register..................................................................................................................................77
7.3.3 Identification Register.........................................................................................................................77
OPERATING PARAMETERS.........................................................................................................78 THERMAL CHARACTERISTICS....................................................................................................79
10 AC CHARACTERISTICS................................................................................................................80 10.1 LINE INTERFACE CHARACTERISTICS...............................................................................................80
10.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS.................................................................81
10.3 SERIAL PORT................................................................................................................................93
10.4 SYSTEM TIMING............................................................................................................................94
10.5 JTAG TIMING................................................................................................................................96
11 PIN CONFIGURATION...................................................................................................................97 11.1 144-PIN LQFP WITH EXPOSED PAD..............................................................................................97
12 PACKAGE INFORMATION............................................................................................................98 12.1 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (56-G6037-002) (SHEET 1 OF 2)..............98
12.2 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (SHEET 2 OF 2).........................................99
13 DOCUMENT REVISION HISTORY...............................................................................................100 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF FIGURES Figure 3-1. Block Diagram...........................................................................................................................................9
Figure 3-2. Receive Logic Detail................................................................................................................................10
Figure 3-3. Transmit Logic Detail...............................................................................................................................10
Figure 4-1. 144-Pin eLQFP Pin Assignment.............................................................................................................19
Figure 4-2. Serial Port Operation for Write Access...................................................................................................21
Figure 4-3. Serial Port Operation for Read Access with CLKE = 0...........................................................................21
Figure 4-4. Serial Port Operation for Read Access with CLKE = 1...........................................................................22
Figure 4-5. Interrupt Handling Flow Diagram............................................................................................................23
Figure 6-1. Prescaler PLL and Clock Generator.......................................................................................................54
Figure 6-2. T1 Transmit Pulse Templates.................................................................................................................56
Figure 6-3. E1 Transmit Pulse Templates.................................................................................................................57
Figure 6-4. LIU Front-End..........................................................................................................................................58
Figure 6-5. HPS Logic...............................................................................................................................................63
Figure 6-6. HPS Block Diagram.................................................................................................................................63
Figure 6-7. Jitter Attenuation.....................................................................................................................................64
Figure 6-8. Analog Loopback.....................................................................................................................................65
Figure 6-9. Digital Loopback......................................................................................................................................66
Figure 6-10. Remote Loopback.................................................................................................................................66
Figure 6-11. Dual Loopback......................................................................................................................................67
Figure 6-12. PRBS Synchronization State Diagram..................................................................................................70
Figure 6-13. Repetitive Pattern Synchronization State Diagram...............................................................................71
Figure 7-1. JTAG Functional Block Diagram.............................................................................................................72
Figure 7-2. TAP Controller State Diagram.................................................................................................................75
Figure 10-1. Intel Nonmuxed Read Cycle.................................................................................................................82
Figure 10-2. Intel Mux Read Cycle............................................................................................................................83
Figure 10-3. Intel Nonmux Write Cycle......................................................................................................................85
Figure 10-4. Intel Mux Write Cycle............................................................................................................................86
Figure 10-5. Motorola Nonmux Read Cycle..............................................................................................................88
Figure 10-6. Motorola Mux Read Cycle.....................................................................................................................89
Figure 10-7. Motorola Nonmux Write Cycle..............................................................................................................91
Figure 10-8. Motorola Mux Write Cycle.....................................................................................................................92
Figure 10-9. Serial Bus Timing Write Operation........................................................................................................93
Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0..............................................................................93
Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1..............................................................................93
Figure 10-12. Transmitter Systems Timing...............................................................................................................94
Figure 10-13. Receiver Systems Timing...................................................................................................................95
Figure 10-14. JTAG Timing.......................................................................................................................................96
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications........................................................................................7
Table 2-2. E1-Related Telecommunications Specifications........................................................................................8
Table 4-1. Pin Descriptions........................................................................................................................................11
Table 4-2. Hardware Mode Configuration Examples.................................................................................................20
Table 4-3. Parallel Port Mode Selection and Pin Functions......................................................................................22
Table 5-1. Primary Register Set................................................................................................................................24
Table 5-2. Secondary Register Set............................................................................................................................25
Table 5-3. Individual LIU Register Set.......................................................................................................................25
Table 5-4. BERT Register Set...................................................................................................................................26
Table 5-5. Primary Register Set Bit Map...................................................................................................................27
Table 5-6. Secondary Register Set Bit Map..............................................................................................................27
Table 5-7. Individual LIU Register Set Bit Map..........................................................................................................28
Table 5-8. BERT Register Bit Map............................................................................................................................28
Table 5-9. G.772 Monitoring Control.........................................................................................................................32
Table 5-10. TST Template Select Transceiver Register...........................................................................................35
Table 5-11. Template Selection.................................................................................................................................35
Table 5-12. Address Pointer for Bank Selection........................................................................................................37
Table 5-13. MCLK Selections....................................................................................................................................42
Table 5-14. Jitter Attenuator Bandwidth Selections...................................................................................................43
Table 5-15. PLL Clock Select....................................................................................................................................45
Table 5-16. Clock A Select........................................................................................................................................45
Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters............................................55
Table 6-2. Registers Related to Control of DS26303 Transmitters...........................................................................55
Table 6-3. DS26303 Template Selections.................................................................................................................56
Table 6-4. LIU Front-End Values...............................................................................................................................58
Table 6-5. Loss Criteria T1.231, G.775, and ETS 300 233 Specifications................................................................60
Table 6-6. AIS Criteria T1.231, G.775, and ETS 300 233 Specifications..................................................................61
Table 6-7. AIS Detection and Reset Criteria.............................................................................................................61
Table 6-8. Registers Related to AIS Detection..........................................................................................................61
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting.....................................................................62
Table 6-10. Pseudorandom Pattern Generation........................................................................................................68
Table 6-11. Repetitive Pattern Generation................................................................................................................68
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture.......................................................................................76
Table 7-2. ID Code Structure.....................................................................................................................................77
Table 7-3 Device ID Codes........................................................................................................................................77
Table 8-1. Recommended DC Operating Conditions................................................................................................78
Table 8-2. Capacitance..............................................................................................................................................78
Table 8-3. DC Characteristics....................................................................................................................................78
Table 9-1. Thermal Characteristics............................................................................................................................79
Table 10-1. Transmitter Characteristics.....................................................................................................................80
Table 10-2. Receiver Characteristics.........................................................................................................................80
Table 10-3. Intel Read Mode Characteristics............................................................................................................81
Table 10-4. Intel Write Cycle Characteristics............................................................................................................84
Table 10-5. Motorola Read Cycle Characteristics.....................................................................................................87
Table 10-6. Motorola Write Cycle Characteristics.....................................................................................................90
Table 10-7. Serial Port Timing Characteristics..........................................................................................................93
Table 10-8. Transmitter System Timing....................................................................................................................94
Table 10-9. Receiver System Timing.........................................................................................................................95
Table 10-10. JTAG Timing Characteristics................................................................................................................96
