DS26102 ,16-Port TDM-to-ATM PHYBlock Diagram.. 7 Figure 7-1. Polling Phase and Selection Phase at Transmit Interface........18 Fig ..
DS26303DK ,3.3V, E1/T1/J1, Short-Haul, Octal LIU Design KitFEATURES The DS26303DK is a fully integrated design kit for Expedites New Designs by Eliminating F ..
DS26303L-120 , 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-120+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitAPPLICATIONS 2.048MHz or 1.544MHz for T1/J1 or E1 T1 Digital Cross-Connects Operation; This Clock w ..
DS26303L-120+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitFEATURES 8 Complete E1, T1, or J1 Short-Haul Line The DS26303 is an 8-channel short-haul line Inte ..
DS26303L-75+ ,3.3V, E1/T1/J1, Short-Haul, Octal Line Interface UnitBLOCK DIAGRAMS ....9 4
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26102
16-Port TDM-to-ATM PHY
GENERAL DESCRIPTION On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a T1/E1 framer or transceiver. On the receive side, the
DS26102 receives a TDM stream from a T1/E1 framer or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic management functions are selectable for the transmit
and receive paths. The DS26102 can also be used in fractional T1/E1 applications. The DS26102 maps ATM cells to T1/E1 TDM frames as per the ATM Forum Specifications af-phy-0016.000
and af-phy-0064.000. In the receive direction, the cell delineation mechanism used for finding ATM cell
boundary within T1/E1 frame is performed as per ITU I.432. The DS26102 provides a mapping solution for
up to 16 T1/E1 TDM ports. The terms physical layer (PHY) and line side are used synonymously in this
document and refer to the device interfacing with the line side of the DS26102. The terms ATM layer and
system side are used synonymously and refer to the DS26102s UTOPIA II interface.
FUNCTIONAL DIAGRAM
FEATURES Supports 16 T1/E1 TDM Ports Supports Fractional T1/E1 Compliant to ATM Forum Specifications for ATM Over T1 and E1 Standard UTOPIA II Interface to the ATM Layer Configurable UTOPIA Address Range Configurable Tx FIFO Depth to 2, 3, or 4 Cells Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction per ITU I.432 Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition HEC-Based Cell Delineation Single-Bit HEC Error Correction in the Receive
Direction Receive HEC-Errored Cell Filtering Receive Idle/Unassigned Cell Filtering User-Definable Cell Filtering 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor Interface Internal Clock Generator Eliminates External High-Speed Clocks Internal One-Second Timer Detects/Reports Up to Eight External Status
Signals with Interrupt Support IEEE 1149.1 JTAG Boundary Scan Support 17mm x 17mm, 256-Pin CSBGA
Features continued on page 5.
APPLICATIONS DSLAMS ATM Over T1/E1
Routers IMA
ORDERING INFORMATION
DS26102
16-Port TDM-to-ATM PHY
DS26102 16-Port TDM-to-ATM PHY
TABLE OF CONTENTS
1. FEATURES......................................................................................................................................5
2. APPLICABLE STANDARDS............................................................................................................5
3. ACRONYMS AND DEFINITIONS.....................................................................................................6
4. BLOCK DIAGRAM...........................................................................................................................7
5. PIN DESCRIPTION..........................................................................................................................8
6. SIGNAL DEFINITIONS...................................................................................................................12 6.1 TDM SIGNALS..........................................................................................................................12
6.2 UTOPIA-SIDE SIGNALS............................................................................................................12
6.3 MICROPROCESSOR AND SYSTEM INTERFACE SIGNALS................................................................14
6.4 TEST AND JTAG SIGNALS.........................................................................................................16
7. TRANSMIT OPERATION...............................................................................................................17 7.1 UTOPIA-SIDE TRANSMITMUXED MODE WITH 1 TXCLAV........................................................17
7.2 UTOPIA-SIDE TRANSMITDIRECT STATUS MODE (MULTITXCLAV).........................................19
7.3 TRANSMIT PROCESSING............................................................................................................20
7.4 PHYSICAL-SIDE TRANSMIT.........................................................................................................21
8. RECEIVE OPERATION..................................................................................................................23 8.1 PHYSICAL-SIDE RECEIVE...........................................................................................................23
8.2 RECEIVE PROCESSING..............................................................................................................25
8.3 UTOPIA-SIDE RECEIVEMUXED MODE WITH 1 RXCLAV..........................................................27
8.4 UTOPIA-SIDE RECEIVEDIRECT STATUS MODE (MULTIRXCLAV)...........................................28
9. REGISTER MAPPING....................................................................................................................30
10. REGISTER DEFINITIONS..............................................................................................................31 10.1 TRANSMIT REGISTERS..............................................................................................................31
10.2 STATUS REGISTERS..................................................................................................................35
10.3 RECEIVE REGISTERS................................................................................................................36
11. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT....................................45 11.1 INSTRUCTION REGISTER............................................................................................................48
11.2 TEST REGISTERS......................................................................................................................49
12. OPERATING PARAMETERS.........................................................................................................52
13. CRITICAL TIMING INFORMATION................................................................................................53
14. THERMAL INFORMATION............................................................................................................59
15. APPLICATIONS INFORMATION...................................................................................................60 15.1 APPLICATION IN ATM USER-NETWORK INTERFACES...................................................................60
15.2 INTERFACING WITH FRAMERS....................................................................................................60
15.3 FRACTIONAL T1/E1 SUPPORT...................................................................................................61
16. PACKAGE INFORMATION............................................................................................................62
17. REVISION HISTORY......................................................................................................................64
DS26102 16-Port TDM-to-ATM PHY
TABLE OF FIGURES Figure 4-1. Block Diagram.......................................................................................................................7
Figure 7-1. Polling Phase and Selection Phase at Transmit Interface.....................................................18
Figure 7-2. End and Restart of Cell at Transmit Interface.......................................................................18
Figure 7-3. Transmission to PHY Paused for Three Cycles....................................................................19
Figure 7-4. Example of Direct Status Indication, Transmit Direction.......................................................20
Figure 7-5. Transmit Cell Flow and Processing......................................................................................21
Figure 7-6. Transmit Framer Interface in TFP Mode for T1.....................................................................22
Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1.....................................................22
Figure 7-8. Transmit Framer Interface in TFP Mode for E1.....................................................................22
Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1.....................................................23
Figure 8-1. Receive Framer Interface in RFP Mode for T1.....................................................................24
Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1......................................................24
Figure 8-3. Receive Framer Interface in RFP Mode for E1.....................................................................25
Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1......................................................25
Figure 8-5. Cell Delineation State Diagram.............................................................................................26
Figure 8-6. Header Correction State Machine.........................................................................................26
Figure 8-7. Polling Phase and Selection at Receive Interface.................................................................27
Figure 8-8. End and Restart of Cell Transmission at Receive Interface..................................................28
Figure 8-9. Example Direct Status Indication, Receive Direction............................................................29
Figure 10-1. Accessing Tx PMON Counter.............................................................................................34
Figure 10-2. Accessing Rx PMON Counters...........................................................................................40
Figure 11-1. JTAG Functional Block Diagram.........................................................................................45
Figure 11-2. TAP Controller State Diagram............................................................................................47
Figure 13-1. Intel Bus Read Timing (BTS = 0/MUX = 1).........................................................................53
Figure 13-2. Intel Bus Write Timing (BTS = 0/MUX = 1).........................................................................54
Figure 13-3. Motorola Bus Timing (BTS = 1/MUX = 1)............................................................................54
Figure 13-4. Intel Bus Read Timing (BTS = 0/MUX = 0).........................................................................55
Figure 13-5. Intel Bus Write Timing (BTS = 0/MUX = 0).........................................................................56
Figure 13-6. Motorola Bus Read Timing (BTS = 1/MUX = 0)..................................................................56
Figure 13-7. Motorola Bus Write Timing (BTS = 1/MUX = 0)..................................................................56
Figure 13-8. Setup/Hold Time Definition.................................................................................................58
Figure 13-9. Delay Time Definition.........................................................................................................58
Figure 13-10. JTAG Interface Timing Diagram.......................................................................................58
Figure 15-1. User-Network Interface Application....................................................................................60
Figure 15-2. DS26102 Interfacing with Dallas Framer in Framing-Pulse Mode.......................................61
DS26102 16-Port TDM-to-ATM PHY
LIST OF TABLES Table 5-A. Pin Description List................................................................................................................8
Table 9-A. Register Map.........................................................................................................................30
Table 11-A. Instruction Codes for IEEE 1149.1 Architecture...................................................................48
Table 11-B. ID Code Structure...............................................................................................................48
Table 11-C. Device ID Codes.................................................................................................................48
Table 11-D. Boundary Scan Control Bits................................................................................................49
Table 13-A. AC CharacteristicsMultiplexed Parallel Port (MUX = 1)....................................................53
Table 13-B. AC CharacteristicsNonmultiplexed Parallel Port (MUX = 1).............................................55
Table 13-C. Framer Interface AC Characteristics...................................................................................57
Table 13-D. UTOPIA Transmit AC Characteristics.................................................................................57
Table 13-E. UTOPIA Receive AC Characteristics...................................................................................57
Table 13-F. JTAG Interface Timing.........................................................................................................58
Table 13-G. System Clock AC Characteristics........................................................................................59
Table 14-A. Thermal Properties, Natural Convection..............................................................................59
Table 14-B. Theta-JA (�JA) vs. Airflow.....................................................................................................59
Table 15-A. Suggested Clock Edge Configurations................................................................................61
Table 15-B. Fractional T1/E1 Register Settings......................................................................................61
DS26102 16-Port TDM-to-ATM PHY
1. FEATURES��Supports 16 T1/E1 Ports
��Supports Fractional T1/E1 and Arbitrary Bit Rates in Multiples of 64kbps (DS0/TS) Up to
2.048Mbps
��Supports Clear E1
��Compliant to the ATM Forum Specifications for ATM Over T1 and E1
��Standard UTOPIA II Interface to the ATM Layer
��Configurable UTOPIA Address Range
��Generic 8-Bit Asynchronous Microprocessor Interface for Configuration and Status Indications
Including Interrupt Capability
��Physical Layer Interface Can Accept T1/E1 TDM Stream in the Form of Either (1) Clock, Data, and
Frame-Overhead Indication or (2) Gapped Clock (Gapped at Overhead Positions in the Frame)
and Data
��Selectable Active Clock Edge for Interface with the T1/E1 Framer
��Supports Diagnostic Loopback
��Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction
as per the ITU I.432 for the Cell-Based Physical Layer
��Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
��Option of Using Either Idle or Unassigned Cells for Cell-Rate Decoupling in Transmit Direction
��1-Byte Programmable Pattern for Payload of Cells Used for Cell-Rate Decoupling
��Tx FIFO Depth Configurable to Either 2, 3, or 4
Cells
��Transmit FIFO Depth Indication for 2-Cell Space Through External Pins
��Optional Single-Bit HEC Error Insertion
��HEC-Based Cell Delineation as per I.432
��Optional Single-Bit HEC Error Correction in the Receive Direction
��Optional Filtering of HEC-Errored Cells Received
��Optional Receive Idle/Unassigned Cell Filtering
��Optional User-Defined Cell Filtering Based on
Programmable Header Bits
��Programmable Loss-Of-Cell Delineation (LCD) Integration and Interrupt
��Interrupt for FIFO Overrun in Receive Direction
��Saturating Counts for (1) Number of Error-Free Assigned Cells Received and Transmitted and
(2) Number of Correctable and Uncorrectable HEC-Errored Cells Received
��Selectable Internally Generated Clock (System
Clock Divided by 8) in Diagnostic Loopback Mode
��Integrated PLL Generates High-Frequency
Clocks
��IEEE 1149.1 JTAG Boundary Scan Support
2. APPLICABLE STANDARDS [1] ATM Forum DS1 Physical Layer Specification, af-phy-0016.000, September 1994 [2] ATM Forum E1 Physical Layer Specification, af-phy-0064.000, September 1996 [3] ATM Forum UTOPIA Level 2 Specification, Version 1.0, af-phy-0039.000, June 1995 [4] B-ISDN User-Network InterfacePhysical Layer SpecificationITU-T Recommendation I.4323/93
DS26102 16-Port TDM-to-ATM PHY
3. ACRONYMS AND DEFINITIONS DS26102 16-Port TDM-to-ATM PHY
4. BLOCK DIAGRAM
Figure 4-1. Block Diagram
DS26102 16-Port TDM-to-ATM PHY
5. PIN DESCRIPTION
Table 5-A. Pin Description List
DS26102 16-Port TDM-to-ATM PHY
DS26102 16-Port TDM-to-ATM PHY
DS26102 16-Port TDM-to-ATM PHY
Note 1: Address-latch enable for muxed bus.
Note 2: Open-drain output.
DS26102 16-Port TDM-to-ATM PHY
6. SIGNAL DEFINITIONS
6.1 TDM Signals Signal Name:
RCLK015 Signal Description:
Receive Line Clock (Ports 0 to 15) Signal Type:
Input The physical layer device uses the RCLK input to latch the RDATA and RFP signals. RDATA and RFP are sampled by the receive section of the DS26102 at either the positive edge or negative edge of RCLK, as controlled by the
RAES (RCR2.2) control bit. RCLK is gapped during nonactive and framing bit positions in gapped-clock mode (RPLIM = 1). RCLK should be glitch-free. Signal Name:
RDATA015 Signal Description:
Receive Line Data (Ports 0 to 15) Signal Type:
Input The RDATA input carries the receive bit stream. If the RCLK is gapped at framing bit positions, RDATA is then sampled at every RCLK tick. If RCLK is not gapped and RFP is used to indicate framing bit positions, the RDATA
bits that are not associated with framing-overhead bits are sampled and cell delineated. In clear E1, RDATA is sampled at every RCLK tick. Signal Name:
RFP015 Signal Description:
Receive Frame Pulse (Ports 0 to 15) Signal Type:
Input This active-high signal indicates the framing-overhead bit positions corresponding to RDATA. For T1/E1, this aligns with the first bit of the T1/E1 frame. For T1, RDATA coming at the RFP position is ignored. For E1, RFP is used to
identify TS0 (RFP position is bit 0 of TS0) and TS16 locations, and RDATA coming at these slots are ignored. In
clear E1, RFP is ignored. In frame-pulse mode, the RFP should come once every 125�s.
Signal Name:
TCLK015 Signal Description:
Transmit Line Clock (Ports 0 to 15) Signal Type:
Input The TCLK input is used by the DS26102s transmit section to launch TDATA and TFP (when configured as an
output) at either positive edge or negative edge, as controlled by the TAES (TCR2.2) control bit.
Signal Name:
TDATA015 Signal Description:
Transmit Line Data (Ports 0 to 15) Signal Type:
Output The TDATA output carries the transmit bit stream. ATM layer data bits are not transmitted during framing/overhead
bit locations. TDATA is output at the TCLK configured active edge.
Signal Name:
TFP015 Signal Description:
Transmit Frame Pulse (Ports 0 to 15) Signal Type:
Input/Output This active-high signal can be set as an input or an output by using the TFSD (TCR2.0) control bit. TFP indicates
the frame-overhead bit positions corresponding to TDATA. For T1/E1, this signal aligns with the first bit of the T1/E1 frame. For T1, TDATA coming at the TFP position does not contain valid data bit. For E1, TFP is used to
identify TS0 (TFP position is bit 0 of TS0) and TS16. TDATA does not contain valid data at these locations. After
RESET, the DS26102 is configured to use this signal as an input. In frame-pulse mode, the TFP should occur once
every 125�s.
6.2 UTOPIA-Side Signals Signal Name:
UR_CLK Signal Description:
Receive UTOPIA Clock Signal Type:
Input
DS26102 16-Port TDM-to-ATM PHY
Signal Name: UR_ADDR[4:0]
Signal Description: Receive UTOPIA Address
Signal Type: Input
The ATM layer drives this 5-bit UTOPIA address bus to select the appropriate UTOPIA port. UR_ADDR4 is the
MSB and UR_ADDR0 is the LSB.
Signal Name: UR_ENB Signal Description: Receive UTOPIA Enable
Signal Type: Input The ATM layer asserts this active-low signal to indicate that UR_DATA and UR_SOC are sampled at the end of the
next cycle.
Signal Name: UR_SOC Signal Description: Receive UTOPIA Start of Cell
Signal Type: Output The DS26102 asserts this active-high, tri-statable signal when UR_DATA contains the first valid byte of a cell.
UR_SOC is enabled only in cycles following those with UR_ENB asserted while a cell transfer is in progress. Signal Name: UR_DATA[7:0]
Signal Description: Receive UTOPIA Data Bus Signal Type: Output
The DS26102 drives this byte-wide data bus in response to the selection of one of the UTOPIA ports by the ATM
layer for cell transfer. This bus is three-statable, and is enabled only in cycles following those that have UR_ENB asserted and a cell transfer in progress for a port. UR_DATA7 is the MSB and UR_DATA0 is the LSB. Signal Name: UR_CLAV[3:0]
Signal Description: Receive UTOPIA Cell Available Signal Type: Output
The active-high UR_CLAV signals are asserted if a complete cell is available for transfer to the ATM layer for the polled port. If UR_ADDR does not match any of the UTOPIA port addresses, this signal is tri-stated. UR_CLAV0 is
driven in multiplexed with 1 CLAV polling mode as well as direct status mode for port 1. UR_CLAV3, UR_CLAV2, and UR_CLAV1 are driven only in direct status mode for ports 4, 3, and 2, respectively. Signal Name: UR_PAR
Signal Description: Receive UTOPIA Parity Bit Signal Type: Output
This three-statable signal allows for parity error checking, as calculated for the 8-bits of the UR_DATA bus, and can represent odd or even parity as determined by the receive parity select bit (RPS) in RCR1. Signal Name: UT_CLK
Signal Description: Transmit UTOPIA Clock Signal Type: Input
This clock is used to register and control the UTOPIA signals on the transmit side.
Signal Name: UT_ADDR[4:0] Signal Description: Transmit UTOPIA Address
Signal Type: Input The ATM layer drives this 5-bit-wide bus to poll and select the appropriate UTOPIA port. UT_ADDR4 is the MSB
and UT_ADDR0 is the LSB.
Signal Name: UT_ENB
Signal Description: Transmit UTOPIA Enable
Signal Type: Input
The ATM layer asserts this active-low enable signal during cycles when UT_DATA contains valid cell data.
DS26102 16-Port TDM-to-ATM PHY
Signal Name: UT_SOC
Signal Description: Transmit UTOPIA Start of Cell
Signal Type: Input
The ATM layer asserts this active-high signal when UT_DATA contains the first valid byte of the cell. Signal Name: UT_DATA[7:0]
Signal Description: Transmit UTOPIA Data Bus
Signal Type: Input
The ATM layer drives this byte-wide true data to one of the selected ports. UT_DATA7 is the MSB and UT_DATA0 is the LSB. Signal Name: UT_CLAV[3:0]
Signal Description: Transmit UTOPIA Cell Available
Signal Type: Output
The DS26102 asserts this active-high UT_CLAV signal if it has cell space available to accommodate a complete cell from the ATM layer to the polled port. If UT_ADDR does not match with any one of the UTOPIA port
addresses, this signal is tri-stated. UT_CLAV0 is driven in multiplexed with 1 CLAV polling mode as well as direct status mode for port 1. UT_CLAV3, UT_CLAV2, and UT_CLAV1 are driven only in direct status mode for ports 4,
3, and 2, respectively.
Signal Name: UT_2CLAV[3:0]
Signal Description: Transmit UTOPIA 2 Cells Available Signal Type: Output
The DS26102 asserts this active-high UT_2CLAV signal if it has cell space available to accommodate two
complete cells from the ATM layer. If UT_ADDR does not match with any one of the UTOPIA port addresses, this signal is tri-stated. UT_2CLAV0 is driven in multiplexed with 2 CLAV polling mode as well as direct status mode for
port 1. UT_2CLAV3, UT_2CLAV2, and UT_2CLAV1 are driven only in direct status mode for ports 4, 3, and 2, respectively.
Signal Name: UT_PAR
Signal Description: Transmit UTOPIA Parity Bit
Signal Type: Input
This signal is used for parity checking as calculated for the 8 bits of the UT_DATA bus. Transmit parity errors are reported in the port status register (PSR) at bit 6. This bit can represent odd or even parity, as determined by the transmit parity select (TPRS) bit in TCR1.
6.3 Microprocessor and System Interface Signals
Signal Name: A[6:0]
Signal Description: Microprocessor Address Bus Signal Type: Input
This bus selects a specific register in the DS26102 during read/write access. A7 is the MSB and A0 is the LSB. A7 is also used as the address latch enable (ALE/AS) during multiplexed bus operation (MUX = 1). Signal Name: A7/ALE (AS)
Signal Description: Address Latch Enable (Address Strobe) or A7 Signal Type: Input
In nonmultiplexed bus operation (MUX = 0), the ALE serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge. Signal Name: D[7:0]/AD[7:0]
Signal Description: Microprocessor Data Bus Signal Type: Input/Output
This 8-bit, bidirectional data bus is used for read/write access of the DS26102s information and control registers. D7/AD7 is the MSB and D0/AD0 is the LSB. This bus also carries address information during multiplexed operation
(MUX = 1).
DS26102 16-Port TDM-to-ATM PHY
Signal Name: CS Signal Description: Chip Select
Signal Type: Input
This active-low signal is used to qualify register read/write accesses. The RD and WR signals are qualified with CS.
Signal Name: RD (DS)
Signal Description: Read Enable Signal Type: Input
Along with CS, this active-low signal qualifies read access to one of the DS26102 registers. While RD and CS are
both low, the DS26102 drives the D/AD bus with the contents of the addressed register.
Signal Name: WR (R/W)
Signal Description: Write Enable
Signal Type: Input
Along with CS, this active-low signal qualifies write access to one of the DS26102 registers. Data at D/AD[7:0] is
written into the addressed register at the rising edge of WR while CS is low.
Signal Name: INT
Signal Description: Interrupt Signal Type: Output
This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INT is deasserted
when all interrupts have been acknowledged and serviced.
Signal Name: MUX Signal Description: Bus Operation
Signal Type: Input Set this signal low to select nonmultiplexed bus operation. Set it high to select multiplexed bus operation. Signal Name: BTS
Signal Description: Bus Type Select Signal Type: Input
Set this signal high to select Motorola bus timing; set it low to select Intel bus timing. This pin controls the function
of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, these pins assume the function listed in parentheses ().
Signal Name: BLS0 Signal Description: Block Select 0
Signal Type: Input
This signal is available on the DS26102 to determine which octal block of ports is mapped to the microprocessor
control port.
Signal Name: REFCLKIN Signal Description: Reference Clock
Signal Type: Input
This continuous T1 (1.544MHz) or E1 (2.048MHz) clock is used to create GCLKOUT. Signal Name: GCLKOUT
Signal Description: Global Clock Output Signal Type: Output
This output clock is 16x the REFCLKIN input (24.7MHz (typ) for T1). This pin is usually connected to GCLKIN.
Signal Name: GCLKIN Signal Description: Global Clock Input
Signal Type: Input
This is the primary clock for internal state machines. It can be connected to GCLKOUT or provided by the user.
The GCLKIN frequency must be at least 10x the T1 or E1 line rate.
DS26102 16-Port TDM-to-ATM PHY
Signal Name: RESET
Signal Description: System Reset
Signal Type: Input
This is an active-low reset. Forcing this input low sets all internal registers to their default value. Signal Name: 8KHZIN
Signal Description: 8kHz Reference Clock
Signal Type: Input
This continuous clock is used to generate the internal one-second-timer pulse. It can be a T1/E1 frame sync.
Signal Name: 1SECOUT
Signal Description: One-Second Clock Output
Signal Type: Output
This is a one-second reference-pulse output created by dividing 8KHzIN by 8000. Using this signal is optional. Signal Name: EXSTAT0-8
Signal Description: External Status Input (1 to 8)
Signal Type: Input
A low-to-high transition on this pin sets the EXSTAT status bit in the port status register (PSR). EXSTAT1 maps to the PSR for port 1 up to EXSTAT8, which maps to port 8. The EXSTAT bit can be enabled to generate an interrupt by setting the EXSTATIM bit in RCR2. These signals could be connected to an external event timer, an external
status signal, or the 1SECOUT signal generated by the DS26102. Application of this signal is optional. If not used, the EXSTAT signals should be grounded.
Signal Name: RLCD015
Signal Description: Receive Loss-of-Cell Delineation for Ports 1 to 15
Signal Type: Output
This signal is the hardware representation of the LCDS status bit (PSR.2). For example, if RLCD3 is high (logic 1), then port 3s receiver has lost cell delineation (synchronization) with the incoming data stream.
6.4 Test and JTAG Signals
Signal Name: JTRST
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
JTRST is used to asynchronously reset the test access port (TAP) controller. After power-up, JTRST must be
toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally through a 10kΩ resistor operation. If boundary scan is not
used, this pin should be held low.
Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select
Signal Type: Input
This pin is sampled on the rising edge of JTCLK and is used to place the TAP into the various defined IEEE 1149.1
states. This pin has a 10kΩ pullup resistor.
Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal
Signal Type: Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name: JTDI
Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kΩ pullup resistor.
DS26102 16-Port TDM-to-ATM PHY
Signal Name: JTDO
Signal Description: IEEE 1149.1 Test Data Output
Signal Type: Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be
left unconnected.
Signal Name: TEST
Signal Description: Test Mode
Signal Type: Input
When TEST is set to logic 1, the REFCLKIN input is connected to the internal SYS_CLK for the IP01 logic cores.
In this mode, the signal on REFCLKIN should be phase-aligned to GCLKIN with a frequency of GCLK/2. Also, when TEST = 1 and RESET = 0, all outputs of the DS26102 should be tri-stated.
7. TRANSMIT OPERATION
The DS26102 interface to the ATM layer is fully compliant to the ATM Forums UTOPIA Level 2 specification. The
DS26102 supports multiplexed with 1 CLAV handshaking only. Each octal block can be configured to use any of the address ranges (0 to 7, 8 to 15, 16 to 23, or 24 to 30) as UTOPIA port addresses. Each octal block on the bus
must be configured for a different UTOPIA address range. The depth of the Tx FIFO is configurable to 2, 3, or 4 cells. When a port is polled and has cell space available, the DS26102 generates a cell-available signal for that
port.
Figure 7-1 shows the polling and cell transfer cycles to UTOPIA ports in the DS26102. Note that UT_SOC must be aligned with the first byte transfer. The DS26102 uses UT_SOC to detect the first byte of a cell. If a spurious
UT_SOC comes during a cell transfer, then the DS26102 aligns with the latest UT_SOC and ignores the bytes (partial cell) received thus far.
7.1 UTOPIA-Side TransmitMuxed Mode with 1 TXCLAV
In Level 1 UTOPIA there is only one PHY layer device. It uses UT_CLAV to convey transfer status to the ATM layer. In Level 2 UTOPIA only one MPHY port at a time is selected for a cell transfer. However, another MPHY port
can be polled for its UT_CLAV status, while the selected MPHY port (device) transfers data. The ATM layer polls the UT_CLAV status of an MPHY port by placing its address on UT_ADDR. The MPHY port (device) drives
UT_CLAV during each cycle, following one with its address on the UT_ADDR lines. The ATM layer selects an MPHY port for transfer by placing the desired MPHY port address onto UT_ADDR, when UT_ENB is deasserted
during the current clock cycle and asserted during the next clock cycle. All MPHY devices only examine the value
on UT_ADDR for selection purposes when UT_ENB is deasserted. The MPHY port is selected starting from the
cycle after its address is on the UT_ADDR lines and UT_ENB is deasserted; a new MPHY port is addressed for
selection ending in the cycle and UT_ENB is deasserted. Once a MPHY port is selected, the cell transfer is accomplished as described by the cell-level handshake of UTOPIA Level 1. To operate an MPHY device in a single
PHY environment, the address pins should be set to the value programmed by the management interface.
Figure 7-1 shows an example where PHYs are polled until the end of a cell transmission cycle. The UT_CLAV signal shows that PHYs N - 3 and N + 3 can accept cells and that PHY N + 3 is selected. The PHY is selected with
the rising clock edge 16. Immediately after the beginning of cell transmission to PHY N + 3, the ATM layer starts polling again. Up to 26 PHYs can be polled using the 2-clock polling cycles shown in Figure 7-1. This maximum
value can only be reached if all responses occur in minimum delays, e.g., as the figure shows, where the response
of the last PHY is obtained with clock edge 15, immediately followed by the UT_ENB pulse to the PHYs. If an ATM implementation needs additional clock cycles to select the PHY, fewer than 26 PHY can be polled during one cell
cycle. Note that if the ATM decides to select PHY N again for the next cell transmission, it could leave the UT_ENB
line asserted and start transmitting the next cell with clock edge 15. This results in back-to-back cell transmission.
Note that the active PHY (PHY N) is polled in octet P48. According to the UTOPIA Level 1 specification, the PHYs UT_CLAV signal at this time indicates the possibility of a subsequent cell transfer. Polling of PHY N before octet P44 would be possible, but it does not indicate availability of the next cell.
DS26102 16-Port TDM-to-ATM PHY
Figure 7-2 shows an example where the transmission of cells through the transmit interface is stopped by the ATM,
as no PHY is ready to accept cells. Polling then continues. Several clock cycles later one PHY gets ready to accept
a cell. During the transmission pause the UT_DATA and UT_SOC may go into high-impedance state, as shown in
Figure 7-2. UT_ENB is held in deasserted state. When a PHY is found that is ready to accept a cell (PHY_N + 3 in this case), the address of this PHY must be applied again to select it. This is necessary because of the 2-clock polling cycle, where the PHY is detected at clock edge 15. At this time, the address of PHY N + 3 is no longer on
the bus, therefore, it must be applied again in the next clock cycle. PHY N + 3 is selected with clock edge 16.
Figure 7-1. Polling Phase and Selection Phase at Transmit Interface
Figure 7-2. End and Restart of Cell at Transmit Interface
DS26102 16-Port TDM-to-ATM PHY
Figure 7-3 shows an example where the ATM must pause the data transmission, as it has no data available (in this
case, for three clock cycles). This is done by deasserting UT_ENB and (optionally) setting UT_DATA and UT_SOC
into high-impedance state. Polling may continue. In the last clock cycle, before restarting the transmission, the address M of the previously selected PHY is put on the UT_ADDR bus to reselect PHY M again.
Figure 7-3. Transmission to PHY Paused for Three Cycles
7.2 UTOPIA-Side TransmitDirect Status Mode (MULTITXCLAV)
The DS26102 supports direct status mode per af-phy-0039.000 for a maximum of four PHY ports connected to one ATM layer. For each PHY port, the status signals UR_CLAV and UT_CLAV are permanently available, according to UTOPIA Level 1 specification. PHY devices with up to four on-chip PHY ports have up to four UR_CLAV and up
to four UT_CLAV status signals, one pair of UR_CLAV and UT_CLAV for each PHY port.
Status signals and cell transfers are independent of each other. No address information is needed to obtain status
information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. With respect to the status signals UR_CLAV and UT_CLAV, this mode of operation corresponds to that of four individual PHY devices, according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation
corresponds to that as described in other parts of this document. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR_ADDR[4:0], UT_ADDR[4:0]), while the enable signal
(UR_ENB, UT_ENB) is deasserted. All PHY ports only examine the value on the address lines for possible selection
when the enable signal is deasserted. In case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time. Figure 7-4 shows a direct status example for the transmit direction. Signals UT_CLAV[3:0] are associated with PHY
port addresses 4, 3, 2, and 1. There is no need for a unique null device, therefore, X = dont care represents any address between 0 and 31 on the address lines UT_ADDR[4:0] or any data on the data bus. In this mode, the
DS26102 supports address ranges 0 to 3, 8 to 11, 16 to 19, or 24 to 27. In Figure 7-4 the polling of PHY ports starts while no cell transfer takes place. The ATM layer has pending cells for all four PHY ports (one individual
queue for each PHY port), but all four PHY ports cannot accept a cell. With rising clock edge 2, PHY port 1 indicates that it can accept a complete cell (UT_CLAV0 asserted). The ATM layer detects this at clock edge 3. It
selects that PHY port by placing address 1 on the address lines with rising clock edge 3. PHY port 1 detects this at
clock edge 4. At clock edge 5, PHY port 1 detects UT_ENB asserted, thus cell transfer for PHY port 1 starts with rising clock edge 5 (byte H1).
DS26102 16-Port TDM-to-ATM PHY
At clock edge 5, the ATM layer detects a cell available at PHY port 3 (UT_CLAV2 asserted). With rising clock edge
52, PHY port 1 indicates that it cannot accept an additional cell by deasserting UT_CLAV0. Thus, at clock edge 57,
the ATM layer detects only UT_CLAV2 asserted (UT_CLAV1 and UT_CLAV3 remain deasserted). The ATM layer deselects PHY port 1 and selects PHY port 3 for cell transfer with rising clock edge 57 by placing address 3 on the
address lines and deasserting UT_ENB. PHY port 1 and PHY port 3 detect this at clock edge 58. At clock edge 59,
PHY port 3 detects UT_ENB asserted, thus cell transfer for PHY port 3 starts with rising clock edge 59 (byte H1). For additional examples, refer to ATM Forum document af-phy-0039.000.
Figure 7-4. Example of Direct Status Indication, Transmit Direction
7.3 Transmit Processing
The DS26102 can insert a valid HEC byte in the cell header, or it can be programmed to transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55) addition can be disabled. The
generator polynomial used is 1 + X + X2 + X8. For idle/unassigned cell insertion (used for cell-rate decoupling), the DS26102 inserts a valid HEC byte with or without COSET addition, depending on the TCRDS (TCR1.3)
microprocessor register bit. The DS26102 can scramble payload bytes, depending on the TPSE (TCR1.4) register bit. The polynomial used for scrambling is X43 + 1. For debugging purposes, the DS26102 can be configured to
introduce a single-bit HEC error in the cell header of transmitted cells. When configured in HEC error-insertion mode, the DS26102 inserts HEC errors in HEC on period number of cells and turns off HEC error insertion for
HEC off period number of cells, as set in the transmit HEC error-pattern register (THEPR). This process repeats periodically until HEC error insertion is disabled through the THEIE bit (TCR1.1).
DS26102 16-Port TDM-to-ATM PHY
Figure 7-5. Transmit Cell Flow and Processing
7.4 Physical-Side Transmit
The transmit framer interface operates in one of two modes:
1) Gapped clock + data 2) Clock + data + frame-pulse indication
The mode can be selected on a per-port basis by the TPLIM control bit (TCR2.1). If configured in frame-pulse-indication mode, valid data bits are not sent during frame-pulse positions in the case of T1 and during TS0 and
TS16 positions in case of E1 direct mapping. The TS0 and TS16 locations are identified from the frame-pulse indication signal aligned with bit 0 of the E1 frame. The TPC (TCFR.0) bit determines T1 or E1 configuration. ATM
cell octets are byte-aligned with respect to the frame-pulse-indication signal. In clear E1 mode, valid data bits are transmitted at every clock tick. The DS26102 can either output the frame-pulse signal or use it as an input as
controlled through TFSD (TCR2.0).
The active edge of the transmit clock can be selected through the TAES control bit (TCR2.2). The active edge used by the transmit interface should be configured to the opposite edge of that used by the external framer. Figure 7-6 shows the transmit-framer-interface operation in frame-pulse mode for T1. In this example, the DS26102
uses the positive edge of TCLK to launch TDATA and TFP. Bit B1 is the MSB of a valid cell octet and B8 is the LSB. The TFP signal should be aligned with the framing bit position. When interfacing to framers where the framing
pulse and data active edges are individually configurable, it should be ensured that the sampling and updating should happen in opposite edges.
DS26102 16-Port TDM-to-ATM PHY
Figure 7-6. Transmit Framer Interface in TFP Mode for T1
Figure 7-7 shows the transmit-framer-interface operation for T1 in gapped-clock mode. The framing overhead-bit position is gapped. In this diagram, DS26102 uses the positive edge to launch TDATA.
Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1 Figure 7-8 shows the E1 transmit-framer-interface operation using TFP to indicate the beginning of the E1 frame.
The DS26102 uses the positive edge to launch TDATA and TFP. Using TFP, the DS26102 identifies TS0 and TS16 slots and does not send valid data on TDATA in these slots. In this case, B0 to B7 are not valid data bits of a
cell so that B8 is the MSB of the cell octet. The timing requirements for the TFP signal are the same as in the T1 case.
Figure 7-8. Transmit Framer Interface in TFP Mode for E1
DS26102 16-Port TDM-to-ATM PHY
Figure 7-9 shows the transmit framer-interface operation for E1 in gapped-clock mode. Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1
The fractional T1 (N x DS0) is supported in TFP and gapped-clock modes of the physical interface. In TFP mode, the framer must generate TFP during frame-overhead-bit and nonactive-DS0-channel positions. Fractional T1 is not supported if TFP is generated by the DS26102. In gapped-clock mode, TCLK should be gapped during frame-
overhead-bit and nonactive-DS0-channel positions. In E1, to achieve a rate in multiples of 64kbps up to
2.048Mbps, the DS26102 should be configured in gapped-clock mode, and TCLK should be gapped during nonactive time slots. TFP mode (for both input and output TFP configurations) is not supported in fractional E1 configuration. The DS26102 can either use the T1/E1 clock from the framer or use an internally generated low-frequency clock at
the transmit line interface. The low-frequency clock is the system clock (1/2 x GCLKIN) divided by 8. This clock is
used primarily for diagnostic loopback.
The TLICS bit (TCR2.6) selects between the framer clock and the internally generated clock. The internally generated clock should be used only in diagnostic loopback (otherwise, the framer and DS26102 are
operating for different clocks). During diagnostic loopback, this clock is fed to the receive line interface unit.
8. RECEIVE OPERATION
The receive interface of the DS26102 is fully compliant to the ATM Forums UTOPIA Level 2 specifications. Each
octal block of the DS26102 can be configured to use one of the address ranges (0 to 7, 8 to 15, 16 to 23, and 24 to 30) as UTOPIA port addresses. If Rx FIFO is not empty, cell available is asserted. After cell transfer from a port,
the external cell-available signal is updated based on the receive-FIFO fill level one clock cycle after cell transfer completion. During this one-clock cycle, cell-available indication for this port is kept in the deasserted state. In other
words, one-clock minimum latency between two cell transfers from the same UTOPIA port is needed by the DS26102 to update its internal cell pointers. Section 8.3 gives additional details concerning the UTOPIA-side
interface.
8.1 Physical-Side Receive
The receive framer interface operates in one of two modes: 1) Gapped clock + data
2) Clock + data + frame-pulse indication
The mode can be selected on a per-port basis with the receive physical-layer interface mode control bit (RPLIM) at RCR2.1. If configured in frame-pulse-indication mode, the bits coming at frame-pulse-indication positions are
ignored in case of T1 direct mapping, and bits coming at TS0 and TS16 positions are ignored in case of E1 direct mapping. TS0 and TS16 slots are identified using the frame-pulse indication aligned with bit 0 of the E1 frame. The
DS26102 16-Port TDM-to-ATM PHY
clock + data mode, in which case the external frame-pulse-indication signal is ignored and the data bits are clocked
at every clock tick. The active edge of the receive clock can be selected through the RAES (RCR2.2) control bit. The active edge
selected for the Rx framer interface should be opposite the active edge that is used by the transmitting device (either an external framer or the transmit section of DS26102, when enabled for diagnostic loopback).
Diagnostic loopback toward the ATM layer side (UTOPIA side) can be enabled through the DLBE (RCR2.0) control
bit. In diagnostic loopback, data, clock, and frame-pulse indication generated by the transmit section of the DS26102 are used instead of the corresponding signals from the physical layer device. Rx physical-interface mode
should be configured with same value as the Tx physical-interface mode. The Rx active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS26102.
Figure 8-1 shows the receive framer-interface operation for T1 mode with the DS26102 using the positive clock
edge to sample RDATA and RFP and the framer using the negative edge to launch RDATA and RFP.
Figure 8-1. Receive Framer Interface in RFP Mode for T1
Figure 8-2 shows the receive-framer-interface operation for T1 in gapped-clock mode. The framing overhead-bit position is gapped. In this figure, the DS26102 uses the positive edge to sample RDATA and RFP. RFP is dont
care.
Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1
Figure 8-3 shows the receive-framer-interface operation for E1 using RFP to indicate the beginning of the E1 frame. The DS26102 uses the positive edge of RCLK to sample RDATA and RFP. Using RFP, the DS26102
identifies TS0 and TS16 slots and ignores RDATA coming in these slots.
DS26102 16-Port TDM-to-ATM PHY
Figure 8-3. Receive Framer Interface in RFP Mode for E1
Figure 8-4 shows the receive-framer-interface operation for E1 in gapped-clock mode. In this mode, RCLK is
gapped during TS0 and TS16 locations.
Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1 The fractional T1 (N x DS0) is supported in both RFP and gapped-clock modes of physical interface. In RFP mode,
the framer must generate RFP during frame-overhead-bit and nonactive-DS0-channel positions. In gapped-clock mode, RCLK should be gapped during frame-overhead-bit and nonactive-DS0-channel positions. In E1 mode, the
DS26102 should be configured in gapped-clock mode and RCLK should be gapped during nonactive time slots. RFP mode is not supported in fractional E1 configuration. 8.2 Receive Processing
The received bits, after ignoring framing-overhead bits, are checked for possible HEC pattern. The polynomial used
for HEC check is G(X) = 1 + X + X2 + X8, per ITU I.432. Clearing the microprocessor interface register bit RCSE (RCR1.0) can disable the COSET subtraction (0x55). The cell boundaries in the incoming bit stream are identified based on HEC. Figure 8-5 shows the cell-delineation
state machine. The cell-delineation state machine is initially in HUNT state. In HUNT state, it performs bit-by-bit hunting for correct HEC. If correct HEC is found, it transitions to the PRESYNC state where it checks cell-by-cell for
correct HEC patterns. If DELTA-consecutive-correct patterns are received in PRESYNC, the cell-delineation state machine transitions to SYNC state. Otherwise, it goes to HUNT state and reinitiates bit-by-bit hunting. In SYNC
state, if ALPHA-consecutive-incorrect HEC patterns are received, cell delineation is lost and it goes to HUNT state. In PRESYNC and SYNC states, only cell-by-cell checking for the proper HEC pattern is performed. For the
DS26102, ALPHA = 7 and DELTA = 6.
The persistence of the out-of-cell delineation (OCD) event is integrated into LCD, based on programmable integration time period (Rx-LCD integration-period register). If OCD persists for the programmed time, LCD is
declared. LCD is deasserted only when cell delineation persists in SYNC for the same-programmed integration time. Whenever there is a change in LCD status (namely into LCD or out of LCD), an external interrupt is
generated when enabled by the corresponding mask bit RCR2.4. The persistence is checked every system clock
DS26102 16-Port TDM-to-ATM PHY
If single-bit header-error correction is enabled, the receiver mode of operation state machine follows the state
machine given in Figure 8-6. Single-bit correction is done only if correction is enabled and the state machine is in the correction mode of operation at the start of cell transfer. Receiver mode of operation is valid only when cell
delineation is in SYNC state. The DS26102 maintains 8-bit correctable and 12-bit uncorrectable HEC-errored cell counts. Both of these counters saturate.
Figure 8-5. Cell Delineation State Diagram
Figure 8-6. Header Correction State Machine
HEC error correction is performed based on receiver mode of operation. In correction mode, only single bit errors
can be corrected and the receiver switches to detection mode. In detection mode, all cells with detected header errors are discarded, provided the receive-pass HEC-errored cells (RPHEC) control bit (RCR1.3) is clear. When a
header is examined and found not to be in error, the receiver switches to correction mode. The term no action in Figure 8-6 means no correction is performed and no cell is discarded. The payload bytes of the cell are descrambled using the self-synchronizing descrambler polynomial 43 + 1, as given in ITU-T I.432. The descrambling can be enabled through the RDE control bit (RCR1.2). Descrambling is activated if cell delineation is in PRESYNC or SYNC state. The cell header is not affected by
DS26102 16-Port TDM-to-ATM PHY
After descrambling and single-bit header-error correction, the cells are written into the receive FIFO as long as cell
delineation is in SYNC and the Rx FIFO is not full. Idle and/or unassigned cells can be filtered when enabled in the
receive control registers. Uncorrectable HEC-errored cells are normally filtered and are not written into the Rx FIFO unless RPHEC (RCR1.3) is set. Note that if HEC error correction is disabled, all HEC-errored cells are termed as
uncorrectable HEC-errored cells. A 16-bit counter tracks the number of cells that can be written into the Rx FIFO and saturates at 0xFFFF. Note that, whether or not the ATM layer dequeues cells from Rx FIFO, this counter is incremented if valid cells are received. This counter is cleared by the microprocessor interface once it is latched. A
4-cell buffer per port is maintained for rate decoupling.
8.3 UTOPIA-Side ReceiveMuxed Mode with 1 RXCLAV
An internal version of the cell-available signal is maintained per port. The DS26102 drives the internal cell-available
signals onto the external CLAV lines based on the configured polling mode. In direct status mode, only four ports are supported. The four external CLAV lines are driven with the corresponding internal CLAV signals for UTOPIA
ports 0 to 3. In multiplexed-with-1-CLAV mode, only CLAV [0] is driven with the cell-available signal for the port corresponding to the current lower three UTOPIA address bits. The upper two UTOPIA address bits should match
the configured address range. If cell transfer is going on for a port, its CLAV is kept asserted until the last byte is transferred to the ATM layer. This is accomplished to support interfacing with the octet-level ATM layer as well. The
ATM layer must poll cell-available status for any fresh cell corresponding to a port only after the current cell transfer to the port is completed. The multiplexed with 1 CLAV polling-mode cycle is depicted in Figure 8-7, in which N, N + 2, N - 3, N - 2, N - 1,
N + 3, N + 1 are considered part of the DS26102 UTOPIA ports. During reception of a cell from PHY N, the other PHYs are polled. It turns out that PHY N - 3 and PHY N + 3 have cells available, and PHY N + 3 is ultimately
selected. Just like the transmit interface, the 2-clock polling cycle allows a maximum of 26 PHYs to be polled in the 8-bit mode during a cell transfer.
Figure 8-7. Polling Phase and Selection at Receive Interface
Figure 8-8 shows a case when, after the end of transmission of a cell from PHY N, no other PHY has a cell
available. Therefore, UR_ENB remains asserted as the ATM assumes a cell available from PHY N. With clock
edge 9, PHY N also has no cell available, as UR_SOC remains low. The ATM then deasserts UR_ENB while the
polling of the PHYs continues. With clock edge 15, PHY N - 3 is found to have a cell for transmission. So address N - 3 is applied, and the PHY N - 3 is selected with clock edge 16. Additional receive interface examples are
DS26102 16-Port TDM-to-ATM PHY
Figure 8-8. End and Restart of Cell Transmission at Receive Interface
8.4 UTOPIA-Side ReceiveDirect Status Mode (MULTIRXCLAV)
Consider up to a maximum of four PHY ports connected to one ATM layer. For each PHY port, the status signals
UR_CLAV and UT_CLAV are permanently available according to UTOPIA Level 1 specification. PHY devices with up to four on-chip PHY ports have up to four UR_CLAV and up to four UT_CLAV status signals, one pair of
UR_CLAV and UT_CLAV for each PHY port.
Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers.
With respect to the status signals UR_CLAV and UT_CLAV, this mode of operation corresponds to that of four individual PHY devices, according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation
corresponds to that described in this document and af-phy-0039.000. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR_ADDR[4:0], UT_ADDR[4:0]), while the enable signal
(UR_ENB, UT_ENB) is deasserted. All PHY ports only examine the value on the address lines for possible selection
when the enable signal is deasserted. If the ATM layer suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time. Figure 8-9 shows an example for the receive direction. The status signals UR_CLAV[3:0] are associated with PHY
port addresses 4, 3, 2, and 1. Note that for the DS26102, the address range can be any one of 0 to 3, 8 to 11, 16 to 19, and 24 to 27. There is no need for a unique null device, so X = dont care on the address lines
UR_ADDR[4:0]. In Figure 8-9 the polling of PHY ports starts while no cell transfer takes place. The ATM layer monitors all four status signals UR_CLAV[3:0]. At clock edge 3, it detects a cell available at PHY port 1
(UR_CLAV0 asserted). It selects that PHY port by placing address 1 on the address lines with rising clock edge 3.
PHY port 1 detects this at clock edge 4. At clock edge 5, PHY port 1 detects UR_ENB asserted, thus cell transfer for PHY port 1 starts with rising clock edge 5. At clock edge 5, the ATM layer detects a cell available at PHY port 3 (UR_CLAV2 asserted). Not knowing whether
PHY port 1 may have another cell available or not, the ATM layer deselects PHY port 1 and selects PHY port 3 for cell transfer with rising clock edge 57 by placing address 3 on the address lines and deasserting UR_ENB. PHY
port 1 and PHY port 3 detect this at clock edge 58. At clock edge 59, PHY port 3 detects UR_ENB asserted, thus
cell transfer starts with rising clock edge 59. At clock edge 111, no cell is available at PHY ports 1, 2, and 4. The
ATM layer keeps UR_ENB asserted and detects at clock edge 113 the first byte of another cell available from PHY
DS26102 16-Port TDM-to-ATM PHY
clock edge 166 that there also is no cell available from PHY port 3 (UR_CLAV2 deasserted). Thus, the ATM layer
deselects PHY port 3 by deasserting UR_ENB with rising clock edge 166.
Figure 8-9. Example Direct Status Indication, Receive Direction
DS26102 16-Port TDM-to-ATM PHY
9. REGISTER MAPPING
The 8-bit registers described in this section are maintained per port, unless otherwise noted. Address bits [7:5]
determine port number, address bit [4] distinguishes Tx and Rx section registers, and address bits [3:0] select the
particular register in Tx and Rx sections. This register arrangement applies to each block of eight T1/E1 ports. The DS26102 contains two octal blocks that are selected with the BLS signal.
Table 9-A. Register Map
P1 to P8 = Address locations (hex) for UTOPIA PHY port 1 through port 8.
Note 1: These registers are common to all ports.
Note 2: Writing into reserved address regions should be avoided. Reading from reserved address regions could give undefined value.
Note 3: Tx-assigned cell counter MSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses.
This register holds the upper 8-bit of the Tx-assigned-cell count for the port selected by accessing the Tx-PMON counter latch-enable
register.
Note 4: Tx-assigned cell counter LSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses.
This register holds the lower 8-bit of the Tx-assigned cell count for the port selected by accessing the Tx-PMON counter latch-enable
register.
Note 5: Rx-assigned cell counter MSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses.
This register holds the upper 8-bit of the Rx-assigned cell count for the port selected by accessing the Rx-PMON counter latch-enable
register.
Note 6: Rx-assigned cell counter LSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses.
This register holds the lower 8-bit of the Rx-assigned cell count for the port selected by accessing the Rx-PMON counter latch-enable
register.
Conventions:
1) In bit definitions, bit 7 is the most significant bit (MSB) and bit 0 is the least significant bit (LSB).
DS26102 16-Port TDM-to-ATM PHY
3) Reserved bit fields should be replaced with 0 while writing and, upon reading, the value corresponding to reserved bit fields is undefined.
4) R indicates read permission; W indicates write permission; RW indicates read/write permission for software to access a register.
10. REGISTER DEFINITIONS
10.1 Transmit Registers
Register Name: TCFR
Register Description: Transmit Configuration Register Register Address: 00h (Common for All Transmit Ports) Bit: 7 6 5 4 3 2 1 0
Name:
Default: Bit 0: Transmit Port Configuration (TPC). This bit affects only the Tx section.
0 = T1 mode 1 = E1 mode Bit 1: Transmit Poll Mode (TPM). Transmit UTOPIA polling mode configuration.
0 = multiplexed with 1CLAV mode 1 = direct status Bits 2, 3: Transmit High Address (TADDR). These bits decide which upper 2 bits of the UTOPIA address are to
be used by the ATM layer for selecting one of the ports. The lower 3 bits of address are assigned to the port number 1 to 8 (one-based):
'00' for address range 07 '01' for address range 815
'10' for address range 1623 '11' for address range 2430* Note that the address range selected when the BSL0 pin = 0 must be different than the address range selected
when BSL0 = 1.
Bits 3 to 7: Unassigned, read only
*Address 31 (1F hex) is reserved as the null address per UTOPIA forum. When an octal block is offset to the highest UTOPIA address range,
the port at address 31 becomes inactive.
DS26102 16-Port TDM-to-ATM PHY
Register Name: TCR1
Register Description: Transmit Control Register 1
Register Address: 06h, 26h, 46h, 66h, 86h, A6h, C6, E6h
Bit: 7 6 5 4 3 2 1 0 Name:
Default: Bit 0: Transmit HEC Insertion Enable (THIE)
0 = HEC byte as received from the ATM layer is transparently passed. 1 = proper HEC value is computed and inserted into the HEC byte of the cell. Bit 1: Transmit HEC Error-Insertion Enable (THEIE)
0 = HEC error insertion disabled
1 = HEC errors are introduced into the transmitted cells, as specified by the transmit HEC error-insertion pattern register.
Bit 2: Transmit COSET Addition Enable (TCAE)
0 = no COSET addition 1 = COSET (0x55) addition to the calculated HEC. Note that if HEC insertion is disabled, the HEC byte is transmitted transparently (this bit does not affect ATM layer cells). However, the HEC byte of
idle/unassigned cells used for cell-rate decoupling includes COSET addition as long as the TCAE bit is enabled. Bit 3: Transmit Cell-Rate Decoupling Selection (TCRDS)
0 = idle cell 1 = unassigned cell Bit 4: Transmit Payload Scrambling Enable (TPSE)
0 = disable scrambling
1 = enable scrambling Bit 5: Transmit Parity Select (TPRS). This bit determines the parity mode expected on the UT_PAR signal. 0 = odd parity check selected for transmit UTOPIA bus 1 = even parity check selected for transmit UTOPIA bus Bit 6: Transmit Parity Error-Detect Interrupt Mask (TPEDIM) 0 = DS26102 does NOT generate an external interrupt on a Tx parity error. 1 = DS26102 does generate an external interrupt on a Tx parity error.
Bit 7: Unassigned, must be set to 0 for proper operation
