DS2506 ,64 kbit Add-Only Memoryblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2506 ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
DS2506S ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
DS25BR400TSQ , Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization
DS25BR400TSQ/NOPB ,Quad 2.5 Gbps CML Transceiver withTransmit De-Emphasis and Receive Equalization 60-WQFN -40 to 85Table 1. PIN DESCRIPTIONS (continued)(1)Pin Name Pin Number I/O DescriptionOB_0+ 55 O Inverting and ..
DS25CP152TSQ/NOPB ,3.125 Gbps LVDS 2x2 Crosspoint Switch 16-WQFN -40 to 85FEATURES DESCRIPTIONThe DS25CP152 is a 3.125 Gbps 2x2 LVDS2• DC - 3.125 Gbps Low Jitter, Low Skew, ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2506
64 kbit Add-Only Memory
FEATURES65536 bits Electrically Programmable Read
Only Memory (EPROM) communicates with
the economy of one signal plus groundUnique, factory-lasered and tested 64-bit
registration number (8-bit family code +48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alikeBuilt-in multidrop controller ensures
compatibility with other MicroLAN productsEPROM partitioned into two hundred fifty six
256-bit pages for randomly accessing
packetized data recordsEach memory page can be permanently write-
protected to prevent tamperingDevice is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing dataArchitecture allows software to patch data by
superseding an old page in favor of a newlyprogrammed pageReduces control, address, data, power, and
programming signals to a single data pinDirectly connects to a single port pin of a
microprocessor and communicates at up to16.3 kbits per secondOverdrive mode boosts communication speed
to 142 kbits per second8-bit family code specifies DS2506communications requirements to readerPresence detector acknowledges when the
reader first applies voltageLow cost PR35 or 8-pin SOIC surface mount
packageReads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
PIN ASSIGNMENT
ORDERING INFORMATIONDS2506PR35 Package
DS2506S8-Pin SOIC Package
DS2506
64-kbit Add-Only MemoryBottom ViewSee Mech.
Drawings Section
PR-35NCNC
DATA
GND
8-PIN SOIC(208 mil)
DS2506
SILICON LABEL DESCRIPTIONThe DS2506 64 kbits Add-Only Memory identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2506 consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (0FH) plus
64 kbits of user-programmable EPROM. The power to program and read the DS2506 is derived entirelyfrom the 1-Wire communication line. Data is transferred serially via the 1-Wire protocol which requires
only a single data lead and a ground return. The entire device can be programmed and then write-
protected if desired. Alternatively, the part may be programmed multiple times with new data being
appended to, but not overwriting, existing data with each subsequent programming of the device. Note:
Individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. Aprovision is also included for indicating that a certain page or pages of data are no longer valid and have
been replaced with new or updated data that is now residing at an alternate page address. This page
address redirection allows software to patch data and enhance the flexibility of the device as a stand-alone
database. The 48-bit serial number that is factory-lasered into each DS2506 provides a guaranteed unique
identity which allows for absolute traceability. The PR35 and SOIC packages provide a compactenclosure that allows standard assembly equipment to handle the device easily for attachment to printed
circuit boards or wiring. Typical applications include storage of calibration constants, maintenance
records, asset tracking, product revision status and access codes.
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections ofthe DS2506. The DS2506 has three main data components: 1) 64-bit lasered ROM, 2) 65536-bits
EPROM Data Memory, and 3) 2816-bits EPROM Status Memory. The device derives its power for read
operations entirely from the 1-Wire communication line by storing energy on an internal capacitor during
periods of time when the signal line is high and continues to operate off of this “parasite” power source
during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply.During programming, 1-Wire communication occurs at normal voltage levels and then is pulsed
momentarily to the programming voltage to cause the selected EPROM bits to be programmed. The
1-Wire line must be able to provide 12 volts and 10 milliamperes to adequately program the EPROM
portions of the part. Whenever programming voltages are present on the 1-Wire line a special high
voltage detect circuit within the DS2506 generates an internal logic signal to indicate this condition. Thehierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one
of the six ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5)
Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command
byte executed at regular speed, the device will enter the Overdrive mode where all subsequent
communication occurs at a higher speed. These commands operate on the 64-bit lasered ROM portion ofeach device and can singulate a specific device if many are present on the 1-Wire line as well as indicate
to the bus master how many and what types of devices are present. The protocol required for these ROM
Function Commands is described in Figure 8. After a ROM Function Command is successfully executed,
the memory functions that operate on the EPROM portions of the DS2506 become accessible and the bus
master may issue any one of the five Memory Function Commands specific to the DS2506 to read orprogram the various data fields. The protocol for these Memory Function Commands is described in
Figure 5. All data is read and written least significant bit first.
64-BIT LASERED ROMEach DS2506 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
DS2506
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions required
to read and program the EPROM sections of the DS2506 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The
1-Wire bus master must first provide one of six ROM function commands: 1) Read ROM, 2) MatchROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. After a
ROM function sequence has been successfully executed, the bus master may then provide any one of the
memory function commands specific to the DS2506 (Figure 5).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Additionalinformation about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to zero.
Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit
of the family code has been entered, then the serial number is entered. After the 48th bit of the serial
number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC shouldreturn the shift register to all zeroes.
DS2506 BLOCK DIAGRAM Figure 1
DS2506
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3MSBLSBMSBLSBMSBLSB
65536-BITS EPROMThe memory map in Figure 4 shows the 65536-bit EPROM section of the DS2506 which is configured as
256 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 16-bit
CRC from the DS2506 that confirms proper receipt of the data and address. If the buffer contents arecorrect, a programming voltage should be applied and the byte of data will be written into the selected
address in memory. This process insures data integrity when programming the memory. The details for
reading and programming the 65536-bit EPROM portion of the DS2506 are given in the Memory
Function Commands section.
EPROM STATUS BYTESIn addition to the 65536 bits of data memory the DS2506 provides 2816 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS2506. The first 32 bytes of the EPROM Status Memory (addresses 000 to 01FH)contain the Write Protect Page bits which inhibit programming of the corresponding page in the 65536-bit
main memory area if the appropriate write protection bit is programmed. Once a bit has been
DS2506
The next 32 bytes of the EPROM Status Memory (addresses 020 to 03FH) contain the Write Protect bits
which inhibit altering the Page Address Redirection Byte corresponding to each page in the 65536-bit
main memory area.
The following 32 bytes within the EPROM Status Memory (addresses 040 to 05FH) are reserved for use
by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in
use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data. As
soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap
corresponding to that page will be programmed to 0, marking this page as used. These bits are applicationflags only and have no impact on the internal logic of the DS2506.
The next 256 bytes of the EPROM Status Memory (addresses 100H to 1FFH) contain the Page Address
Redirection Bytes which indicate if one or more of the pages of data in the 65536-bit EPROM section
have been invalidated by software and redirected to the page address contained in the appropriateredirection byte. The hardware of the DS2506 makes no decisions based on the contents of the Page
Address Redirection Bytes. Since with EPROM technology bits can only be changed from a logical 1 to
a logical 0 by programming, it is not possible to simply rewrite a page if the data requires changing or
updating. But with space permitting, an entire page of data can be redirected to another page within the
DS2506. Under TMEX a page is redirected by writing the one’s complement of the new page addressinto the Page Address Redirection Byte that corresponds to the original (replaced) page. This architecture
allows the user’s software to make a “data patch” to the EPROM by indicating that a particular page or
pages should be replaced with those indicated in the Page Address Redirection Bytes. To leave an
authentic audit trail of data patches, it is recommended to also program the write protect bit of the Page
Address Redirection Byte, after the page redirection is programmed. Without this protection, it is stillpossible to modify the Page Address Redirection Byte, making it point to a different memory page than
the true one.
If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to
that page is valid. If a Page Address Redirection Byte has some other hex value than FFH, the data in thepage corresponding to that redirection byte is invalid. According to the TMEX definitions the valid data
can now be found at the one’s complement of the page address indicated by the hex value stored in the
associated Page Address Redirection Byte. A value of FDH in the redirection byte for page 1, for
example, would indicate that the updated data is now in page 2. The status memory is programmed
similarly to the data memory. Details for reading and programming the EPROM status memory portion ofthe DS2506 are given in the Memory Function Commands section.
The Status Memory address range of the DS2506 extends from 000 to 1FFH. The memory locations 60H
to 0FFH and 200H and higher are physically not implemented. Reading these locations will usually
result in FFH bytes. Attempts to write to these locations will be ignored.
DS2506
DS2506 MEMORY MAP Figure 4
STATUS MEMORY MAP
DS2506
MEMORY FUNCTION COMMANDSThe “Memory Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the
various data fields within the DS2506. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A three byte protocol is issued by the bus master. It is
comprised of a command byte to determine the type of operation and two address bytes to determine thespecific starting byte location within a data field. The command byte indicates if the device is to be read
or written. Writing data involves not only issuing the correct command sequence but also providing a
12-volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into the selected address. Write sequences always occur
a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data isread from the part beginning at that initial location and continuing to the end of the selected data field or
until a reset sequence is issued. All bits transferred to the DS2506 and received back by the bus master
are sent least significant bit first.
READ MEMORY [F0H]The Read Memory command is used to read data from the 65536 bits EPROM data field. The bus masterfollows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. With every subsequent read data time slot the bus master
receives data from the DS2506 starting at the initial address and continuing until the end of the 65536 bits
data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space,
the bus master may issue sixteen additional read time slots and the DS2506 will respond with a 16-bitCRC of the command, address bytes and all data bytes read from the initial starting byte through the last
byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command
byte followed by the two address bytes and the data bytes beginning at the first addressed memory
location and continuing through to the last byte of the EPROM data memory. After the CRC is received
by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued.Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC
available.
Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (SeeBook of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-
Wire environment). If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.
READ STATUS [AAH]The Read Status command is used to read data from the EPROM Status data field. The bus masterfollows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. With every subsequent read data time slot the bus master
receives data from the DS2506 starting at the supplied address and continuing until the end of an eight
byte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit
CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS2506
and read back by the bus master to check if the command word, starting address and data were receivedcorrectly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire
sequence must be repeated.
DS2506
Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always hasan ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a
16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting
at the first byte of the next page of the EPROM Status data field.
This feature is provided since the EPROM Status information may change over time making it impossibleto program the data once and include an accompanying CRC that will always be valid. Therefore, the
Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current
data stored in the EPROM Status data field.
MEMORY FUNCTION FLOW CHART Figure 5
DS2506
MEMORY FUNCTION FLOW CHART Figure 5 (cont’d)
DS2506
MEMORY FUNCTION FLOW CHART Figure 5 (cont’d)
DS2506
After the 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1s
from the DS2506 until a Reset Pulse is issued. The Read Status command sequence can be ended at any
point by issuing a Reset Pulse.
EXTENDED READ MEMORY [A5H]The Extended Read Memory command supports page redirection when reading data from the 65536-bitEPROM data field. One major difference between the Extended Read Memory and the basic Read
Memory command is that the bus master receives the Redirection Byte first before investing time in
reading data from the addressed memory location. This allows the bus master to quickly decide whether
to continue and access the data at the selected starting page or to terminate and restart the reading process
at the redirected page address. A non-redirected page is identified by a Redirection Byte with a value ofFFH (see description of EPROM Status Bytes). If the Redirection Byte is different than this, the master
has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in
the new address the master has to send to the DS2506 to read the updated data replacing the old data.
There is no logical limitation in the number of redirections of any page. The only limit is the number of
available memory pages within the DS2506.
In addition to page redirection, the Extended Read Memory command also supports “bit-oriented”
applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications
the EPROM information may change over time within a page boundary making it impossible to include
an accompanying CRC that will always be valid. Therefore, the Extended Read Memory commandconcludes each page with the DS2506 generating and supplying a 16-bit CRC that is based on and
therefore always consistent with the current data stored in each page of the 65536-bit EPROM data field.
After having sent the command code of the Extended Read Memory command, the bus master follows
the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting bytelocation within the data field. By sending eight read data time slots, the master receives the Redirection
Byte associated with the page given by the starting address. With the next sixteen read data time slots,
the bus master receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This
CRC is computed by the DS2506 and read back by the bus master to check if the command word, starting
address and Redirection Byte were received correctly.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and
receives data from the DS2506 starting at the initial address and continuing until the end of a 32 byte
page is reached. At that point the bus master will send sixteen additional read time slots and receive a16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial
starting byte to the last byte of the current page.
With the next 24 read data time slots the master will receive the Redirection Byte of the next page
followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 65536-bitEPROM data field starting at the beginning of the new page. This sequence will continue until the final
page and its accompanying CRC are read by the bus master. The Extended Read Memory command
provides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte
and 2) at the end of each memory page. The CRC at the end of the memory page is always the result of
clearing the CRC generator and shifting in the data bytes beginning at the first addressed memorylocation of the EPROM data page until the last byte of this page. With the initial pass through the
Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into
DS2506
passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of
clearing the CRC generator and then shifting in the Redirection Byte only.
After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2506 untila Reset Pulse is issued. The Extended Read Memory command sequence can be exited at any point by
issuing a Reset Pulse.
WRITING EPROM MEMORYThe DS2506 has two independent EPROM memory fields, Data Memory and Status Memory. The
function flow for writing either field is almost identical. After the appropriate write command has been
issued, the bus master will send a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte ofdata (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the
DS2506 and read back by the bus master to confirm that the correct command word, starting address, and
data byte were received.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence mustbe repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the
1-Wire bus for 480 µs) is issued by the bus master. Prior to programming, the entire EPROM memory
field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a
logical 0, the corresponding bit in the selected byte of the EPROM memory is programmed to a logical 0
after the programming pulse has been applied.
After the 480 µs programming pulse is applied and the data line returns to the idle level (5 volts), the bus
master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2506
responds with the data from the selected EPROM address sent least significant bit first. This byte contains
the bit-wise logical AND of all data ever written to this address. If the EPROM byte contains 1s in bitpositions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current
byte address should be programmed again. If the DS2506 EPROM byte contains 0s in the same bit
positions as the data byte, the programming was successful and the DS2506 will automatically increment
its address counter to select the next byte in the EPROM memory field. The new two byte address will
also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byteof data using eight write time slots.
As the DS2506 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2506with sixteen read time slots to confirm that the address incremented properly and the data byte was
received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the write sequence must be
restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in
memory will be programmed.
Note that the initial pass through the write flow chart will generate an 16-bit CRC value that is the result
of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the
data byte. Subsequent passes through the write flow chart due to the DS2506 automatically incrementing
its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new
(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS2506) is made
DS2506program pulse is applied by the bus master, incorrect programming could occur within the DS2506.
Also note that the DS2506 will always increment its internal address counter after the receipt of the eight
read time slots used to confirm the programming of the selected EPROM byte. The decision to continue
is again made entirely by the bus master. Therefore if the EPROM data byte does not match the supplieddata byte but the master continues with the write command, incorrect programming could occur within
the DS2506. The write command sequence can be ended at any point by issuing a Reset Pulse.
WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3H]The Write Memory command is used to program the 65536-bit EPROM data field. The details of the
functional flow chart are described in the section “WRITING EPROM MEMORY.”
The data memory address range is 0000H to 1FFFH. If the bus master sends a starting address higher than
this, the three most significant address bits are set to zeros by the internal circuitry of the chip. This will
result in a mismatch between the CRC calculated by the DS2506 and the CRC calculated by the bus
master, indicating an error condition.
To save time when writing more than one consecutive byte of the DS2506’s data memory it is possible to
omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the
EPROM memory. At regular speed this saves 16 time slots or 976 µs for every byte to be programmed.
This speed-programming mode is accessed with the command code F3H instead of 0FH. It follows
basically the same flow chart as the Write Memory command, but skips sending the CRC immediatelypreceding the program pulse. This command should only be used if the electrical contact between bus
master and the DS2506 is firm since a poor contact may result in corrupted data inside the EPROM
memory.
WRITE STATUS [55H]/SPEED WRITE STATUS [F5H]The Write Status command is used to program the 2816-bit EPROM Status Memory field. The details ofthe functional flow chart are described in the section “WRITING EPROM MEMORY.”
The Status Memory address range is 0000H to 01FFH. Attempts to write to the not implemented status
memory locations will be ignored. If the bus master sends a starting address higher than 1FFFH, the three
most significant address bits are set to zeros by the internal circuitry of the chip. This will result in amismatch between the CRC calculated by the DS2506 and the CRC calculated by the bus master,
indicating an error condition. To save time when writing more than one consecutive byte of the
DS2506’s status memory it is possible to omit reading the 16-bit CRC which allows verification of data
and address before the data is copied to the EPROM memory. At regular speed this saves 16 time slots or
976 µs for every byte to be programmed. This speed-programming mode is accessed with the commandcode F5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skips
sending the CRC immediately preceding the program pulse. This command should only be used if the
electrical contact between bus master and the DS2506 is firm since a poor contact may result in corrupted
data inside the EPROM status memory.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS2506 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signalling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
