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DS2502
1 kbit Add-Only Memory
FEATURES 1024 bits Electrically Programmable ReadOnly Memory (EPROM) communicates with
the economy of one signal plus ground Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assuresabsolute traceability because no two parts are
alike Built-in multidrop controller ensures
compatibility with other MicroLAN products EPROM partitioned into four 256-bit pagesfor randomly accessing packetized data Each memory page can be permanently
write-protected to prevent tampering Device is an “add only” memory where
additional data can be programmed intoEPROM without disturbing existing data Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page Reduces control, address, data, power, andprogramming signals to a single data pin Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3 kbits per second§ 8-bit family code specifies DS2502
communications requirements to reader Presence detector acknowledges when the
reader first applies voltage Low cost TO-92 or 8-pin SOIC and TSOC
surface mount package§ Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
PIN ASSIGNMENT
ORDERING INFORMATIONDS2502TO-92 packageDS2502S8-pin SOIC package
DS2502P6-pin TSOC package
DS2502TTape & Reel version of DS2502
DS2502YTape & Reel version of DS2502S
DS2502VTape & Reel version of DS2502PDS2502X1Chip Scale Pkg., Tape & Reel
TOP VIEW
3.7 X 4.0 X 1.5 mm
See Mech.
Drawings Section
TSOC PACKAGE
GND
DATA
DATA
GND
8-PIN SOIC (150 MIL)
1 kbit Add-Only Memory
DS2502
SILICON LABEL DESCRIPTIONThe DS2502 1 kbit Add-Only Memory identifies and stores relevant information about the product towhich it is associated. This lot- or product-specific information can be accessed with minimal interface-
for example, a single port pin of a microcontroller. The DS2502 consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1
kbit of EPROM which is user-programmable. The power to program and read the DS2502 is derived
entirely from the 1-WireTM communication line.
Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground
return. The entire device can be programmed and then write-protected if desired. Alternatively, the part
may be programmed multiple times with new data being appended to, but not overwriting, existing data
with each subsequent programming of the device. Note: Individual bits can be changed only from alogical 1 to a logical 0, never from a logical 0 to a logical 1. A provision is also included for indicating
that a certain page or pages of data are no longer valid and have been replaced with new or updated data
that is now residing at an alternate page address. This page address redirection allows software to patch
data and enhance the flexibility of the device as a stand-alone database. The 48-bit serial number that is
factory-lasered into each DS2502 provides a guaranteed unique identity which allows for absolute
traceability. The familiar TO-92 or SOIC or TSOC packages provide a compact enclosure that allowsstandard assembly equipment to handle the device easily for attachment to printed circuit boards or
wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking,
product revision status, and access codes.
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections ofthe DS2502. The DS2502 has three main data components: 1) 64-bit lasered ROM, 2) 1024-bit EPROM,
and 3) EPROM Status Bytes. The device derives its power for read operations entirely from the 1-Wire
communication line by storing energy on an internal capacitor during periods of time when the signal line
is high and continues to operate off of this “parasite” power source during the low times of the 1-Wire
line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wirecommunication occurs at normal voltage levels and then is pulsed momentarily to the programming
voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12
volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever
programming voltages are present on the 1-Wire line a special high voltage detect circuit within the
DS2502 generates an internal logic signal to indicate this condition. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the six ROM Function
Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on
the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on
the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The
protocol required for these ROM Function Commands is described in Figure 9. After a ROM FunctionCommand is successfully executed, the memory functions that operate on the EPROM portions of the
DS2502 become accessible and the bus master may issue any one of the five Memory Function
Commands specific to the DS2502 to read or program the various data fields. The protocol for these
Memory Function Commands is described in Figure 5. All data is read and written least significant bit
first.
64-BIT LASERED ROMEach DS2502 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
DS2502
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions requiredto read and program the EPROM sections of the DS2502 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 9). The 1-
Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM,
3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the
bus master may then provide any one of the memory function commands specific to the DS2502 (Figure
6).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Figure 4
shows a hardware implementation of this CRC generator. Additional information about the DallasSemiconductor 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards.
The shift register acting as the CRC accumulator is initialized to 0. Then starting with the least significant
bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s.
DS2502 BLOCK DIAGRAM Figure 1
DS2502
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3MSBLSBMSBLSBMSBLSB
1-WIRE CRC GENERATOR Figure 4
DS2502
1024-BITS EPROMThe memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured asfour pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit
CRC from the DS2502 that confirms proper receipt of the data. If the buffer contents are correct, a
programming voltage should be applied and the byte of data will be written into the selected address in
memory. This process ensures data integrity when programming the memory. The details for reading and
programming the 1024-bit EPROM portion of the DS2502 are given in the Memory Function Commandssection.
EPROM STATUS BYTESIn addition to the 1024 bits of data memory the DS2502 provides 64 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS2502. The first byte of the EPROM Status Memory contain the Write Protect Page
bits which inhibit programming of the corresponding page in the 1024-bit main memory area if the
appropriate write protection bit is programmed. Once a bit has been programmed in the Write Protect
Page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still beread.
The next 4 bytes of the EPROM Status Memory contain the Page Address Redirection Bytes, which
indicate if one or more of the pages of data in the 1026-bit EPROM section have been invalidated and
redirected to the page address contained in the appropriate redirection byte. The hardware of the DS2502makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes
of Status EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by
programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the
data requires changing or updating, but with space permitting, an entire page of data can be redirected to
another page within the DS2502 by writing the one’s complement of the new page address into the PageAddress Redirection Byte that corresponds to the original (replaced) page.
This architecture allows the user’s software to make a “data patch” to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
If a Page Address Redirection Byte has an FFH value, the data in the main memory that corresponds to
that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that theupdated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS2502 are given in the Memory Function Commands section.
MEMORY FUNCTION COMMANDSThe “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
various data fields within the DS2502. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and createthe correct control signals within the device. A 3-byte protocol is issued by the bus master. It is
DS2502
or written. Writing data involves not only issuing the correct command sequence by also providing a 12-volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into the selected address. Write sequences always occur
a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data is
read from the part beginning at that initial location and continuing to the end of the selected data field or
until a reset sequence is issued. All bits transferred to the DS2502 and received back by the bus master
are sent least significant bit first.
DS2502 MEMORY MAP Figure 5
DS2502
MEMORY FUNCTION FLOW CHART Figure 6
DS2502
MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
DS2502
MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
DS2502
READ MEMORY [F0H]The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus masterfollows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by
the DS2502 and read back by the bus master to confirm that the correct command word and starting
address were received. If the CRC read by the bus master is incorrect, a reset pulse must be issued and the
entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues
read time slots and receives data from the DS2502 starting at the initial address and continuing until theend of the 1024-bit data field is reached or until a reset pulse is issued. If reading occurs through the end
of memory space, the bus master may issue eight additional read time slots and the DS2502 will respond
with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory.
After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s untila reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory will not
have the 8-bit CRC available.
Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment). If CRC values are imbedded within the data, a reset pulse may be issued at the end
of memory space during a Read Memory command.
READ STATUS [AAH]The Read Status command is used to read data from the EPROM Status data field. The bus master
follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a startingbyte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by
the DS2502 and read back by the bus master to confirm that the correct command word and starting
address were received. If the CRC read by the bus master is incorrect, a reset pulse must be issued and the
entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues
read time slots and receives data from the DS2502 starting at the supplied address and continuing untilthe end of the EPROM Status data field is reached. At that point the bus master will receive an 8-bit CRC
that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte
through the final factory-programmed byte that contains the 00h value.
This feature is provided since the EPROM Status information may change over time making it impossible
to program the data once and include an accompanying CRC that will always be valid. Therefore, theRead Status command supplies a 8-bit CRC that is based on and always is consistent with the current data
stored in the EPROM Status data field.
After the 8-bit CRC is read, the bus master will receive logical 1s from the DS2502 until a reset pulse isissued. The Read Status command sequence can be ended at any point by issuing a reset pulse.
READ DATA/GENERATE 8-BIT CRC [C3H]The Read Data/Generate 8-bit CRC command is used to read data from the 1024-bit EPROM data field.
The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that
indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address
bytes is computed by the DS2502 and read back by the bus master to confirm that the correct commandword and starting address were received. If the CRC read by the bus master is incorrect, a reset pulse
DS2502
address and continuing until the end of a 32-byte page is reached. At that point the bus master will sendeight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC
generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-
bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next
page. This sequence will continue until the final page and its accompanying CRC are read by the bus
master. Thus each page of data can be considered to be 33 bytes long: the 32 bytes of user-programmed
EPROM data and an 8-bit CRC that gets generated automatically at the end of each page.
This type of read differs from the Read Memory command which simple reads each page until the end of
address space is reached. The Read Memory command only generates an 8-bit CRC at the end of memory
space that often might be ignored, since in many applications the user would store a 16-bit CRC with thedata itself in each page of the 1024-bit EPROM data field at the time the page was programmed.
The Read Data/Generate 8-bit CRC command provides and alternate read capability for applications that
are “bit-oriented” rather than “page-oriented” where the 1024-bit EPROM information may change over
time within a page boundary making it impossible to program the page once and include an
accompanying CRC that will always be valid. Therefore, the Read Data/Generate 8-bit CRC commandconcludes each page with the DS2502 generating and supplying an 8-bit CRC that is based on and
therefore is always consistent with the current data stored in each page of the 1024-bit EPROM data field.
After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2502 until
a reset pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any pointby issuing a reset pulse.
WRITE MEMORY [0FH]The Write Memory command is used to program the 1024–bit EPROM data field. The bus master will
follow the command byte with a 2-byte starting address (TA1=(T7:T0), TA2=(T5:T8)) and a byte of data
(D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the DS2502
and read back by the bus master to confirm that the correct command word, starting address, and databyte were received.
The highest starting address within the DS2502 is 007FH. If the bus master sends a starting address
higher than this, the nine 9 most significant address bits are set to 0 by the internal circuitry of the chip.This will result in a mismatch between the CRC calculated by the DS2502 and the CRC calculated by the
bus master, indicating an error condition.
If the CRC read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-
Wire bus for 480 µs) is issued by the bus master. Prior to programming, the entire unprogrammed 1024-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master
that is set to a logical 0, the corresponding bit in the selected byte of the 1024-bit EPROM will be
programmed to a logical 0 after the programming pulse has been applied at that byte location.
After the 480 µs programming pulse is applied and the data line returns to a 5-volt level, the bus master
issues eight read time slots to verify that the appropriate bits have been programmed. The DS2502
responds with the data from the selected EPROM address sent least significant bit first. This byte contains
the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in
bit positions where the byte issued by the master contains 0s, a reset pulse should be issued and the
