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DS2482S-100-DS2482S-100+
Single-Channel 1-Wire Master
GENERAL DESCRIPTION The DS2482-100 is an I²C� to 1-Wire� bridge device
that interfaces directly to standard (100kHz max) or fast (400kHz max) I²C masters to perform bi-
directional protocol conversion between the I²C master and any downstream 1-Wire slave devices.
Relative to any attached 1-Wire slave device, the DS2482-100 is a 1-Wire master. Internal factory
trimmed timers relieve the system host processor from generating time-critical 1-Wire waveforms,
supporting both standard and Overdrive 1-Wire communication speeds. To optimize 1-Wire
waveform generation, the DS2482-100 performs slew rate control on rising and falling 1-Wire edges and
provides additional programmable features to match drive characteristics to the 1-Wire slave environment.
Programmable strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs
and sensors. The DS2482-100 combines these features with an output to control an external
MOSFET for enhanced strong pullup application. The I²C slave address assignment is controlled by two
binary address inputs, resolving potential conflicts with other I²C slave devices in the system.
APPLICATIONS Printers Medical Instruments Industrial Sensors Cell Phones, PDAs
TYPICAL OPERATING CIRCUIT
FEATURES I²C Host Interface, Supports 100kHz and 400kHz I²C Communication Speeds 1-Wire Master IO with Selectable Active or
Passive 1-Wire Pullup Provides Reset/Presence, 8-Bit, Single-Bit, and Three-Bit 1-Wire IO Sequences Standard and Overdrive 1-Wire Communication Speeds Slew Controlled 1-Wire Edges Selectable 1-Wire Slave Presence-Pulse Falling
Edge Masking to Control Fast Edges on the 1-Wire Line Supports Low-Impedance 1-Wire Strong Pullup
for EEPROMs, Temp Sensors, or Other 1-Wire Slaves that have Momentary High Current
Modes 2 Address Inputs for I²C Address Assignment Wide Operating Range: 2.9V to 5.5V, -40°C to +85°C 8-Pin, 150-mil SO Package
ORDERING INFORMATION
PIN CONFIGURATION 2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its Associated Companies,
conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.
1-Wire is a Registered Trademark of Dallas Semiconductor.
DS2482-100
Single-Channel 1-Wire Master
DS2482-100: Single-Channel 1-Wire Master
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current into Any Pin �20mAOperating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°CSoldering Temperature See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (VCC = 2.9V to 5.5V, TA = -40°C to +85°C.)
DS2482-100: Single-Channel 1-Wire Master
DS2482-100: Single-Channel 1-Wire Master
Note 1: Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive.
Note 2: With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on
threshold VIL1 may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not
exceed 300pF.
Note 3: Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN.
Note 4: Active or resistive pullup choice is configurable.
Note 5: Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit. Therefore, if one of these
parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in
the same direction and by the same degree.
Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew
rate is slightly faster.
Note 7: Fall time high-to-low (tF1) is derived from PDSRC, referenced from 0.9 × VCC to 0.1 × VCC.
Note 8: Presence-pulse masking only applies to standard speed.
Note 9: All I²C timing values are referred to VIHmin and VILmax levels.
Note 10: Applies to SDA, SCL, and AD0, AD1.
Note 11: I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off.
Note 12: The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Note 13: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 14: A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement tSU:DAT �250ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns
(according to the standard-mode I²C-bus specification) before the SCL line is released.
Note 15: CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to I²C-bus Specification
v2.1 are allowed.
Note 16: I²C communication should not take place for the max tOSCWUP time following a power-on reset.
PIN DESCRIPTION DS2482-100: Single-Channel 1-Wire Master
Figure 1. Block Diagram DETAILED DESCRIPTION The DS2482-100 is a self-timed 1-Wire master, which supports advanced 1-Wire waveform features including
standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence-pulse masking. Once supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search,
without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function,
presence pulse, 1-Wire short, search direction taken) through the Status register and data through the Read Data register. The DS2482 communicates with a host processor through its I²C bus interface in standard mode or in fast
mode. The logic state of two address pins determines the I²C slave address of the DS2482, allowing up to four devices operating on the same bus segment without requiring a hub.
DEVICE REGISTERS The DS2482 has three registers that the I²C host can read: Configuration, Status, and Read Data. These registers
are addressed by a read pointer. The position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The host has read and
write access to the Configuration register to enable certain 1-Wire features.
Configuration Register The DS2482 supports allows four 1-Wire features that are enabled or selected through the Configuration register. These features are: Active Pullup (APU) Presence Pulse Masking (PPM) Strong Pullup (SPU) 1-Wire Speed (1WS)
These features can be selected in any combination. While APU, PPM, and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended.
Configuration Register Bit Assignment After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration register reads
DS2482-100: Single-Channel 1-Wire Master
Active Pullup (APU) The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (RWPU resistor) is used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active Pullup
should be selected if the 1-Wire line has a substantial length (several 10m) or if there is a large number (~20 or more) of devices connected to a 1-Wire line. The active pullup does not apply to the rising edge of a presence
pulse or a recovery after a short on the 1-Wire line. The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire
slave) ends. From this point on the 1-Wire bus is pulled high through RWPU internal to the DS2482. VCC and the capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive
pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has reached a level between VIL1max and VIH1min, the DS2482 actively pulls the 1-Wire line high applying a controlled
slew rate, as represented by the dashed line. The active pullup continues until tAPUOT is expired at t3. From that time on the resistive pullup will continue.
Figure 2. Rising Edge Pullup Presence-Pulse Masking (PPM) The PPM bit controls whether the DS2482 masks the leading edge (falling) of presence pulses. When PPM = 0, masking is disabled. Presence pulse masking applies only to standard 1-Wire speed (1WS = 0); this bit has no
function if 1WS = 1 (Overdrive speed). Presence-Pulse Masking can improve the performance of large 1-Wire networks since it prevents the fast falling edge of a presence pulse generated by a 1-Wire slave device from
propagating through the network and getting reflected. Reflections can cause glitches in the network that in turn can cause slave devices to lose synchronization with the 1-Wire master. Figure 3 shows the timing references for the Presence-Pulse Masking. If enabled (PPM = 1), the DS2482 begins pulling the 1-Wire line low at tPPM1 after the reset low time tRSTL is expired. The pulldown ends at tPPM2, at which a
1-Wire slave, if present, is pulling the 1-Wire line low. The falling edge of the presence-pulse mask is slew-rate controlled.
Figure 3. Presence-Pulse Masking
DS2482-100: Single-Channel 1-Wire Master
Strong Pullup (SPU)
The SPU bit controls whether the DS2482 will apply a low impedance pullup to VCC on the 1-Wire line after the last bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong
pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D
converters. The respective device data sheets specify the location in the communications protocol after which the strong pullup should be applied. The SPU bit in the Configuration register of the DS2482 must be set immediately
prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power.
If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts, regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance
pullup does not end after tAPUOT is expired. Instead, as shown in Figure 4, the low-impedance pullup remains active until either the next 1-Wire communication command is issued (the typical case), the Configuration register is
written to with the SPU bit being 0, or the Device Reset command is issued. The PCTLZ control output is active low for the entire duration of the low-impedance pullup, enabling an external p-channel MOSFET to supply additional
power to the 1-Wire line. PCTLZ remains inactive (high) at all other time slots that do not use the strong pullup feature. Additionally, when the pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup does not
change the state of the APU bit in the Configuration register.
Figure 4. Low-Impedance Pullup Timing 1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave
devices support standard speed (1WS = 0), where the transfer of a single bit (tSLOT in Figure 4) is completed within 65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from
standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device
has received the speed-changing command code. The DS2482 must take part in this speed change to stay synchronized. This is accomplished by writing to the Configuration register with the 1WS bit being 1 immediately after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration register
with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on
the active 1-Wire line back to standard speed. Status Register
The read-only Status register is the general means for the DS2482 to report bit-type data from the 1-Wire side,
1-Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the Device Reset command position the read pointer at the Status register for the host processor to read with minimal protocol overhead. Status information is updated during the execution of certain commands only. Details are given
in the description of the various status bits below.
Status Register Bit Assignment
DS2482-100: Single-Channel 1-Wire Master
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1; once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how
long it remains at 1 are found in the Function Commands section.
Presence-Pulse Detect (PPD) The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire
device at tMSP during the Presence Detect cycle, the PPD bit will be set to 1. This bit returns to its default 0 if there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command. Short Detected (SD)
The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at tSI during the Presence Detect cycle, the SD bit is set to 1. This bit returns to its default 0 with a subsequent 1-Wire
Reset command provided that the short has been removed. If SD is 1, PPD is 0. The DS2482 cannot distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404/DS1994 is
used in the application, the interrupt function must be disabled. The interrupt signaling is explained in the respective device data sheets. Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire line is sampled for this purpose every time the Status register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle), provided that the Read Pointer is positioned at the Status register. Device Reset (RST)
If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write
Configuration command to restore the selection of the desired 1-Wire features.
Single Bit Result (SBR) The SBR bit reports the logic state of the active 1-Wire line sampled at tMSR of a 1-Wire Single Bit command or the
first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single Bit command sends a 0-bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending on the response
of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit.
Triplet Second Bit (TSB) The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the second bit of a 1-Wire Triplet
command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no function with other commands. Branch Direction taken (DIR)
Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that was chosen by the 3rd bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other commands. For additional information see the description of the 1-Wire Triplet command and the Dallas Application Note 187, "1-Wire Search Algorithm".
DS2482-100: Single-Channel 1-Wire Master
FUNCTION COMMANDS
The DS2482 understands eight function commands, which fall into four categories: device control, I²C
communication, 1-Wire set-up and 1-Wire communication. The feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information.
The host processor sends these commands and applicable parameters as strings of one or two bytes using the I²C interface. The I²C protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication.
Details of the I²C protocol including acknowledge are found in the I²C interface description of this document. Device Reset
Set Read Pointer
Valid Pointer Codes
DS2482-100: Single-Channel 1-Wire Master
Write Configuration
1-Wire Reset
DS2482-100: Single-Channel 1-Wire Master
Figure 5. 1-Wire Reset/Presence Detect Cycle 1-Wire Single Bit
Bit Allocation in the Bit Byte
x = don’t care
