DS2480S ,Serial 1-Wire Line DriverPIN DESCRIPTIONpull–up for Crypto iButton, sensors and EEPROM GND Ground1–W 1–Wire Input/Output• Se ..
DS2482+100 ,Single-Channel 1-Wire MasterFEATURES The DS2482-100 is an I²C to 1-Wire bridge device I²C Host Interface, Supports 100kHz ..
DS2482-100+ ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterFEATURES The DS2482-100 is an I²C to 1-Wire bridge device I²C Host Interface, Supports 100kHz ..
DS2482S-100+ ,Single-Channel 1-Wire Masterfeatures with an output to control an external 8-Pin, 150-mil SO Package MOSFET for enhanced str ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2480S
Serial 1-Wire Line Driver
DS2480Serial 1–WireTM Line Driver
DS2480
042498 1/26
FEATURESUniversal, common–ground serial port to 1–WireTM
line driver for MicroLANTM applicationsWorks with all iButtons and MicroLAN–compatible
1–Wire slave devicesCommunicates at regular and Overdrive 1–Wire
speed and serial port data rates of 9600 (default),
19200, 57600 and 115200 bpsSupports 12V EPROM programming and stiff 5V
pull–up for Crypto iButton, sensors and EEPROMSelf–calibrating time base with ±5% tolerance for
serial and 1–Wire communicationSlew rate controlled 1–Wire pull–down and active
pull–up to accommodate long lines and reduce radi-
ationUser–selectable RXD/TXD polarity minimizes com-
ponent count when interfacing to 5V based RS232
systems or directly to UARTsProgrammable 1–Wire timing and driver characteris-
tics accommodate a wide range of MicroLAN configu-
rations at regular speedSmart protocol combines data and control information
without requiring extra pinsCompatible to optical, IR and RF to RS232 convertersLow cost 8–pin SOIC surface mount packageOperates over 4.5V to 5.5V from –40°C to +85°C
PIN ASSIGNMENTRXD
1–W
GND
POL
TXD
VPP
8–PIN SOIC
(150 MIL)
VDD
PIN DESCRIPTIONGNDGround
1–W1–Wire Input/OutputNo Connection
VDD4.5 to 5.5 Volts
VPPOptional EPROM
Programming Voltage
POLRXD/TXD Polarity Select
TXDSerial Data from UART
RXDSerial Data to UART
ORDERING INFORMATIONDS2480S8–pin SOIC
DESCRIPTIONThe DS2480 is a serial port to 1–Wire interface chip that
supports standard and Overdrive speeds. It connects
directly to UARTs and 5V RS232 systems. Interfacing to
RS232C (±12V levels) requires a passive clamping cir-
cuit and one 5V to ±12V level translator. Internal timers
relieve the host of the burden of generating the time–
critical 1–Wire communication waveforms. In contrast
to the DS9097(E) where a full character must be sent by
the host for each 1–Wire time slot, the DS2480 can
translate each character into eight 1–Wire time slots
thereby increasing the data throughput significantly. In
addition, the DS2480 can be set to communicate at four
different data rates including 115.2 kbps, 57.6 kbps and
19.2 kbps with 9.6 kbps being the power–on default.
Command codes received from the host’s crystal con-
trolled UART serve as a reference to continuously cali-
brate the on–chip timing generator. The DS2480 uses a
unique protocol that merges data and control informa-
tion without requiring control pins. This approach main-
tains compatibility to off–the–shelf serial to wireless
converters allowing easy realization of 1–Wire media
jumpers. The various control functions of the DS2480
are optimized for MicroLAN 1–Wire networks and sup-
port the special needs of all current 1–Wire devices
including the Crypto iButton, EPROM–based Add–Only
Memories, EEPROM devices and 1–Wire Thermome-
ters.
DS2480
042498 2/26
DETAILED PIN DESCRIPTION
OVERVIEWThe DS2480 directly interfaces a 5V serial communica-
tion port with its lines TXD (transmit) and RXD (receive)
to a 1–Wire bus. In addition the device performs a speed
conversion allowing the data rate at the communication
port to be different from the 1–Wire date rate. Several
parameters relating to the 1–Wire port and its timing as
well as the communication speed at both the port and
the 1–Wire bus are configurable. The circuit to achieve
these functions is outlined in Figure 1, Block Diagram.
The device gets its input data from the serial commu-
nication port of the host computer through pin TXD. For
compatibility with active–high as well as active–low sys-
tems, the incoming signal can be inverted by means of
the polarity input POL. The polarity chosen by hard–wir-
ing the logic level of this pin is also valid for the output pin
RXD. If for minimizing the interface hardware an asym-
metry between RXD and TXD is desired, this can be
achieved by setting the most significant bit of the Speed
Control parameter to a 1 (see Configuration Parameter
Value Codes). With the MS bit of the speed control set to
1, the polarity at TXD is still selected by the logic level at
POL, but the polarity at RXD will be the opposite of what
the logic level at POL specifies.
As data enters the core of the DS2480’s logic circuitry, it
is analyzed to separate data and command bytes and to
calibrate the device’s timing generator. The timing gen-
erator controls all speed relations of the communication
interface and the 1–Wire bus as well as the wave forms
on the 1–Wire bus.
Command bytes either affect the configuration setting
or generate certain wave forms on the 1–Wire bus. Data
bytes are simply translated by the protocol converter
into the appropriate 1–Wire activities. Each data byte
generates a return byte from the 1–Wire bus, that is
communicated back to the host through the RXD pin as
soon as the activity on the 1–Wire bus is completed.
The 1–Wire driver shapes the slopes of the 1–Wire
wave forms, applies programming pulses or strong
pull–up to 5 volts and reads the 1–Wire bus using a non–
TTL threshold to maximize the noise margin for best
performance on large 1–Wire MicroLAN networks.
DS2480
042498 3/26
DS2480 BLOCK DIAGRAM Figure 1VPP
RXD
POL
TXD
DEVICE OPERATIONThe DS2480 can be described as a complex state
machine with two static and several dynamic states.
Two device–internal flags as well as functions assigned
to certain bit positions in the command codes determine
the behavior of the chip, as shown in the state transition
diagram (Figure 2). The DS2480 requires and gener-
ates a communication protocol of 8 data bits per charac-
ter, 1 stop bit and no parity. It is permissible to use two
stop bits on the TXD line. However, the DS2480 will only
assert a single stop bit on RXD.
When powering up, the DS2480 performs a master
reset cycle and enters the Command Mode, which is
one of the two static states. The device now expects to
receive one 1–Wire reset command on the TXD line
sent by the host at a data rate of 9600 bits per second
(see section Communication Commands for details).
This command byte is required solely for calibration of
the timing generator the DS2480 and is not translated
into any activity on the 1–Wire bus. After this first com-
mand byte the device is ready to receive and execute
any command as described later in this document.
A master reset cycle can also be generated by means of
software. This may be necessary if the host for any rea-
son has lost synchronization with the device. The
DS2480 will perform a master reset cycle equivalent to
the power–on reset if it detects start polarity in place of
the stop bit. The host has several options to generate
this condition. These include making the UART gener-
ate a break signal, sending a NULL character at a data
rate of 4800 bps and sending any character with parity
enabled and selecting space polarity for the parity bit.
As with the power–on reset, the DS2480 requires a
1–Wire reset command sent by the host at a data rate of
9600 bps for calibration.
DS2480
042498 4/26
STATE TRANSITION DIAGRAM Figure 2INACTIVE
COMMAND MODE
CONFIGURATION
CHECK
MODE
ARRIVAL
CODE
SINGLE BIT
FUNCTIONSEARCH
ACCEL.PULSERESET
SOFTWARE
MASTER RESET
TX E3hTX BYTE
N.C.
N.C.
N.C.
ARRIVAL
POWER OFF
E1h
ALL OTHER
CODES
ACC.ON
STR. PULL–UP
ARMEDACC. OFF
STR. PULL–UP NOT ARMED
N.C. = UNCONDITIONAL
GENERATE STRONG
PULL–UP TO 5V
LEGEND:VBINARY VALUE (TYPE OF WRITE TIME SLOT)1–WIRE SPEED SELECTION CODEIF LOGIC 1, GENERATES STRONG PULL–UP TO 5V IMMEDIATELY FOLLOWING THE TIME SLOTTYPE OF PULSE; 0 = STRONG PULL–UP (5V), 1 = PROGRAMMING PULSE (12V)1 = ARM STRONG PULL–UP AFTER EVERY BYTE; 0 = DISARMSEARCH ACCELERATOR CONTROL; 1 = ACCELERATOR ON, 0 = ACCELERATOR OFF
ZZZCONFIGURATION PARAMETER CODE (WRITE), 000 = READ CONFIGURATION PARAMETER
VVVCONFIGURATION PARAMETER VALUE CODE (WRITE), CONFIGURATION PARAMETER CODE (READ)DON’T CARE
CHECK SEARCH
ACCELERATOR FLAGDATA MODE
PERFORM SEARCH
SEQUENCE
DS2480
042498 5/26
After the DS2480 has reached the command mode, the
host can send commands such as 1–Wire Reset, Pulse,
Configuration, Search Accelerator and Single Bit func-
tions or switch over to the second static state called
Data Mode. In data mode the DS2480 simply convertsbytes it receives at the TXD pin into their equivalent
1–Wire wave forms and reports the results back to the
host through the RXD pin. If the Search Accelerator is
on, each byte seen at TXD will generate a 12–bit
sequence on the 1–Wire bus (see section Search
Accelerator for details). If the Strong Pull–up to 5V is
enabled (see Pulse command) each byte on the 1–Wire
bus will be followed by a pause of predefined duration
where the bus is pulled to 5V via a low impedance tran-
sistor in the 1–Wire driver circuit.
While being in the Data Mode the DS2480 checks each
byte received from the host for the reserved code that is
used to switch back to Command Mode. To be able to
write any possible code (including the reserved one) to
the 1–Wire bus, the transition to the Command Mode is
as follows: After having received the code for switching
to Command Mode, the device temporarily enters the
Check Mode where it waits for the next byte. If bothbytes are the same, the byte is sent once to the 1–Wire
bus and the device returns to the Data Mode. If the
second byte is different from the reserved code, it will be
executed as command and the device finally enters the
Command Mode. As a consequence, if the reserved
code that normally switches to Command Mode is to be
written to the 1–Wire bus, this code byte must be sent
twice (duplicated). This detail must be considered care-
fully when developing software drivers for the DS2480.
After having completed a memory function with a device
on the 1–Wire bus it is recommended to issue a Reset
Pulse. This means that the DS2480 has to be switched
to Command mode. The host then sends the appropri-
ate command code and continues performing other
tasks. If during this time a device arrives at the 1–Wire
bus it will generate a presence pulse. The DS2480 will
recognize this unsolicited presence pulse and notify the
host by sending a byte such as XXXXXX01b. The Xs
represent undefined bit values. The fact that the host
receives the byte unsolicited together with the pattern
01b in the least significant two bits marks the bus arrival.
If the DS2480 is left in Data Mode after completing a
memory function command it will not report any bus
arrival to the host.
COMMAND CODE OVERVIEWThe DS2480 is controlled by a variety of commands. All
command codes are 8 bits long. The most significant bit
of each command code distinguishes between commu-
nication and configuration commands. Configuration
commands access the configuration registers. They
can write or read any of the configurable parameters.
Communication commands use data of the configura-
tion register in order to generate activity on the 1–Wire
bus and/or (dis)arm the strong pull–up after every byte
or (de)activate the Search Accelerator without generat-
ing activity on the 1–Wire bus. Details on the command
codes are included in the State Transition diagram
(Figure 2). A full explanation is given in the subsequent
sections Communication Commands and Configura-
tion Commands.
In addition to the command codes explained in the sub-
sequent sections the DS2480 understands the follow-
ing reserved command codes:
E1hswitch to Data Mode
E3hswitch to Command Mode
F1hpulse termination
Except for these reserved commands, the Search
Accelerator control and the first byte after power–on
reset or master reset cycle, every legal command byte
generates a response byte. The pulse termination code
triggers the response byte of the terminated pulse com-
mand. Illegal command bytes do not generate a com-
mand response byte.
Once the device is switched back from Data Mode to
Command Mode one must not repeat the E3h com-
mand while the Command Mode is still active.
COMMUNICATION COMMANDSThe DS2480 supports four communication function
commands: Reset, Single Bit, Pulse, and Search Accel-
erator control. Details on the assignment of each bit of
the command codes are shown in Table 1. The corre-
sponding command response bytes are detailed in
Table 2. The Reset, Search Accelerator Control and
Single Bit commands include bits to select the 1–Wire
communication speed (regular, flexible regular, Over-
drive). Even if a command does not generate activity on
the 1–Wire bus, these bits are latched inside the device
and will take effect immediately.
DS2480
042498 6/26
COMMUNICATION COMMAND CODES Table 1
COMMUNICATION COMMAND RESPONSE Table 2(The Search Accelerator Control command does not generate a response byte.)
ResetThe Reset command must be used to begin all 1–Wire
communication. The speed selection included in the
command code immediately takes effect. The response
byte includes a code for the reaction on the 1–Wire bus
(bits 0 and 1) and a code for the chip revision (bits 2 to 4).
If bit 5 of the response byte reads ‘1’, a programming
voltage is present on the VPP pin, indicating that one
may try programming EPROM devices.
Single BitThe Single Bit command is used to generate a single
time slot on the 1–Wire bus at the speed indicated by
bits 2 and 3. The type of the time slot (write zero or write
one) is determined by the logic value of bit 4. A read data
time slot is identical to the write one time slot. Bits 0 and
1 of the response byte transmitted by the DS2480 at the
end of the time slot reveal the value found on the 1–Wire
bus when reading.
For a time slot without a subsequent strong pull–up, bit 1
of the command must be set to 0. For a time slot immedi-
ately followed by a strong pull–up bit 1 must be set to 1.
As soon as the strong pull–up is over, the device will
send a second response byte, code EFh (read 1) or ECh
(read 0), depending on the value found on the 1–Wire
bus when reading. The strong pull–up directly following
the single bit is used in conjunction with the Crypto
iButton.
Search Accelerator ControlThe Search Accelerator Control command is used to set
or reset the Search Accelerator control flag. Bit 4 of the
command code contains the state to which the acceler-
DS2480
042498 7/26
ator control flag is to be set. If the flag is set to a 1 (on) the
device translates every byte received in data mode into
a 12–bit sequence on the 1–Wire bus. For details on
how the Search Accelerator works please refer to the
section Search Accelerator Operation. Before activat-
ing the Search Accelerator, one must make sure that the
strong pull–up after every byte is disarmed (see Pulse
Command). The Search Accelerator command does
not generate a command response byte.
Although the Search Accelerator Control command
itself does not generate any 1–Wire activity, it can be
used to select the communication speed on the 1–Wire
bus. The speed selection (if different from the previous
setting, e.g., from a Reset command) will take effect
immediately.
PulseThe Pulse command serves several functions that are
selected by the contents of bit 1 and bit 4 of the com-
mand code. The main functions are generating a strong
pull–up to 5V and generating 12V programming pulses
for EPROM devices (if the 12V are available at the VPP
pin). The secondary function of the pulse command is
arming and disarming a strong pull–up after every sub-
sequent byte in data mode. The arm/disarm function is
controlled by bit 1 of the command code. Bit 4 deter-
mines whether the device will generate a strong pull–up
to 5V or a 12V programming pulse. The table below
summarizes these options.
The strong pull–up to 5V is required to program
EEPROM devices or to operate special function
devices that require a higher current for a limited time
after having received a “go and convert” command.
Therefore and because it significantly reduces the
effective data throughput on the 1–Wire bus, the strong
pull–up is disarmed most of the time. Although arming or
disarming is simultaneously possible while generating a
programming pulse, this is not recommended since it is
likely to destroy the DS2480 if non–EPROM devices are
connected to the 1–Wire bus.
The duration of the strong pull–up or programming
pulse is determined by configuration parameters and
ranges from a few microseconds up to unlimited (see
section Configuration Commands). However, unlimited
duration is not allowed in conjunction with arming the
strong–pull–up after every byte. As long as the DS2480
is in Command Mode the host may terminate a strong
pull–up or programming pulse prematurely at any time
by sending the command code F1h.
The response byte is generated as soon as the strong
pull–up or programming pulse is over (either because
the predefined time has elapsed or due to termination).
The response byte mainly returns the command code
as sent by the host, but the two least significant bits are
undefined.
If the strong pull–up is armed and the device is in Data
Mode, the end of the strong pull–up will be signaled as
code F6h if the most significant bit of the preceding data
byte on the 1–Wire bus was a 1 and 76h otherwise. The
host will see this response byte in addition to the
response on the data byte sent (see also section Wave
Forms later in this document).
SEARCH ACCELERATOR INTRODUCTIONThe Search Accelerator is a logic block inside the
DS2480 that allows using the Search ROM function
very efficiently under modern operating systems such
as Windows and Windows 95/NT. Without the DS2480
all 1–Wire port adapters have to involve the computer’s
CPU for every single time slot or pulse to be generated
on the 1–Wire bus.
Under DOS, accessing peripherals such as the UART
or parallel port is very straight forward and therefore
fast. Under Windows the situation is different and it may
take several milliseconds or more to get the first time
slot generated on the 1–Wire bus. Every subsequent
time slot will be generated in much less time, since the
computer simply sends out (“streams”) a long chain of
bytes. This works reasonably well when reading or writ-
ing large blocks of data.
DS2480
042498 8/26
Searching the 1–Wire bus to identify all ROM IDs of the
devices connected, however, requires reading two bits,
making a decision and then writing a bit. This procedure
is to be repeated 64 times to identify and address a
single device. With the overhead of modern operating
systems this fairly simple process takes a lot of time,
reducing the discovery rate of devices on the 1–Wire
bus from a typical value of 40 to 50 per second under
DOS to less than 10 under Windows. To solve this prob-
lem the Search Accelerator was developed.
The Search Accelerator receives from the host informa-
tion on the preferred path to chose during the execution
of the Search ROM function as one contiguous chain of
bytes and then translates it into the appropriate time
slots on the 1–Wire bus. In addition, the Search Acceler-
ator reports back to the host the ROM ID of the device
actually addressed and the bit positions in which con-
flicts were found. (If the ROM ID of one device has a 0 in
a bit position where another device has a 1, this is called
a “conflict” on the electrical level and “discrepancy” on
the logical level. See the Book of DS19xx iButton Stan-
dards for a more detailed discussion of the Search
ROM). This helps the host to select the preferred path
for the next Search ROM activity.
Since the ROM ID of all MicroLAN compatible devices is
64 bits long and a conflict may occur in any of these bits,
the total length of data reported to the host is 128 bits or
16 bytes. To avoid data overrun (if the CPU sends data
faster than it can be processed) the protocol for the
Search Accelerator operation was defined so that one
has to send as many bytes as one will receive. This way
the CPU sends 16 bytes for each path and the UART
guarantees the correct data timing and frees the CPU
for other tasks while the DS2480 performs a Search
ROM function.
SEARCH ACCELERATOR OPERATIONAfter the Search Accelerator is activated and the data
mode is selected, the host must send 16 bytes to com-
plete a single Search ROM pass on the 1–Wire bus.
These bytes are constructed as follows:
first byte
et cetera
16th byte
In this scheme, the index (values from 0 to 63, “n”) des-
ignates the position of the bit in the ROM ID of a Micro-
LAN compatible device. The character “x” marks bits
that act as filler and do not require a specific value (don’t
care bits). The character “r” marks the path to go at that
particular bit in case of a conflict during the execution of
the ROM Search.
For each bit position n (values from 0 to 63) the DS2480
will generate three time slots on the 1–Wire bus. These
are referenced as:for the first time slot (read data)for the second time slot (read data) andfor the third time slot (write data).
The type of time slot b2 (write 1 or write 0) is determined
by the DS2480 as follows:= rn if conflict (as chosen by the host)
= b0 if no conflict (there is no alternative)
= 1 if error (there is no response)
The response the host will receive during a complete
pass through a Search ROM function using the Search
Accelerator consists of 16 bytes as follows:
first byte
et cetera
16th byte
As before, the index (values from 0 to 63, “n”) desig-
nates the position of the bit in the ROM ID of a MicroLAN
compatible device. The character “d” marks the discrep-
ancy flag in that particular bit position. The discrepancy
flag will be 1 if there is a conflict or no response in that
particular bit position and 0 otherwise. The character
“r’ ” marks the actually chosen path at that particular bit
position. The chosen path is identical to b2 for the partic-
ular bit position of the ROM ID.
DS2480
042498 9/26
To perform a Search ROM sequence one starts with all
bits rn being 0s. In case of a bus error, all subsequent
response bits r’n are 1’s until the Search Accelerator is
deactivated. Thus, if r’63 and d63 are both 1, an error has
occurred during the search procedure and the last
sequence has to be repeated. Otherwise r’n (n = 0 ... 63)
is the ROM code of the device that has been found and
addressed.
For the next Search ROM sequence one re–uses the
previous set rn (n = 0 ... 63) but sets rm to 1 with “m” being
the index number of the highest discrepancy flag that is
1 and sets all ri to 0 with i > m. This process is repeated
until the highest discrepancy occurs in the same bit
position for two consecutive passes.
The table below shows an example for the communica-
tion between host and DS2480 to perform one pass
through the Search ROM function using the Search
Accelerator. After a device has been identified and
addressed, a (not specified here) memory function is
executed and finally a reset pulse is generated. This
example assumes that the DS2480 was in Command
Mode and that regular 1–Wire speed is used.
Search Accelerator Usage Example
CONFIGURATION COMMANDSThe DS2480 is designed to be configurable for the vary-
ing requirements of its application. When the device
powers up and/or performs a master reset cycle, the
hard–wired default configuration settings take effect.
These settings will work on a short 1–Wire bus and
assume regular 1–Wire communication speed. To
change these default settings and to verify the current
settings, the logic of the DS2480 supports configuration
commands. A summary of the available configuration
parameters, their default settings at regular and Over-
drive speed and their applicability is shown in Table 3.
Parameters not related to the communication speed on
the 1–Wire bus specify the duration of the 12V program-
ming pulse, the duration of the strong pull–up to 5V and
the baud rate on the interface that connects the DS2480
to the host. The remaining three parameters are used to
modify the 1–Wire communication wave forms if one
selects “Flexible Speed” (see “Communication Com-
mands” for speed selection).
Flexible speed is implemented to improve the perfor-
mance of large MicroLAN Networks. This is accom-
plished by:limiting the slew rate on falling edges (e. g., at the
beginning of time slots, to reduce ringing),extending the Write 1 low time (allows the current flow
through the network to end slowly, to prevent voltage
spikes from inductive kickback),delaying the time point when reading a bit from the
1–Wire bus (gives the network more time to stabilize,
to get a higher voltage margin) andadding extra recovery time between Write 0 time slots
(allows more energy transfer through the network, to
replenish the parasite power supply of the devices on
the bus).
The latter two functions are controlled by a single
parameter. Taking advantage of flexible speed requires
changing one or more of these parameters from their
default values. Otherwise the waveforms will be identi-
cal to those at regular speed.
Each configuration parameter is identified by its 3–bit
parameter code and can be programmed for one of a
maximum 8 different values using a 3–bit value code. A
matrix of parameter codes and value codes with the
associated physical values in shown in Table 4.
DS2480
042498 10/26
CONFIGURATION COMMAND OVERVIEW Table 3The numbers given for parameter 001 (Pull–Down Slew
Rate Control) are nominal values. They may vary as
specified in the Electrical Characteristics section and
are almost independent of the load on the 1–Wire bus.
Information on how to select the optimum value of this
parameter is given in section “Controlled Edges”.
For the parameters 010 (Programming Pulse Duration)
and 011 (Strong Pull–Up Duration) one may select
indefinite duration. This value, however, should only be
selected if one is not going to switch the device to Data
Mode. As long as the device stays in Command Mode,
any pulse function (programming or strong pull–up) that
uses one of these parameters can be terminated by
sending the command code F1h. Termination is not pos-
sible if the device is in Data Mode.
Parameter 111 (RS232 Baud Rate) has two functions. It
selects the baud rate and allows inversion of the signal
at the RXD pin. Using one of the value codes 100 to 111
will set the polarity at RXD to the opposite of what is
defined by the logic level at the POL pin (asymmetry bit,
see Figure 1). This may reduce the component count in
some applications of the device. Note that when chang-
ing the baud rate, the DS2480 will send the command
response byte at the new data rate.
A short explanation on the use of parameters 100 (Write
1 low time) and 101 (Data Sample Offset/Write 0 Recov-
ery Time) is given in the section “Timing Diagrams” later
in this document. The parameter code 110 is reserved
for future extensions; one should not change the value
code from its default setting.
CONFIGURATION PARAMETER VALUE CODES Table 4
DS2480
042498 11/26
The syntax of configuration commands is very simple.
Each 8–bit code word contains a 3–bit parameter code
to specify the parameter and the 3–bit value code to be
selected. Bit 7 of the command code is set to 0 and bit 0
is always a 1. To read the value code of a parameter, one
writes all zeros for the parameter code and puts the
parameter code in place of the parameter value code.
Table 5 shows the details.
The configuration command response byte is similar to
the command byte itself. Bit 0 of the response byte is
always 0. When writing a parameter, the upper 7 bits are
the echo of the command code. When reading a param-
eter, the current value code is returned in bit positions 1
to 3 with the upper 4 bits being the same as sent (see
Table 6).
CONFIGURATION COMMAND CODES Table 5
CONFIGURATION COMMAND RESPONSE BYTE Table 6
DS2480
042498 12/26
CONTROLLED EDGESOne of the tasks of the DS2480 is to actively shape the
edges of the 1–Wire communication waveforms. This
speeds up the recharging of the 1–Wire bus (rising
edges) and reduces ringing of long lines (falling edges).
The circuitry for shaping rising edges is always on. The
slew rate of falling edges is actively controlled only at
flexible speed and requires the parameter for slew rate
control being different from its power–on default value.
All Rising EdgesThe active pull–up of the rising edges reduces the rise
time on the 1–Wire bus significantly compared to a sim-
ple resistive pull–up. Figure 4 shows how the DS2480 is
involved in shaping a rising edge.
ACTIVE PULL–UP Figure 4IS DISCHARGEDt2t3
The circuit operates as follows: At t1 the pull–down
(induced by the DS2480 or a device on the bus) ends.
From this point on the 1–Wire bus is pulled high by the
weak pull–up current IWEAKPU provided by the DS2480.
The slope is determined by the load on the bus and the
value of the pull–up current. At t2 the voltage crosses the
threshold voltage VIAPO. Now the DS2480 switches
over from the weak pull–up current IWEAKPU to the
higher current IACTPU. As a consequence, the voltage
on the bus now rises faster. As the voltage on the bus
crosses the threshold VIAPTO at t3, a timer is started. As
long as this timer is on (tAPUOT), the IACTPU current will
continue to flow. After the timer is expired, the DS2480
will switch back to the weak pull–up current.
Falling Edges (DS2480–initiated)Whenever the DS2480 begins pulling the 1–Wire bus
low to initiate a time slot, for example, it first turns off the
weak pull–up current IWEAKPU. Then, at regular and
Overdrive speed it will generate a falling edge at a slew
rate of typically 15V/μs. This value is acceptable for
short 1–Wire busses and adequate for communication
at Overdrive speed. For MicroLAN networks of more
than roughly 30 meters length one should always use
flexible speed. One of the parameters that is adjustable
at flexible speed is the slew rate of DS2480–initiated fal-
ling edges. The effect of the slew rate control is shown in
Figure 5.
SLEW RATE CONTROL Figure 51–WIRE BUS
IS PULLED UP
WEAK PULL–UP ENDS,
PULL–DOWN BEGINSt1
As extensive tests have shown, MicroLAN networks at a
length of up to 300 meters will perform best if the fall time
tF is in the range of 4 ± 0.5 μs. This translates into a slew
rate of approximately 1V/μs. This slew rate is typically
achieved by setting the configuration parameter 001
(Pull–Down Slew Rate Control) to a value of 100 (see
Table 4). If the actual measured fall time is longer than
the target value, one should use a value code of 011 or
lower. If the fall time is shorter, one should use a value
code of 101 or higher.
Once determined, the value code for the Pull–Down
Slew Rate Control parameter should be stored in the
host and always be loaded into the DS2480 after a
power–on or master reset cycle.
DS2480
042498 13/26
TIMING DIAGRAMSThis section explains the wave forms generated by the
DS2480 on the 1–Wire bus in detail. First the commu-
nication wave forms such as the Reset/Presence
Detect Sequence and the time slots are discussed.
After that follows a detailed description of the pulse
function under various conditions. The wave forms as
generated by the DS2480 may deviate slightly from
specifications found in the “Book of DS19xx iButton
Standards” or in data sheets of 1–Wire slave devices.
However, at a closer look one will find that all of the tim-
ing requirements are met.
1–WIRE COMMUNICATION WAVE FORMSOne of the major features of the DS2480 is that it
relieves the host from generating the timing of the
1–Wire signals and sampling the 1–Wire bus at the
appropriate times. How this is done for the reset/pres-
ence detect sequence is shown in Figure 6a. This
sequence is composed of four timing segments: the
reset low time tRSTL, the short/interrupt sampling offset
tSI, the presence detect sampling offset tPDT and a delay
time tFILL. The timing segments tSI, tPDT and tFILL com-
prise the reset high time tRSTH where 1–Wire slave
devices assert their presence or interrupt pulse. During
this time the DS2480 pulls the 1–Wire bus high with its
weak pull–up current.
The values of all timing segments for all 1–Wire speed
options are shown in the table. Since the reset/presence
sequence is slow compared to the time slots, the values
for regular and flexible speed are the same. Except for
the falling edge of the presence pulse all edges are con-
trolled by the DS2480. The shape of the uncontrolled
falling edge is determined by the capacitance of the
1–Wire bus and the number, speed and sink capability
of the slave devices connected.
Reset/Presence Detect Figure 6aAfter having received the command code for generating
a reset/presence sequence, the DS2480 pulls the
1–Wire bus low for tRSTL and then lets it go back to 5V.
The DS2480 will now wait for the short/interrupt sam-
pling offset tSI to expire and then test the voltage on the
1–Wire bus to determine if there is a short or an interrupt
signal. If there is no short or interrupt (as shown in the
picture), the DS2480 will wait for tPDT and test the volt-
age on the 1–Wire bus for a presence pulse. Regardless
of the result of the presence test, the DS2480 will then
wait for tFILL to expire and then send the command
response byte to the host.
If the test for interrupt or short reveals a logic 0, the
DS2480 will wait for 4096 μs and then test the 1–Wire
bus again. If a logic 0 is detected, the 1–Wire bus is
shorted and a command response byte with the code for
SHORT will be sent immediately. If a logic 1 is detected,
the device will wait for tFILL to expire after which it will
send the command response byte with the code for an
alarming presence pulse. No additional testing for a
presence pulse will be done. The DS2480 will perform
the short/interrupt testing as described also at Over-
drive speed, although interrupt signaling is only defined
for regular speed.
