DS2450S ,1-Wire Quad A/D ConverterPIN DESCRIPTIONDS2450’s to be identified and operated on aV 4.5 to 5.5 VoltsCCcommon 1-Wire busNC D ..
DS2450S+ ,1-Wire Quad A/D ConverterPIN DESCRIPTION DS2450’s to be identified and operated on a V 4.5 to 5.5V CCcommon 1-Wire bus N ..
DS2460 ,SHA-1 Coprocessor with EEPROMELECTRICAL CHARACTERISTICS (-40°C to +85°C, see Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNI ..
DS2460S+ ,SHA-1 Coprocessor with EEPROMAPPLICATIONS ±4kV IEC 1000-4-2 ESD Protection Level on All License Management Pins Secure Feature ..
DS2460S+T , SHA-1 Coprocessor with EEPROMAbridged Data Sheet
DS2480 ,Serial 1-Wire Line DriverPIN DESCRIPTIONfor serial and 1-Wire communicationGND GroundSlew rate controlled 1-Wire pull-down a ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2450S
1-Wire Quad A/D Converter
FEATURES Four high-impedance inputs to measure
analog voltages over the 1-Wire bus User programmable input range (2.56V,
5.12V), resolution (1 to 16 bits) and alarm
thresholds§ 5V, single supply operation Very low power: 2.5 mW active, 25 mW idle Built-in multidrop controller allows multiple
DS2450’s to be identified and operated on acommon 1-Wire bus Responds to Conditional Search if the analog
voltage crosses the alarm thresholds Channels not used as analog input can serve
as open drain digital outputs for closed-loopcontrol Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3k bits per second Overdrive mode boosts communication speedto 142k bits per second On-chip 16-bit CRC-generator for
safeguarding data transfers Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit serial number 8-bit CRC tester) assures
absolute traceability because no two parts are
alike 8-bit family code specifies device
communication requirements to bus master Operating temperature range from -40°C to
+85°C Compact, low cost 8-pin SOIC surface mount
package
PIN ASSIGNMENT
PIN DESCRIPTIONVCC4.5 to 5.5 VoltsDo Not Connect
DATA1-Wire BusGNDGround
AIN-AAnalog Input A
AIN-BAnalog Input B
AIN-CAnalog Input C
AIN-DAnalog Input D
ORDERING INFORMATIONDS2450S8-pin SOIC
DESCRIPTIONThe DS2450 1-Wire Quad A/D Converter is based on a successive-approximation analog to digital
converter with a four to one analog multiplexer. Each input channel has its own register set to store the
input voltage range, resolution, and alarm threshold values as well as flags to enable participation of the
1-WireTM8-PIN SOIC (208 MIL)
DS2450
the comparison. Each A/D conversion is initiated by the bus master. A channel not used as analog inputcan serve as a digital open-drain output. After disabling the input the bus master can directly switch on or
off the open-drain transistor at the selected channel. All device settings are stored in SRAM and kept
non-volatile while the device gets power either through the 1-Wire bus or through its VCC pin. After
powering up a power-on reset flag signals the bus master the need to restore the device settings before the
regular operation can resume. All device registers and conversion read-out registers are organized as
three 8-byte memory pages similar to the Status Memory of a DS2505/6 device. An on-chip CRC16generator protects the communication against transmission errors when reading through the end of a
memory page as well as when writing individual bytes.
OVERVIEWThe block diagram in Figure 1 shows the major function blocks of the device. The DS2450 contains a
factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-
bit family code (20H). The 64-bit ROM portion of the DS2450 not only creates an absolutely unique
electronic identification for the device itself but also is a means to locate and address the device in orderto exercise its control functions.
The device gets its power either from the 1-Wire bus or through its VCC pin. Without a VCC supply the
device stores energy on an internal capacitor during periods where the signal line is high and continues to
operate off of this “parasite” power source during the low times of the 1-Wire line until it returns to high
to replenish the parasite (capacitor) supply. This, however, provides sufficient energy only forcommunication. To perform an A/D conversion a strong pullup of the 1-Wire bus to 5V or a VCC supply
is required.
DS2450 BLOCK DIAGRAM Figure 1
DS2450
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2The DS2450 uses the standard Dallas Semiconductor 1-Wire protocol for data transfers. Communicationto and from the DS2450 requires a single bi-directional line that is typically a port pin of a
microcontroller. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The 1-Wire bus
master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM or 7) Overdrive-
Match ROM. Upon completion of an overdrive ROM command byte executed at standard speed, thedevice will enter Overdrive mode where all subsequent communication occurs at a higher speed. The
protocol required for these ROM function commands is described in Figure 9. After a ROM function
command is successfully executed, the memory and control functions become accessible and the master
may provide any one of the available commands. The protocol for these commands is described in Figure
6. All data is read and written least significant bit first.
64-BIT LASERED ROMEach DS2450 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButtonTM Standards. Theshift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all
DS2450
64-BIT LASERED ROM Figure 3
1-WIRE CRC-GENERATOR Figure 4
DEVICE REGISTERSAll registers of the DS2450 are mapped into a linear memory range of 24 adjacent bytes organized as
three 8-byte pages. The first page, called conversion read-out, contains the memory area where the chip-
internal logic places the results of a conversion for the bus master to read. Starting with channel A at the
lowest address, each channel has an area of 16 bits assigned for the conversion result, as shown in Figure5a. The power-on default for the conversion read-out registers is all zeros. Regardless of the resolution
requested, the most significant bit of the conversion is always at the same bit position. If less than 16-bit
resolution is requested, the least significant bits of the conversion result will be filled with zeros in order
to always generate a 16-bit result. For applications that require less than four analog inputs, one shouldstart using input D for the first channel, input C for the second one, etc. The advantage is that when
reading the conversion results one reaches the end of the page and with it the CRC16 sooner and
minimizes the traffic on the 1-Wire bus. For more details on reading please refer to the Read Memory
command description.
MEMORY MAP PAGE 0, CONVERSION READ-OUT Figure 5aThe control and status information for all channels is located in memory page 1 (Figure 5b). As for theconversion read-out, each channel has assigned 16 bits. The four least significant bits, called RC3 to
RC0, are an unsigned binary number that represents the number of bits to be converted. A code of 1111
(15 decimal) will generate a 15-bit result. For a full 16-bit conversion the code number needs to be 0000.
The next two bits beyond RC3 will always read 0. They have no function and cannot be changed to 1s.
DS2450
The next bits, OC (output control) and OE (enable output) control the alternate use of a channel as output.For normal operation as analog input the OE bit of a channel needs to be 0, rendering the OC bit to a
don’t care. With OE set to 1, a 0 for OC will make the channel’s output transistor conducting, a 1 for OC
will switch the transistor off. With a pullup resistor to a positive voltage, for example, the OC bit will
directly translate into the voltage equivalent of its logic state. Enabling the output does not disable the
analog input. Conversions remain possible, but will result in values close to 0 if the transistor is
conducting.
The IR bit in the second byte of a channel’s control and status memory selects the input voltage range.
With IR set to 0, the highest possible conversion result is reached at 2.55V. Setting IR to 1 requires an
input voltage of 5.10V for the same result. The next bit beyond IR has no function. It will always read 0and cannot be changed to 1.
The next two bits, AEL alarm enable low and AEH alarm enable high, control whether the device will
respond to the Conditional Search command (see ROM Functions) if a conversion results in a value
higher (AEH) than or lower (AEL) than the channel’s alarm threshold voltage as specified in the alarm
settings. The alarm flags AFL (low) and AFH (high) tell the bus master whether the channel’s inputvoltage was beyond the low or high threshold at the latest conversion. These flags are cleared
automatically if a new conversion reveals a non-alarming value. They can alternatively be written to 0 by
the bus master without a conversion.
The next bit of a channel’s control and status memory always reads 0 and cannot be changed to 1. The
POR bit (power on reset) is automatically set to 1 as the device performs a power-on reset cycle. As long
as this bit is set the device will always respond to the Conditional Search command in order to notify the
bus master that the control and threshold data is no longer valid. After powering-up the POR bit needs to
be written to 0 by the bus master. This may be done together with restoring the control and threshold
data. It is possible for the bus master to write the POR bit to a 1. This will make the device participate inthe conditional search but will not generate a reset cycle. Since the POR bit is related to the device and
not channel-specific the value written with the most recent setting of an input range or alarm enable
applies. The power-on default setting for the control/status data is 08h for the first and 8Ch for the
second byte of each channel.
MEMORY MAP PAGE 1, CONTROL/STATUS DATA Figure 5b0
DS2450
MEMORY MAP PAGE 2, ALARM SETTINGS Figure 5cThe registers for the alarm threshold voltages of each channel are located in memory page 2 with the low
threshold being at the lower address (Figure 5c). The power-on default thresholds are 00h for low alarmand FFh for high alarm. The alarm settings are always eight bits. For a resolution higher or equal to
eight bits the alarm flag will be set if the eight most significant bits of the conversion result yield a
number higher than stored in the high alarm register (AFH) or lower than stored in the low alarm register
(AFL). For a resolution lower than eight bits the least significant bits of the alarm registers are ignored.
There is a fourth memory page in the address range of 18 to 1F used during calibration at the factory.
This memory page is accessible to the user through the Read Memory and Write Memory commands.
Changing the data of this page arbitrarily will de-calibrate the A/D converter or make the device
nonfunctional until it undergoes a power-on reset.
If the device is VCC powered the analog circuitry
must be kept permanently active by writing a value of 40 hex to memory address 1C after power-up.This also eliminates the offset time otherwise needed with each CONVERT command. See the
description of the CONVERT command for details.
FUNCTION COMMANDSThe Function Command Flow Chart (Figure 6) describes the protocols necessary for accessing the device
registers. Since the memory map of the DS2450 is small compared to the 16-bit addressing capabilitiesthe 11 most significant bits of the address will be forced to 0 before they enter the CRC-generator. The
communication between master and DS2450 takes place either at regular speed (default, OD = 0) or at
Overdrive Speed (OD = 1). If not explicitly set into Overdrive mode the device assumes regular speed.
READ MEMORY [AAH]The Read Memory command is used to read conversion results, control/status data and alarm settings.
The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) thatindicates a starting byte location within the memory map. With every subsequent read data time slot the
bus master receives data from the DS2450 starting at the supplied address and continuing until the end of
an eight-byte page is reached. At that point the bus master will receive a 16-bit CRC of the command
byte, address bytes and data bytes. This CRC is computed by the DS2450 and read back by the busmaster to check if the command word, starting address and data were received correctly. If the CRC read
by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated.
Note that the initial pass through the Read Memory flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC-generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing throughto the last byte of the addressed page. Subsequent passes through the Read Memory flow chart will
DS2450
WRITE MEMORY [55H]The Write Memory command is used to write to memory pages 1 and 2 in order to set the channel-specific control data and alarm thresholds. The bus master will follow the command byte with a two byte
starting address (TA1=(T7:T0), TA2=(T15:T8)) and a data byte of (D7:D0). A 16-bit CRC of the
command byte, address bytes, and data byte is computed by the DS2450 and read back by the bus master
to confirm that the correct command word, starting address, and data byte were received. Now the
DS2450 copies the data byte to the specified memory location. With the next eight time slots the bus
master receives a copy of the same byte but read from memory for verification. If the verification fails, aReset Pulse should be issued and the current byte address should be written again.
If the bus master does not issue a Reset Pulse and the end of memory was not yet reached, the DS2450
will automatically increment its address counter to address the next memory location. The new two-byteaddress will also be loaded into the 16-bit CRC-generator as a starting value. The bus master will send
the next byte using eight write time slots. As the DS2450 receives this byte it also shifts it into the CRC-
generator and the result is a 16-bit CRC of the new data byte and the new address. With the next sixteen
read time slots the bus master will read this 16-bit CRC from the DS2450 to verify that the address
incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse
should be issued in order to repeat the Write Memory command sequence.
Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC-generator, followed by the two address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2450automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not
shifting) the new (incremented) address into the CRC-generator and then shifting in the new data byte.
The decision to continue after having received a bad CRC or if the verification fails is made entirely by
the bus master. Write access to the conversion read-out registers is not possible. If a write attempt is
made to a page 0 address the device will follow the Write Memory flow chart correctly but theverification of the data byte read back from memory will usually fail. The Write Memory command
sequence can be ended at any point by issuing a Reset Pulse.
DS2450
FUNCTION COMMAND FLOW CHART Figure 6
DS2450
FUNCTION COMMAND FLOW CHART Figure 6 (continued)
DS2450
CONVERT [3CH]The Convert command is used to initiate the analog to digital conversion for one or more channels at the
resolution specified in memory page 1, control/status data. The conversion takes between 60 and 80 ms
per bit plus an offset time of maximum 160 ms every time the convert command is issued. For four
channels with 12-bit resolution each, as an example, the convert command will not take more than
4x12x80 ms plus 160 ms offset, which totals 4 ms. If the DS2450 gets its power through the VCC pin, thebus master may communicate with other devices on the 1-Wire bus while the DS2450 is busy with A/D
conversions. If the device is powered entirely from the 1-Wire bus, the bus master must instead provide a
strong pullup to 5V for the estimated duration of the conversion in order to provide sufficient energy.
The conversion is controlled by the input select mask (Figure 7a) and the read-out control byte (Figure7b). In the input select mask the bus master specifies which channels participate in the conversion. A
channel is selected if the bit associated to the channel is set to 1. If more than one channel is selected, the
conversion takes place one channel after another in the sequence A, B, C, D, skipping those channels that
are not selected. The bus master can read the result of a channel’s conversion before the conversion of all
the remaining selected channels is completed. In order to distinguish between the previous result and thenew value the bus master uses the read-out control byte. This byte allows presetting the conversion read-
out registers for each selected channel to all 1’s or all 0’s. If the expected result is close to 0 then one
should preset to all 1’s or to all 0’s if the conversion result will likely be a high number. In applications
where the bus master can wait until all selected channels are converted before reading, a preset of the
read-out registers is not necessary.
Note that for a channel not selected in the input select mask, thechannel’s read-out control setting has no effect. If a channel constantly yields conversion results close to
0 the channel’s output transistor may be conducting. See section Device Registers for details.
INPUT SELECT MASK (CONVERSION COMMAND) Figure 7a
READ-OUT CONTROL (CONVERSION COMMAND) Figure 7bFollowing the Convert command byte the bus master transmits the input select mask and the read-outcontrol byte. Now the bus master reads the CRC16 of the command byte, select mask and control byte.
The conversion will start no earlier than 10 ms after the most significant bit of the CRC is received by the
bus master.
With a parasitic power supply the bus master must activate the strong pullup within this 10 ms window for
a duration that is estimated as explained above. After that, the data line returns to an idle high state and
communication on the bus can resume. The bus master would normally send a reset pulse to exit the
DS2450
With VCC power supply the bus master may either send a reset pulse to exit the Convert command orcontinuously generate read data time slots. As long as the DS2450 is busy with conversions the bus
master will read 0’s. After the conversion is completed the bus master will receive 1’s instead. Since in a
open-drain environment a single 0 overwrites multiple 1’s the bus master can monitor multiple devices
converting simultaneously and immediately knows when the last one is ready. As in the parasitically
powered scenario the bus master finally has to exit the Convert command by issuing a rest pulse.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2450 is a slave device. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol
defines bus transactions in terms of the bus state during specific time slots that are initiated on the fallingedge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of
the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATIONThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2450 is open drain with an internal circuit equivalentto that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed can be
boosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup
resistor of approximately 5kW at regular speed or maximum 2.2kW at Overdrive speed for
communication. During A/D conversions the bus master must provide a strong pullup to 5V to supplysufficient energy if the DS2450 is powered entirely from the 1-Wire bus.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16 ms (Overdrive Speed) or more than 120 ms (regular speed), one or more devices on the
bus may be reset.
HARDWARE CONFIGURATION Figure 8
DS2450
TRANSACTION SEQUENCEThe protocol for accessing the DS2450 via the 1-Wire port is as follows:§ Initialization ROM Function Command Memory/Convert Function Command Transaction/Data
INITIALIZATIONAll transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequenceconsists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2450 is on the bus and is ready to
operate. For more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDSOnce the bus master has detected a presence, it can issue one of the seven ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart inFigure 9):
Read ROM [33H]This command allows the bus master to read the DS2450’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS2450 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the sametime (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will result in a mismatch of the CRC.
MATCH ROM [55H]The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2450 on a multidrop bus. Only the DS2450 that exactly matches the 64-bit ROM sequencewill respond to the following memory/convert function command. All slaves that do not match the 64-bit
ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices
on the bus.
SKIP ROM [CCH]This command can save time in a single drop bus system by allowing the bus master to access the
memory/ convert functions without providing the 64-bit ROM code. If more than one slave is present onthe bus and a read command is issued following the Skip ROM command, data collision will occur on the
bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
SEARCH ROM [F0H]When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a processof elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
