DS2433X#U ,4Kb 1-Wire EEPROMPIN DESCRIPTION 8-bit family code specifies DS2433PR-35 SOcommunication requirements to readerPin ..
DS2433X-S#T ,4Kb 1-Wire EEPROMFEATURES 4096 bits Electrically Erasable ProgrammableRead-Only Memory (EEPROM)PR-35 Unique, facto ..
DS2434 ,Battery identification chipPIN DESCRIPTIONPIN PIN14-PIN SOIC PR35 SYMBOL DESCRIPTION1 1 GND Ground pin14 2 DQ Data Input/Outpu ..
DS2435 ,Battery identification chip with time/temperature histogramPIN DESCRIPTIONPIN PIN16-PIN SSOP PR-35 SYMBOL DESCRIPTION8, 9 1 GNDGround pin.12 DQ Data Input/Out ..
DS2435 ,Battery identification chip with time/temperature histogramPIN DESCRIPTIONGND - GroundDQ - Data In/OutV - Supply VoltageDDNC - No ConnectDESCRIPTIONThe DS2435 ..
DS2435 ,Battery identification chip with time/temperature histogramApplications include portable computers,portable/cellular phones, consumer NC 6 11NCelectronics, an ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2433+-DS2433X#U-DS2433X-S#T
4Kb 1-Wire EEPROM
FEATURES4096 bits Electrically Erasable Programmable
Read-Only Memory (EEPROM)Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assuresabsolute identity because no two parts are
alikeBuilt-in multidrop controller ensures
compatibility with other MicroLAN™
productsMemory partitioned into sixteen 256-bit pages
for packetizing data256-bit scratchpad with strict read/write
protocols ensures integrity of data transferReduces control, address, data, and power to asingle data pinDirectly connects to a single port pin of a
microprocessor and communicates at up to
16.3kbpsOverdrive mode boosts communication speed
to 142kps8-bit family code specifies DS2433
communication requirements to readerPresence detector acknowledges when readerfirst applies voltageLow cost PR-35 or 8-pin SO surface mount
packageReads and writes over a wide voltage range of
2.8V to 6.0V from -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTION
PR-35SOPin 1GroundNCPin 2DataNC
Pin 3NCData
Pin 4—Ground
Pin 5-8—NC
ORDERING INFORMATIONDS2433 PR-35 package
DS2433S 8-pin SOIC package
DS2433S/T&R Tape & Reel version of
DS2433S
DS2433X Chip Scale Pkg., Tape &Reel
DS2433X-SChip-Scale Pkg, 2.5k pc.,
Tape & Reel
SILICON LABEL DESCRIPTION®
DS2433
4kb 1-Wire EEPROMDATA
GND
8-Pin SO (208mil)21
BOTTOM VIEW
PR-35
DS2433
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (23h) plus
4096 bits of user-programmable EEPROM. The power to read and write the DS2433 is derived entirely
from the 1-Wire communication line. The memory is organized as sixteen pages of 256 bits each. The
scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to thescratchpad where it may be read back for verification. A copy scratchpad command will then transfer the
data to memory. This process insures data integrity when modifying the memory. The 64-bit registration
number provides a guaranteed unique identity which allows for absolute traceability and acts as node
address if multiple DS2433 are connected in parallel to form a local network. Data is transferred serially
via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SOICpackages provide a compact enclosure that allows standard assembly equipment to handle the device
easily for attachment to printed circuit boards or wiring. Typical applications include storage of
calibration constants, board identification and product revision status.
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2433. The DS2433 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,and 3) 4096-bit EEPROM. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The
bus master must first provide one of the six ROM Function Commands, 1)Read ROM, 2) Match ROM,
3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion
of an overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode
where all subsequent communication occurs at a higher speed. The protocol required for these ROMfunction commands is described in Figure 9. After a ROM function command is successfully executed,
the memory functions become accessible and the master may provide any one of the four memory
function commands. The protocol for these memory function commands is described in Figure 7. All data
is read and written least significant bit first.
PARASITE POWERThe block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and
voltage requirements are met.
DS2433
Figure 1. DS2433 BLOCK DIAGRAM
64-BIT LASERED ROMEach DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register andXOR gates as shown in Figure 4. The polynomial is X8+ X5+ X4+ 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton® Standards.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial numberis entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.
MEMORYThe memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS2433 contains pages 0 through 15 that make up the 4096-bit EEPROM. Thescratch-pad is an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUSBecause of the serial data transfer, the DS2433 employs three address registers, called TA1, TA2 and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be
written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,the master only has read access to this register. The lower five bits of the E/S register indicate the address
of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the
E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or
if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear
the PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address also
DS2433
bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency,
the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0.
Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH.
However, it is possible to write one or several contiguous bytes somewhere within a page. The endingoffset together with the Partial Flag support the master checking the data integrity after a Write command.
The highest valued bit of the E/S register, called AA is valid only if the PF flag reads 0. If PF is 0 and AA
is 1, a copy has taken place. The AA bit is cleared when the device receives a write scratchpad command.
WRITING WITH VERIFICATIONTo write data to the DS2433, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written tothe scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address and data at the end of the write scratchpad command sequence.
Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the
communication was successful and proceed to the Copy Scratchpad command. If the master could not
receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to verifydata integrity. As preamble to the scratchpad data, the DS2433 repeats the target address TA1 and TA2
and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not
need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag
together with a cleared PF flag indicates that the Write command was not recognized by the device. Ifeverything went correctly, both flags are cleared and the ending offset indicates the address of the last
byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the
contents of these registers by reading the scratchpad or derive it from the target address and the amount ofdata to be written. As soon as the DS2433 has received these bytes correctly, it will copy the data to the
requested location beginning at the target address.
DS2433
Figure 2. HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL
Figure 3. 64-BIT LASERED ROMMSBLSB
MSBLSBMSBLSBMSBLSB
Figure 4. 1-WIRE CRC GENERATOR
MEMORY FUNCTION COMMANDSThe “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS2433 takes place
either at regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the
Overdrive Mode the DS2433 assumes regular speed.
WRITE SCRATCHPAD COMMAND [0FH]After issuing the write scratchpad command, the master must first provide the 2-byte target address,
DS2433
writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be
ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command the CRC generator inside the DS2433 (see Figure 12)calculates a CRC over the entire data stream, starting at the command code and ending at the last data
byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC
generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target
Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write
Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 readtime slots and will receive the CRC generated by the DS2433.
The memory address range of the DS2433 is 0000H to 01FFH. If the bus master sends a target address
higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as
they are shifted into the internal address register. The Read Scratchpad command will reveal the targetaddress as it will be used by the DS2433. The master will identify such address modifications by
comparing the target address read back to the target address transmitted. If the master does not read the
scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the
target address the master sends will not match the value the DS2433 expects.
READ SCRATCHPAD COMMAND [AAH]This command is used to verify scratchpad data and target address. After issuing the read scratchpadcommand, the master begins reading. The first two bytes will be the target address. The next byte will be
the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:
T0). The master may read data until the end of the scratchpad after which the data read will be all logic
1’s.
COPY SCRATCHPAD [55H]This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, the master must provide a 3-byte authorization pattern which can be obtained by reading the
scratchpad for verification. This pattern must exactly match the data contained in the three address
registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag
will be set and the copy will begin. Copy takes 5 ms maximum during which the voltage on the 1-Wirebus must not fall below 2.8V. A pattern of alternating 1s and 0s will be received after the data has been
copied until a Reset Pulse is issued by the master.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset through the ending offset, will be copied to memory, starting at the target address.Anywhere from 1 to 32 bytes may be copied to memory with this command.
Figure 5. DS2433 MEMORY MAPADDRESS
0000H TO
001FH
003FH
01DFH
0020H TO
0040H TO
PAGE 0
PAGE 1
PAGE 2
DS2433
Figure 6. ADDRESS REGISTER
READ MEMORY [F0H]The read memory command may be used to read the entire memory. After issuing the command, the
master must provide the 2-byte target address. After the two bytes, the master reads data beginning from
the target address and may continue until the end of memory, at which point logic 1’s will be read. It isimportant to realize that the target address registers will contain the address provided. The ending
offset/data status byte is unaffected.
The hardware of the DS2433 provides a means to accomplish error-free writing to the memory section.
To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it isrecommended to packetize data into data packets of the size of one memory page each. Such a packet
would typically store a 16-bit CRC with each page of data to insure rapid, error-free data transfers that
eliminate having to read a page multiple times to determine if the received data is correct or not. (See the
Book of DS19xx iButton Standards, Chapter 7 or Application Note 114 for the recommended file
structure.)
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
1) THIS BIT WILL ALWAYS BE 0.
DS2433
Figure 7. MEMORY FUNCTION FLOW CHART
DS2433
Figure 7. MEMORY FUNCTION FLOW CHART (continued)
DS2433
MEMORY FUNCTION EXAMPLEExample: Write two data bytes to memory location 0026 and 0027. Read entire memory.
DS2433
Figure 8. HARDWARE CONFIGURATION*5k��is adequate for reading the DS2433. To write to a single device, a 2.2k��resistor and VPUP of at
least 4.0V is sufficient. For writing multiple DS2433s simultaneously or operation at low VPUP, the RPU
should be bypassed by a low-impedance pullup to VPUP while the device copies the scratchpad to
EEPROM. Depending on the 1-Wire communication speed and the bus-load characteristics, the optimal
pullup resistor (RPU) value will be in the 1.5k� to 5k� range.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2433 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system
is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling
(signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state duringspecific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more
detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATIONThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have opendrain or 3-state outputs. The 1-Wire port of the DS2433 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps
by activating the Overdrive Mode. The 1-Wire bus requires a pullup resistor of approximately 5k�.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16�s (Overdrive Speed) or more than 120�s (regular speed), one or more devices on the
bus may be reset.
TRANSACTION SEQUENCEThe protocol for accessing the DS2433 via the 1-Wire port is as follows:InitializationROM Function CommandMemory Function CommandTransaction/Data
