DS2431 ,1024-Bit 1-Wire EEPROMFEATURES ® 1024 Bits of EEPROM Memory Partitioned into The DS2431 is a 1024-bit, 1-Wire EEPROM c ..
DS2431 ,1024-Bit 1-Wire EEPROMAPPLICATIONS PART TEMP RANGE PIN-PACKAGE Accessory/PC Board Identification DS2431 -40°C to 85°C TO- ..
DS2431 ,1024-Bit 1-Wire EEPROMFEATURES ® 1024 Bits of EEPROM Memory Partitioned into The DS2431 is a 1024-bit, 1-Wire EEPROM c ..
DS2431 ,1024-Bit 1-Wire EEPROM DS2431 1024-Bit 1-Wire EEPROM
DS2431 ,1024-Bit 1-Wire EEPROMAPPLICATIONS PART TEMP RANGE PIN-PACKAGE Accessory/PC Board Identification DS2431 -40°C to 85°C TO- ..
DS2431 ,1024-Bit 1-Wire EEPROM DS2431 1024-Bit 1-Wire EEPROM
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2431
1024-Bit 1-Wire EEPROM
GENERAL DESCRIPTION The DS2431 is a 1024-bit, 1-Wire® EEPROM chip
organized as four memory pages of 256 bits each.
Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special
feature, the four memory pages can individually be write protected or put in EPROM-emulation mode,
where bits can only be changed from a 1 to a 0 state. The DS2431 communicates over the single-
conductor 1-Wire bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol.
Each device has its own unalterable and unique 64-bit ROM registration number that is factory lasered
into the chip. The registration number is used to address the device in a multidrop 1-Wire net
environment.
APPLICATIONS Accessory/PC Board Identification Medical Sensor Calibration Data Storage
Analog Sensor Calibration Including IEEE-P1451.4 Smart Sensors
Ink and Toner Print Cartridge Identification After-Market Management of Consumables
TYPICAL OPERATING CIRCUIT
FEATURES 1024 Bits of EEPROM Memory Partitioned into
Four Pages of 256 Bits Individual Memory Pages can be Permanently Write Protected or Put in EPROM-Emulation
Mode ("Write to 0") Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air) Reads and Writes Over a Wide Voltage Range of 2.8V to 5.25V from -40°C to +85°C Communicates to Host with a Single Digital
Signal at 15.4kbps or 111kbps Using 1-Wire Protocol
ORDERING INFORMATION PIN CONFIGURATION Commands, Registers, and Modes are capitalized for clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
DS2431
1024-Bit 1-Wire EEPROM
DS2431: 1024-Bit, 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.5V, +6V
I/O Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C
Storage Temperature Range -40°C to +85°C Soldering Temperature See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.)
DS2431: 1024-Bit, 1-Wire EEPROM
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 3: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k� resistor is used to pull up the data line, 2.5µs
after VPUP has been applied the parasite capacitance will not affect normal communications.
Note 4: Guaranteed by design, simulation only. Not production tested.
Note 5: VTL, VTH, and VHY are a function of the internal supply voltage.
Note 6: Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 7: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.
Note 8: Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic '0'.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: Applies to a single DS2431 attached to a 1-Wire line.
Note 12: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 14: Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 15: � represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH.
Note 16: � represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus
master.
Note 17: Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a
low impedance bypass of Rpup which can be activated during programming may need to be added.
Note 18: Interval begins tWiLMIN after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from IPROG to IL.
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
DS2431: 1024-Bit, 1-Wire EEPROM
PIN DESCRIPTION DESCRIPTION The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes,
and a fully-featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the
register page. Data is first written to the scratchpad from which it can be read back. After the data has been verified, a copy scratchpad command transfers the data to its final memory location. Applications of the DS2431
include accessory/PC board identification, medical sensor calibration data storage, analog sensor calibration including IEEE-P1451.4 Smart Sensors, ink and toner print cartridge identification, and after-market management
of consumables.
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS2431. The DS2431 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, and 4) 64-bit register page. The hierarchical structure of the 1-Wire protocol is shown in Figure
2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of
an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is
described in Figure 9. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure 7. All data is read and written least significant bit first.
DS2431: 1024-Bit, 1-Wire EEPROM
Figure 1. Block Diagram
Figure 2. Hierarchical Structure for 1-Wire Protocol DS2431: 1024-Bit, 1-Wire EEPROM
64-BIT LASERED ROM Each DS2431 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire CRC is available in Application Note 27. The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
Figure 4. 1-Wire CRC Generator DS2431: 1024-Bit, 1-Wire EEPROM
Figure 5. Memory Map Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither
write-protect the address nor activate any function.
MEMORY Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the
registers have unrestricted read access. The DS2431 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into 4 memory pages (32 bytes each). These 4 pages are the primary data memory.
Each page can be individually set to open (unprotected), write protected, or EPROM mode by setting the associated protection byte in the register row. The last two rows contain protection registers, and reserved bytes.
The register row consists of 4 protection control bytes, a copy protection byte, the factory byte, and two user byte/manufacture ID bytes. The manufacturer ID can be a customer-supplied identification code that assists the application software in identifying the product the DS2431 is associated with. Contact the factory to set up and
register a custom manufacturer ID. The last row is reserved for future use. It is undefined in terms of R/W
functionality and should not be used.
In addition to the main EEPROM array, an 8-byte volatile scratchpad is included. Writes to the EEPROM array are a two-step process. First, data is written to the scratchpad, and then copied into the main array. This allows the user to first verify the data written to scratchpad prior to copying into the main array. The device only supports full
row (8-byte) copy operations. In order for data in the scratchpad to be valid for a copy operation, the address
supplied with a Write Scratchpad must start on a row boundary, and 8 full bytes must be written into the scratchpad.
DS2431: 1024-Bit, 1-Wire EEPROM
The protection control registers determine how incoming data on a write-scratchpad command is loaded into the
scratchpad. A protection setting of 55h (Write Protect) causes the incoming data to be ingnored and the target address main memory data to be loaded into the scratchpad. A protection setting of AAh (EPROM Mode) causes
the logical AND of incoming data and target address main memory data to be loaded into the scratchpad. Any other protection control register setting leaves the associated memory page open for unrestricted write access.
Protection control byte settings of 55h or AAh also write protects the protection control byte. The protection-control byte setting of 55h does not block the copy. This allows write-protected data to be refreshed (i. e., reprogrammed
with the current data) in the device.
The copy protection byte is used for a higher level of security, and should only be used after all other protection control bytes, user bytes, and write-protected pages are set to their final value. If the copy protection byte is set to
55h or AAh, all copy attempts to the register row and user byte row are blocked. In addition, all copy attempts to write-protected main memory pages (i. e., refresh) are blocked.
ADDRESS REGISTERS AND TRANSFER STATUS The DS2431 employs three address registers: TA1, TA2, and E/S (Figure 6). These registers are common to many
other 1-Wire devices but operate slightly differently with the DS2431. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer-
status register, used to verify data integrity with write commands. ES bits E2:E0 are loaded with the incoming T2:T0 on a write-scratchpad command, and increment on each subsequent data byte. This is in effect a byte-
ending offset counter within the 8-byte scratchpad. Bit 5 of the E/S register, called PF, is a logic 1 if the data in the scratchpad is not valid due to a loss of power or if the master sends less bytes than needed to reach the end of the
scratchpad. For a valid write to the scratchpad, T2:T0 must be 0 and the master must have sent 8 data bytes. Bits 3, 4, and 6 have no function; they always read 0. The highest valued bit of the E/S register, called AA or
Authorization Accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag.
Figure 6. Address Registers
DS2431: 1024-Bit, 1-Wire EEPROM
WRITING WITH VERIFICATION
To write data to the DS2431, the scratchpad has to be used as intermediate storage. First the master issues the
Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Note that Copy Scratchpad commands must be performed on 8-byte boundaries, i. e., the 3 LSBs of
the target address (T2..T0) must be equal to 000b. If T2..T0 are sent with non-zero values, the copy function will be blocked. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16 of
the command, address (actual address sent) and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the
communication was successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad
data, the DS2431 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to
the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the
Write command. If everything went correctly, both flags are cleared. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for
example. This command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master should obtain the contents of these registers by reading the scratchpad.
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the
DS2431. An example on how to use these functions to write to and read from the device is included at the end of this document. The communication between master and DS2431 takes place either at regular speed (default, OD =
0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode, the DS2431 assumes regular speed. WRITE SCRATCHPAD COMMAND [0Fh]
The Write Scratchpad command applies to the data memory, and the writable addresses in the register page. In order for the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad
command of 8 bytes starting at a valid row boundary. The Write Scratchpad command accepts invalid addresses, and partial rows, but subsequent Copy Scratchpad commands are blocked. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by
the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T2:T0. The ES bits E2:E0 are loaded with the starting byte offset, and increment with each susequent byte. Effectively,
E2:E0 is the byte offset of the last full byte written to the scratchpad. Only full data bytes are accepted.
When executing the Write Scratchpad command, the CRC generator inside the DS2431 (Figure 13) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the
master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses (TA1 and TA2), and all the
data bytes. Note that the CRC16 calculation is performed with the actual TA1 and TA2 and data sent by the master. The master may end the Write Scratchpad command at any time. However, if the end of the scratchpad is
reached (E2:E0 = 111b), the master may send 16 read-time slots and receive the CRC generated by the DS2431.
If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad
is loaded with the bitwise logical AND of the transmitted data and data already in memory.
DS2431: 1024-Bit, 1-Wire EEPROM
Figure 7-1. Memory Function Flow Chart
From ROM Functions
DS2431: 1024-Bit, 1-Wire EEPROM
Figure 7-2. Memory Function Flow Chart (continued)
DS2431: 1024-Bit, 1-Wire EEPROM
Figure 7-3. Memory Function Flow Chart (continued)
memory locations.
