DS2431P+T&R ,1024-Bit 1-Wire EEPROMElectrical Characteristics(T = -40°C to +85°C.) (Note 1)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UN ..
DS2431P+TR , 1024-Bit, 1-Wire EEPROM
DS2431P-A1+T ,1024-Bit 1-Wire EEPROMFeatures®The DS2431 is a 1024-bit, 1-Wire EEPROM chip orga- ● Easily Add Traceability and Relevant ..
DS2431Q+T , 1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently
DS2431Q+U ,1024-Bit 1-Wire EEPROMElectrical Characteristics(T = -40°C to +85°C.) (Note 1)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UN ..
DS2431X+U ,1024-Bit 1-Wire EEPROMApplicationsfrom 2.8V to 5.25V from -40°C to +85°C● Accessory/PCB Identiication• Communicates to Ho ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2431+-DS2431P+-DS2431P+T&R-DS2431P-A1+T-DS2431Q+U-DS2431X+U-DS2431X-S+
1024-Bit 1-Wire EEPROM
General DescriptionThe DS2431 is a 1024-bit, 1-Wire® EEPROM chip orga-
nized as four memory pages of 256 bits each. Data is
written to an 8-byte scratchpad, verified, and then copied
to the EEPROM memory. As a special feature, the four
memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. The DS2431 communi-
cates over the single-conductor 1-Wire bus. The com-
munication follows the standard 1-Wire protocol. Each
device has its own unalterable and unique 64-bit ROM
registration number that is factory lasered into the chip.
The registration number is used to address the device in
a multidrop, 1-Wire net environment.
Applications●Accessory/PCB Identiication●Medical Sensor Calibration Data Storage●Analog Sensor Calibration Including IEEE P1451.4 Smart Sensors●Ink and Toner Print Cartridge Identiication●After-Market Management of Consumables
Beneits and Features●Easily Add Traceability and Relevant Information to
Any Individual System1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 BitsIndividual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(Write to 0) Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise●Minimalist 1-Wire Interface Lowers Cost and
Interface ComplexityIEC 1000-4-2 Level 4 ESD Protection
(±8kV Contact, ±15kV Air, typ)Reads and Writes Over a Wide Voltage Range
from 2.8V to 5.25V from -40°C to +85°CCommunicates to Host with a Single Digital Signal
at 15.4kbps or 125kbps
Pin Configurations appear at end of data sheet.1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Note: The leads of TO-92 packages on tape and reel are formed to approximately 100-mil (2.54mm) spacing. For details,
refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
PARTTEMP RANGEPIN-PACKAGEDS2431+-40°C to +85°C3 TO-92
DS2431+T&R-40°C to +85°C3 TO-92
DS2431P+-40°C to +85°C6 TSOC
DS2431P+T&R-40°C to +85°C6 TSOC
DS2431G+U-40°C to +85°C2 SFN (6mm x 6mm)
DS2431G+T&R-40°C to +85°C2 SFN (6mm x 6mm)
(2.5k pcs)
DS2431GA+U-40°C to +85°C2 SFN (3.5mm x 6.5mm)
DS2431GA+T&R-40°C to +85°C2 SFN (3.5mm x 6.5mm)
(2.5k pcs)
DS2431Q+T&R-40°C to +85°C6 TDFN-EP* (2.5k pcs)
DS2431X-S+-40°C to +85°C3x3 UCSPR (2.5k pcs)
DS2431X+-40°C to +85°C3x3 UCSPR (10k pcs)
RPUP
VCC
GND
DS2431
DS24311024-Bit, 1-Wire EEPROM
Typical Operating Circuit
Ordering Information
IO Voltage Range to GND........................................-0.5V to +6V
IO Sink Current....................................................................20mA
Operating Temperature Range.............................-40°C to +85°C
Junction Temperature........................................................+150°C
Storage Temperature Range..............................-55°C to +125°C
Lead Temperature (excluding UCSP, soldering, 10s).......+300°C
Soldering Temperature (reflow)
TO-92............................................................................+250°C
AIl other packages, excluding SFN...............................+260°C
(TA = -40°C to +85°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
IO PIN: GENERAL DATA1-Wire Pullup Voltage VPUP(Note 2)2.85.25V
1-Wire Pullup Resistance RPUP(Notes 2, 3)0.32.2kΩ
Input CapacitanceCIO(Notes 4, 5)1000pF
Input Load Current ILIO pin at VPUP0.056.7µA
High-to-Low Switching ThresholdVTL(Notes 5, 6, 7)0.5VPUP -
1.8V
Input Low VoltageVIL(Notes 2, 8)0.5V
Low-to-High Switching ThresholdVTH(Notes 5, 6, 9)1.0VPUP -
1.0V
Switching HysteresisVHY(Notes 5, 6, 10)0.211.70V
Output Low VoltageVOLAt 4mA (Note 11)0.4V
Recovery Time
(Notes 2,12)tREC
Standard speed, RPUP = 2.2kΩ5Overdrive speed, RPUP = 2.2kΩ2
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2kΩ5
Rising-Edge Hold-Off Time (Notes
5, 13)tREHStandard speed 0.55.0µsOverdrive speedNot applicable (0)
Time Slot Duration
(Notes 2, 14)tSLOT
Standard speed 65Overdrive speed8
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLEReset Low Time (Note 2)tRSTLStandard speed 480640µsOverdrive speed4880
Presence-Detect High TimetPDH
Standard speed 1560Overdrive speed26
Presence-Detect Low TimetPDLStandard speed 60240µs
Overdrive speed824
Presence-Detect Sample Time
(Notes 2, 15)tMSPStandard speed 6075µsOverdrive speed610
DS24311024-Bit, 1-Wire EEPROM
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(TA = -40°C to +85°C.) (Note 1)
Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be
required.
Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values
of VTL, VTH, and VHY.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.
Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS2431 present. The power-up pres-
ence detect pulse could be outside this interval, but will be complete within 2ms after power-up.
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
IO PIN: 1-Wire WRITEWrite-Zero Low Time
(Notes 2, 16, 17)tW0L
Standard speed60120Overdrive speed, VPUP > 4.5V515.5
Overdrive speed615.5
Write-One Low Time
(Notes 2, 17)tW1LStandard speed115µsOverdrive speed12
IO PIN: 1-Wire READRead Low Time
(Notes 2, 18)tRLStandard speed515 - dµs
Overdrive speed12 - d
Read Sample Time
(Notes 2, 18)tMSRStandard speedtRL + d15µsOverdrive speedtRL + d2
EEPROMProgramming CurrentIPROG(Notes 5, 19)0.8mA
Programming TimetPROG(Notes 20, 21)10ms
Write/Erase Cycles (Endurance)
(Notes 22, 23)NCYAt +25°C200k—At +85°C (worst case)50k
Data Retention
(Notes 24, 25, 26)tDRAt +85°C (worst case)40Years
DS24311024-Bit, 1-Wire EEPROM
Electrical Characteristics (continued)
Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a
low-impedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy
Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current
drawn by the device has returned from IPROG to IL.
Note 21: tPROG for units branded version “A1” is 12.5ms. tPROG for units branded version “A2” and later is 10ms.
Note 22: Write-cycle endurance is degraded as TA increases.
Note 23: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as TA increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 26: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
*Intentional change; longer recovery time requirement due to modified 1-Wire front-end.
Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.
PARAMETER
LEGACY VALUESDS2431 VALUES
STANDARD SPEED (µs)OVERDRIVE SPEED (µs)STANDARD SPEED (µs)OVERDRIVE SPEED (µs)
MINMAXMINMAXMINMAXMINMAXtSLOT (including tREC)61(undeined)7(undeined)65*(undeined)8*(undeined)
tRSTL480(undeined)48804806404880
tPDH156026156026
tPDL6024082460240824
tW0L60120616601206
15.5DS24311024-Bit, 1-Wire EEPROM
Comparison Table
Detailed DescriptionThe DS2431 combines 1024 bits of EEPROM, an 8-byte
register/control page with up to 7 user read/write bytes,
and a fully featured 1-Wire interface in a single chip. Each
DS2431 has its own 64-bit ROM registration number that
is factory lasered into the chip to provide a guaranteed
unique identity for absolute traceability. Data is transferred
serially through the 1-Wire protocol, which requires only a
single data lead and a ground return. The DS2431 has an
additional memory area called the scratchpad that acts as
a buffer when writing to the main memory or the register
page. Data is first written to the scratchpad from which it
can be read back. After the data has been verified, a Copy
Scratchpad command transfers the data to its final memory
location. The DS2431 applications include accessory/PCB
identification, medical sensor calibration data storage,
analog sensor calibration including IEEE P1451.4 smart
sensors, ink and toner print cartridge identification, and
after-market management of consumables.
OverviewThe block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS2431. The DS2431 has four main data components:
64-bit lasered ROM, 64-bit scratchpad, four 32-byte
pages of EEPROM, and a 64-bit register page.Figure 1. Block Diagram
PIN
NAMEFUNCTIONTSOCTO-92TDFN-EPSFNUCSPR3, 4, 5, 631, 4, 5, 6—A2, A3, C2, N.C.Not Connected221C1IO1-Wire Bus Interface. Open-drain signal
that requires an external pullup resistor.132A1GNDGround Reference————EP
Exposed Pad (TDFN only). Solder
evenly to the board’s ground plane for
proper operation. Refer to Application
Note 3273: Exposed Pads: A Brief
Introduction for additional information.
MEMORY
FUNCTION
CONTROL UNIT
DATA MEMORY
4 PAGES OF
256 BITS EACH
CRC-16
GENERATOR
64-BIT
SCRATCHPAD
1-Wire
FUNCTION CONTROL
64-BIT
LASERED ROM
PARASITE POWER
REGISTER PAGE
64 BITS
DS2431DS24311024-Bit, 1-Wire EEPROM
Pin Description
The hierarchical structure of the 1-Wire protocol is shown
in Figure 2. The bus master must first provide one of
the seven ROM function commands: Read ROM, Match
ROM, Search ROM, Skip ROM, Resume, Overdrive-Skip
ROM, or Overdrive-Match ROM. Upon completion of an
Overdrive-Skip ROM or Overdrive-Match ROM command
byte executed at standard speed, the device enters over-
drive mode where all subsequent communication occurs
at a higher speed. The protocol required for these ROM
function commands is described in Figure 9. After a ROM
function command is successfully executed, the memory
functions become accessible and the master can provide
any one of the four memory function commands. The pro-
tocol for these memory function commands is described
in Figure 7. All data
is read and written least signifi-cant bit first.
64-Bit Lasered ROMEach DS2431 contains a unique ROM code that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next 48
bits are a unique serial number. The last 8 bits are a cyclic
redundancy check (CRC) of the first 56 bits. See Figure 3
for details. The 1-Wire CRC is generated using a polyno-
mial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1.
Additional information about the 1-Wire CRC is available
in Application Note 27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton® Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift reg-
ister contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 2. Hierarchical Structure for 1-Wire Protocol
Figure 3. 64-Bit Lasered ROM
DS2431 COMMAND LEVEL:
AVAILABLE COMMANDS:DATA FIELD AFFECTED:READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG. #, RC-FLAG, OD-FLAG
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
DS2431-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
MSB
8-BIT
CRC CODE48-BIT SERIAL NUMBER
MSBMSBLSB
LSB
LSB
8-BIT FAMILY CODE
(2Dh)
MSBLSB
DS24311024-Bit, 1-Wire EEPROM
Memory AccessData memory and registers are located in a linear address
space, as shown in Figure 5. The data memory and the
registers have unrestricted read access. The DS2431
EEPROM array consists of 18 rows of 8 bytes each.
The first 16 rows are divided equally into four memory
pages (32 bytes each). These four pages are the primary
data memory. Each page can be individually set to open
(unprotected), write protected, or EPROM mode by set-
ting the associated protection byte in the register row. As
a factory default, the entire data memory is unprotected
and its contents are undefined. The last two rows contain
protection registers and reserved bytes. The register row
consists of 4 protection control bytes, a copy-protection
byte, the factory byte, and 2 user byte/manufacture ID
bytes. The manufacturer ID can be a customer-supplied
identification code that assists the application software
in identifying the product the DS2431 is associated with.
Figure 4. 1-Wire CRC Generator
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGEX1X2X3X4
POLYNOMIAL = X8 + X5 + X4 + 1
INPUT DATAX6X7X8
ADDRESS RANGETYPEDESCRIPTIONPROTECTION CODES0000h to 001FhR/(W)Data Memory Page 0—
0020h to 003FhR/(W)Data Memory Page 1—
0040h to 005FhR/(W)Data Memory Page 2—
0060h to 007FhR/(W)Data Memory Page 3—
0080h*R/(W)Protection Control Byte Page 055h: Write Protect P0; AAh: EPROM Mode P0;
55h or AAh: Write Protect 80h
0081h*R/(W)Protection Control Byte Page 1 55h: Write Protect P1; AAh: EPROM Mode P1;
55h or AAh: Write Protect 81h
0082h*R/(W)Protection Control Byte Page 255h: Write Protect P2; AAh: EPROM Mode P2;
55h or AAh: Write Protect 82h
0083h*R/(W)Protection Control Byte Page 3 55h: Write Protect P3; AAh: EPROM Mode P3;
55h or AAh: Write Protect 83h
0084h*R/(W)Copy Protection Byte 55h or AAh: Copy Protect 0080h:008Fh, and Any
Write-Protected Pages
0085hRFactory Byte. Set at Factory.AAh: Write Protect 85h, 86h, 87h;
55h: Write Protect 85h; Unprotect 86h, 87h
0086hR/(W)User Byte/Manufacturer ID —
0087hR/(W)User Byte/Manufacturer ID —
0088h to 008Fh—Reserved—
*Once programmed to AAh or 55h this address becomes read only. All other codes can be stored, but neither write protect
DS24311024-Bit, 1-Wire EEPROM
Contact the factory to set up and register a custom manu-
facturer ID. The last row is reserved for future use. It is
undefined in terms of R/W functionality and should not
be used.
In addition to the main EEPROM array, an 8-byte volatile
scratchpad is included. Writes to the EEPROM array are
a two-step process. First, data is written to the scratchpad
and then copied into the main array. This allows the user
to first verify the data written to the scratchpad prior to
copying into the main array. The device only supports full
row (8-byte) copy operations. For data in the scratchpad
to be valid for a copy operation, the address supplied with
a Write Scratchpad command must start on a row bound-
ary, and 8 full bytes must be written into the scratchpad.
The protection control registers determine how incom-
ing data on a Write Scratchpad command is loaded into
the scratchpad. A protection setting of 55h (write protect)
causes the incoming data to be ignored and the target
address main memory data to be loaded into the scratch-
pad. A protection setting of AAh (EPROM mode) causes
the logical AND of incoming data and target address
main memory data to be loaded into the scratchpad. Any
other protection control register setting leaves the associ-
ated memory page open for unrestricted write access.
Note: For the EPROM mode to function, the entire affected memory page must first be programmed to FFh.
Protection-control byte settings of 55h or AAh also write
protect the protection-control byte. The protection-control
byte setting of 55h does not block the copy. This allows
write-protected data to be refreshed (i.e., reprogrammed
with the current data) in the device.
The copy-protection byte is used for a higher level of
security and should only be used after all other protection
control bytes, user bytes, and write-protected pages are
set to their final value. If the copy-protection byte is set
to 55h or AAh, all copy attempts to the register row and
user-byte row are blocked. In addition, all copy attempts
to write-protected main memory pages (i.e., refresh) are
blocked.
Address Registers and Transfer StatusThe DS2431 employs three address registers: TA1, TA2,
and E/S (Figure 6). These registers are common to many
other 1-Wire devices but operate slightly differently with
the DS2431. Registers TA1 and TA2 must be loaded with
the target address to which the data is written or from
which data is read. Register E/S is a read-only transfer-
status register used to verify data integrity with write com-
mands. E/S bits E[2:0] are loaded with the incoming T[2:0]
on a Write Scratchpad command and increment on each
subsequent data byte. This is, in effect, a byte-ending off-
set counter within the 8-byte scratchpad. Bit 5 of the E/S
register, called PF, is a logic 1 if the data in the scratchpad
is not valid due to a loss of power or if the master sends
fewer bytes than needed to reach the end of the scratch-
pad. For a valid write to the scratchpad, T[2:0] must be 0
and the master must have sent 8 data bytes. Bits 3, 4, and
6 have no function; they always read 0. The highest val-
ued bit of the E/S register, called authorization accepted
(AA), acts as a flag to indicate that the data stored in the
scratchpad has already been copied to the target memory
address. Writing data to the scratchpad clears this flag.
Figure 6. Address Registers
BIT #76543210
TARGET ADDRESS (TA1)T7T6T5T4T3T2T1T0
TARGET ADDRESS (TA2)T15T14T13T12T11T10T9T8
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)0PF00E2E1E0
DS24311024-Bit, 1-Wire EEPROM
Writing with VeriicationTo write data to the DS2431, the scratchpad must be
used as intermediate storage. First, the master issues
the Write Scratchpad command to specify the desired
target address, followed by the data to be written to the
scratchpad. Note that Copy Scratchpad commands must
be performed on 8-byte boundaries, i.e., the three LSBs
of the target address (T2, T1, T0) must be equal to 000b.
If T[2:0] are sent with nonzero values, the copy func-
tion is blocked. Under certain conditions (see the Write
Scratchpad [0Fh] section) the master receives an inverted
CRC-16 of the command, address (actual address sent),
and data at the end of the Write Scratchpad command
sequence. Knowing this CRC value, the master can
compare it to the value it has calculated to decide if the
communication was successful and proceed to the Copy
Scratchpad command. If the master could not receive the
CRC-16, it should send the Read Scratchpad command to
verify data integrity. As a preamble to the scratchpad data,
the DS2431 repeats the target address TA1 and TA2 and
sends the contents of the E/S register. If the PF flag is set,
data did not arrive correctly in the scratchpad, or there was
a loss of power since data was last written to the scratch-
pad. The master does not need to continue reading; it can
start a new trial to write data to the scratchpad. Similarly,
a set AA flag together with a cleared PF flag indicates that
the device did not recognize the Write command.
If everything went correctly, both flags are cleared. Now
the master can continue reading and verifying every data
byte. After the master has verified the data, it can send the
Copy Scratchpad command, for example. This command
must be followed exactly by the data of the three address
registers, TA1, TA2, and E/S. The master should obtain
the contents of these registers by reading the scratchpad.
Memory Function CommandsThe Memory Function Flowchart (Figure 7) describes
the protocols necessary for accessing the memory of the
DS2431. An example on how to use these functions to
write to and read from the device is in the Memory Function
Example section. The communication between the master
and the DS2431 takes place either at standard speed
(default, OD = 0) or at overdrive speed (OD = 1). If not
explicitly set into overdrive mode, the DS2431 assumes
standard speed.
Write Scratchpad [0Fh]The Write Scratchpad command applies to the data
memory and the writable addresses in the register page.
For the scratchpad data to be valid for copying to the
array, the user must perform a Write Scratchpad com-
mand of 8 bytes starting at a valid row boundary. The
Write Scratchpad command accepts invalid addresses
and partial rows, but subsequent Copy Scratchpad com-
mands are blocked.
After issuing the Write Scratchpad command, the master
must first provide the 2-byte target address, followed by
the data to be written to the scratchpad. The data is writ-
ten to the scratchpad starting at the byte offset of T[2:0].
The E/S bits E[2:0] are loaded with the starting byte offset
and increment with each subsequent byte. Effectively,
E[2:0] is the byte offset of the last full byte written to the
scratchpad. Only full data bytes are accepted.
When executing the Write Scratchpad command, the
CRC generator inside the DS2431 (Figure 13) calculates
a CRC of the entire data stream, starting at the command
code and ending at the last data byte as sent by the mas-
ter. This CRC is generated using the CRC-16 polynomial
by first clearing the CRC generator and then shifting in the
command code (0Fh) of the Write Scratchpad command,
the target addresses (TA1 and TA2), and all the data
bytes. Note that the CRC-16 calculation is performed with
the actual TA1 and TA2 and data sent by the master. The
master can end the Write Scratchpad command at any
time. However, if the end of the scratchpad is reached
(E[2:0] = 111b), the master can send 16 read time slots
and receive the CRC generated by the DS2431.
If a Write Scratchpad command is attempted to a write-
protected location, the scratchpad is loaded with the data
already existing in memory rather than the data transmitted.
Similarly, if the target address page is in EPROM mode,
the scratchpad is loaded with the bitwise logical AND of the
transmitted data and data already existing in memory.
DS24311024-Bit, 1-Wire EEPROM
BUS MASTER Tx MEMORY
FUNCTION COMMAND
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
BUS MASTER Rx
TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE
BUS MASTER Rx
DATA BYTE FROM
SCRATCHPAD
MASTER Tx DATA BYTE
TO SCRATCHPADAPPLIES ONLY
IF THE MEMORY
AREA IS NOT
PROTECTED.
IF WRITE PROTECTED,
THE DS2431 COPIES
THE DATE BYTE FROM
THE TARGET ADDRESS
INTO THE SCRATCHPAD.
IF IN EPROM MODE,
THE DS2431 LOADS
THE BITWISE LOGICAL
AND OF THE TRANSMITTED
BYTE AND THE DATA
BYTE FROM THE TARGETED
ADDRESS INTO THE
SCRATCHPAD.
BUS MASTER
Rx "1"s
DS2431
INCREMENTS
E[2:0]
PF = 0
DS2431
SETS PF = 1
CLEARS AA = 0
SETS E[2:0] = T[2:0]
0Fh
WRITE SCRATCHPADN
MASTER Tx RESET
E[2:0] = 7
T[2:0] = 0
MASTER Tx RESET
DS2431 SETS
SCRATCHPAD
BYTE COUNTER = T[2:0]
AAh
READ SCRATCHPADN
DS2431 Tx CRC-16 OF
COMMAND, ADDRESS,
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER
BUS MASTER
Rx "1"sMASTER Tx RESET
BUS MASTER Rx CRC-16
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
AS SENT BY THE DS2431
MASTER Tx RESET
BYTE COUNTER
= E[2:0]
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 9)
TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)
DS2431
INCREMENTS
BYTE COUNTER
TO FIGURE 7b
FROM FIGURE 7b
DS24311024-Bit, 1-Wire EEPROM
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
DURATION: tPROG*
* 1-Wire IDLE HIGH FOR POWER.
DS2431 COPIES
SCRATCHPAD
DATA TO ADDRESS
BUS MASTER
Rx "1"s
AA = 1
BUS MASTER
Rx "1"s
MASTER Tx RESETNY
MASTER Tx RESET
MASTER Tx RESET
BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE
55h
COPY SCRATCHPADN
DS2431 Tx "0"
DS2431 Tx "1"
F0h
READ MEMORYN
AUTH. CODE
MATCH
T[15:0] < 0090h
PF = 0
ADDRESS < 90hCOPY PROTECTED
BUS MASTER
Rx "1"s
MASTER Tx RESETN
DS2431 SETS MEMORY
ADDRESS = (T[15:0])
BUS MASTER Rx
DATA BYTE FROM
MEMORY ADDRESS
MASTER Tx RESET
ADDRESS < 8Fh
MASTER Tx RESET
DS2431
INCREMENTS
ADDRESS
COUNTER
TO FIGURE 7a
FROM FIGURE 7a
DS24311024-Bit, 1-Wire EEPROM
Read Scratchpad [AAh]The Read Scratchpad command allows verifying the tar-
get address and the integrity of the scratchpad data. After
issuing the command code, the master begins reading.
The first two bytes are the target address. The next byte
is the ending offset/data status byte (E/S) followed by the
scratchpad data, which may be different from what the
master originally sent. This is of particular importance if
the target address is within the register page or a page
in either write-protection mode or EPROM mode. See the
Write Scratchpad [0Fh] section for details. The master
should read through the scratchpad (E[2:0] - T[2:0] + 1
bytes), after which it receives the inverted CRC based on
data as it was sent by the DS2431. If the master continues
reading after the CRC, all data is logic 1.
Copy Scratchpad [55h]The Copy Scratchpad command is used to copy data
from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master must
provide a 3-byte authorization pattern, which should
have been obtained by an immediately preceding Read
Scratchpad command. This 3-byte pattern must exactly
match the data contained in the three address registers
(TA1, TA2, E/S, in that order). If the pattern matches, the
target address is valid, the PF flag is not set, and the tar-
get memory is not copy protected, then the AA flag is set
and the copy begins. All 8 bytes of scratchpad contents
are copied to the target memory location. The duration
of the device’s internal data transfer is tPROG during
which the voltage on the 1-Wire bus must not fall below
2.8V. A pattern of alternating 0s and 1s are transmitted
after the data has been copied until the master issues a
reset pulse. If the PF flag is set or the target memory is
copy protected, the copy does not begin and the AA flag
is not set.
Read Memory [F0h]The Read Memory command is the general function to
read data from the DS2431. After issuing the command,
the master must provide the 2-byte target address. After
these 2 bytes, the master reads data beginning from the
target address and can continue until address 008Fh. If
the master continues reading, the result is logic 1s. The
device’s internal TA1, TA2, E/S, and scratchpad contents
are not affected by a Read Memory command.
1-Wire Bus SystemThe 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS2431 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots, which are initiated
on the falling edge of sync pulses from the bus master.
Hardware ConigurationThe 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or three-
state outputs. The 1-Wire port of the DS2431 is open drain
with an internal circuit equivalent to that shown in Figure 8.multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2431 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. Note that legacy 1-Wire
products support a standard communication speed of
16.3kbps and overdrive of 142kbps. The slightly reduced
rates for the DS2431 are a result of additional recovery
times, which in turn were driven by a 1-Wire physical
interface enhancement to improve noise immunity. The
value of the pullup resistor primarily depends on the net-
work size and load conditions. The DS2431 requires a pullup resistor of 2.2kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16μs (overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
Transaction SequenceThe protocol for accessing the DS2431 through the
1-Wire port is as follows:InitializationROM Function CommandMemory Function CommandTransaction/Data
DS24311024-Bit, 1-Wire EEPROM
InitializationAll transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS2431 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling section.
1-Wire ROM Function CommandsOnce the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS2431 supports. All ROM function commands are 8 bits
long. A list of these commands follows (see the flowchart
in Figure 9).
Read ROM [33h]The Read ROM command allows the bus master to read
the DS2431’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one slave
is present on the bus, a data collision occurs when all
slaves try to transmit at the same time (open drain pro-
duces a wired-AND result). The resultant family code and
48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS2431 on a multidrop bus. Only the DS2431 that exactly
matches the 64-bit ROM sequence responds to the sub-
sequent memory function command. All other slaves wait
for a reset pulse. This command can be used with a single
Search ROM [F0h]When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the registra-
tion number, starting with the least significant bit, the bus
master issues a triplet of time slots. On the first slot, each
slave device participating in the search outputs the true
value of its registration number bit. On the second slot,
each slave device participating in the search outputs the
complemented value of its registration number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choosing
which state to write, the bus master branches in the ROM
code tree. After one complete pass, the bus master knows
the registration number of a single device. Additional
passes identify the registration numbers of the remaining
devices. Refer to Application Note 187: 1-Wire Search
Algorithm for a detailed discussion, including an example.
Skip ROM [CCh]This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. If more
than one slave is present on the bus and, for example,
a read command is issued following the Skip ROM com-
mand, data collision occurs on the bus as multiple slaves
transmit simultaneously (open-drain pulldowns produce a
Figure 8. Hardware Configuration
RPUP
VPUP
BUS MASTEROPEN-DRAIN
PORT PIN100 MOSFET
DATA
DS2431 1-Wire PORTRx = RECEIVE
Tx = TRANSMIT
DS24311024-Bit, 1-Wire EEPROM
DS2431 Tx
PRESENCE PULSE
BUS MASTER Tx
RESET PULSE
BUS MASTER Tx ROM
FUNCTION COMMAND
DS2431 Tx
CRC BYTE
DS2431 Tx
FAMILY CODE
(1 BYTE)
DS2431 Tx
SERIAL NUMBER
(6 BYTES)
RC = 0
MASTER Tx BIT 0
RC = 0RC = 0RC = 0
OD = 0Y
33h
READ ROM
COMMAND
55h
MATCH ROM
COMMAND
BIT 0 MATCHBIT 0 MATCHNNN
F0h
SEARCH ROM
COMMAND
RESET PULSE
CCh
SKIP ROM
COMMAND
RC = 1
MASTER Tx BIT 1
MASTER Tx BIT 63
BIT 1 MATCH
BIT 63 MATCH
RC = 1
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)
DS2431 Tx BIT 0
DS2431 Tx BIT 0
MASTER Tx BIT 0
BIT 1 MATCH
BIT 63 MATCH
DS2431 Tx BIT 1
DS2431 Tx BIT 1
MASTER Tx BIT 1
DS2431 Tx BIT 63
DS2431 Tx BIT 63
MASTER Tx BIT 63
TO FIGURE 9b
TO FIGURE 9b
FROM FIGURE 9b
FROM FIGURE 9b
DS24311024-Bit, 1-Wire EEPROM
