DS2430-DS2430AP-DS2430AX Fast Delivery |IC PHOENIX CO.,LIMITED

DS2430AP ,256 bit 1-Wire EEPROMFEATURES PIN ASSIGNMENT§ 256-bit Electrically Erasable ProgrammableTO-92Read Only Memory (EEPROM) p ..
DS2430AP ,256 bit 1-Wire EEPROMapplications include storage of calibration constants, board identification and productrevision sta ..
DS2430AP+ ,256-Bit 1-Wire EEPROMFEATURES PIN ASSIGNMENT 256-bit Electrically Erasable ProgrammableTO-92Read Only Memory (EEPROM) p ..
DS2430AP+T&R ,256-Bit 1-Wire EEPROMPIN DESCRIPTIONTO-92 TSOCORDERING INFORMATIONPin 1 Ground GroundDS2430A TO-92 packagePin 2 Data Dat ..
DS2430AP+T&R ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2430AP+TR , 256-Bit 1-Wire EEPROM
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS2430-DS2430AP-DS2430AX
256-Bit 1-Wire EEPROM
FEATURES 256-bit Electrically Erasable Programmable
Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bitserial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike Built-in multidrop controller ensures
compatibility with other MicroLAN products EEPROM organized as one page of 32 bytesfor random access Reduces control, address, data and power to a
single data pin Directly connects to a single port pin of a
microprocessor and communicates at up to16.3 kbits per second 8-bit family code specifies DS2430A
communication requirements to reader Presence detector acknowledges when readerfirst applies voltage Low cost TO-92 or 6-pin TSOC surface mount
package Reads and writes over a wide voltage range of
2.8V to 6.0V from -40°C to +85°C
ORDERING INFORMATION
DS2430ATO-92 packageDS2430AP6-pin TSOC package
DS2430ATTape & Reel version of DS2430A
DS2430AVTape & Reel version of DS2430APDS2430AXChip Scale Pkg., Tape & Reel
PIN ASSIGNMENT
PIN DESCRIPTION
TO-92TSOC
Pin 1GroundGroundPin 2DataData
Pin 3NCNC
Pin 4––––NC
Pin 5––––NC
Pin 6––––
256-Bit 1-WireTM EEPROM
3.7 X 4.0 X 1.5 mm
See Mech.
Drawing Section
TSOC PACKAGESee Mech.
Drawings Section
DS2430A
SILICON LABEL DESCRIPTION
The DS2430A 256-bit 1-Wire EEPROM identifies and stores relevant information about the product towhich it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2430A consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus
256 bits of user-programmable EEPROM and a 64-bit one-time programmable application register. The
power to read and write the DS2430A is derived entirely from the 1-Wire communication line. Data is
transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity
which allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that
allows standard assembly equipment to handle the device easily for attachment to printed circuit boards
or wiring. Typical applications include storage of calibration constants, board identification and productrevision status.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit
EEPROM data memory with scratchpad, 3) 64-bit one-time programmable application register with
scratchpad and 4) 8-bit Status Memory. The hierarchical structure of the 1-Wire protocol is shown inFigure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2)
Match ROM, 3) Search ROM, 4) Skip ROM. The protocol required for these ROM Function Commands
is described in Figure 8. After a ROM Function Command is successfully executed, the memory
functions become accessible and the master may provide any one of the four memory function
commands. The protocol for these memory function commands is described in Figure 6. All data is readand written least significant bit first.
64-BIT LASERED ROM
Each DS2430A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code
(14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure
3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XORgates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas
1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift
register bits are initialized to 0. Then starting with the least significant bit of the family code, 1 bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered.
After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting
in the 8 bits of CRC should return the shift register to all 0s.
DS2430A
DS2430A BLOCK DIAGRAM Figure 1
DS2430A
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3
MSBLSBMSBLSBMSBLSB
1-WIRE CRC GENERATOR Figure 4
Polynomial = X8 + X5 + X4 + 1
DS2430A
MEMORY
The memory of the DS2430A consists of three separate sections, called data memory, application registerand status register (Figure 5). The data memory and the application register each has its own intermediate
storage area called scratchpad that acts as a buffer when writing to the device. The data memory can be
read and written as often as desired. The application register, however, is one-time programmable only.
Once the application register is programmed, it is automatically write protected. The status register will
indicate if the application register is already locked or if it is still available for storing data. As long as the
application register is unprogrammed, the status register will read FFh. Copying data from the registerscratchpad to the application register will clear the 2 least significant bits of the status register, yielding a
FCh the next time one reads the status register.
DS2430A MEMORY MAP Figure 5
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
different memory sections of the DS2430A. An example is shown later in this document.
WRITE SCRATCHPAD [0Fh]
After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by
the data to be written to the scratchpad for the data memory. The DS2430A will automatically increment
the address after every byte it received. After having received a data byte for address 1Fh, the address
counter will wrap around to 00h for the next byte and writing continues until the master sends a reset
pulse.
READ SCRATCHPAD [AAh]
This command is used to verify data previously written to the scratchpad before it is copied into the final
storage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1-
byte starting address from where data is to be read. The DS2430A will automatically increment theaddress after every byte read by the master. After the data of address 1Fh has been read, the address
counter will wrap around to 00h for the next byte and reading continues until the master sends a reset
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6
COPY SCRATCHPAD [55h]
After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad
command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM
memory. This command will always copy the data of the entire scratchpad. Therefore, if one desires tochange only a few bytes of the EEPROM data, the scratchpad should contain a copy of the latest
EEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After this
command is issued, the data line must be held at logic high level for at least 10 ms.
READ MEMORY [F0h]
The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy
the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from thedata memory to the scratchpad and to read it, the master must issue the read memory command followed
by the 1-byte starting address from where data is to be read from the scratchpad. The DS2430A will
automatically increment the address after every byte read by the master. After the data of address 1Fh has
been read, the address counter will wrap around to 00h for the next byte and reading continues until the
master sends a reset pulse. If one intends to copy the entire data memory to the scratchpad without
reading data, a starting address is not required; the master may send a reset pulse immediately followingthe command code.
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
WRITE APPLICATION REGISTER [99h]
This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bit
register scratchpad. After issuing the command code, the master must provide a 1-byte address, followed
by the data to be written. The DS2430A will automatically increment the address after every byte it
received. After having received a data byte for address 07h, the address counter will wrap around to 00h
for the next byte and writing continues until the master sends a reset pulse. The Write ApplicationRegister command can be used as long as the application register has not yet been locked. If issued for a
device with the application register locked, the data written to the register scratchpad will be lost.
READ STATUS REGISTER [66h]
The status register is a means for the master to find out if the application register has been programmed
and locked. After issuing the read status register command, the master must provide the validation key00h before receiving status information. The two least significant bits of the 8-bit status register will be 0
if the application register was programmed and locked; all other bits will always read 1. The master may
finish the read status command by sending a reset pulse at any time.
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6 (cont’d)
READ APPLICATION REGISTER [C3h]
This command is used to read the application register or the register scratchpad. As long as the
application register is not yet locked, one will receive data from the register scratchpad. After theapplication register is locked the DS2430A will transmit data from the application register, making the
register scratchpad inaccessible for reading. The contents of the status register indicates where the data
received with this command came from. After issuing the Read Application Register command, the
master must provide the 1-byte starting address from where data is to be read. The DS2430A will
automatically increment the address after every byte read by the master. After the data of address 07h hasbeen read, the address counter will wrap around to 00h for the next byte and reading continues until the
master sends a reset pulse.
COPY & LOCK APPLICATION REGISTER [5Ah]
After the data stored in the register scratchpad has been verified the master may send the Copy & Lock
Application Register command followed by a validation key of A5h to transfer the contents of the entireregister scratchpad to the application register and to simultaneously write-protect it. The master may
cancel this command by sending a reset pulse instead of the validation key. After the validation key was
transmitted, the application register will contain the data of the register scratchpad. Further write accesses
to the application register will be denied. The Copy & Lock Application Register command can only
be executed once.

Partno	Mfg	Dc	Qty	Available	Descript
DS2430		N/a	44	avai	256-Bit 1-Wire EEPROM
DS2430AP	DALLAS	N/a	322	avai	256 bit 1-Wire EEPROM
DS2430AP	MAXIM	N/a	1500	avai	256 bit 1-Wire EEPROM
DS2430AX	MAXIM	N/a	1500	avai	256 bit 1-Wire EEPROM