DS2423P ,4kbit 1-Wire RAM with CounterPIN DESCRIPTIONcompatibility with other MicroLAN productsPin 1 Ground Directly connects to a singl ..
DS2430 ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2430A ,256 bit 1-Wire EEPROMFEATURES PIN ASSIGNMENT 256-bit Electrically Erasable ProgrammableTO-92Read Only Memory (EEPROM) p ..
DS2430A ,256 bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2430A ,256 bit 1-Wire EEPROMPIN DESCRIPTIONTO-92 TSOCORDERING INFORMATIONPin 1 Ground GroundDS2430A TO-92 packagePin 2 Data Dat ..
DS2430A ,256 bit 1-Wire EEPROMapplications include storage of calibration constants, board identification, and productrevision st ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2423P
4kbit 1-Wire RAM with Counter
FEATURES4096 bits of SRAMFour 32-bit, read-only countersActive-low external trigger inputs for two of
the counters with on-chip debouncing
compatible with reed and Wiegand switchesUnique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alikeMemory partitioned into 16 256-bit pages in
for packetizing data256-bit scratchpad with strict read/write
protocols ensures integrity of data transferOn-chip 16-bit CRC generator for
safeguarding data transfersBuilt-in multidrop controller ensurescompatibility with other MicroLAN productsDirectly connects to a single port pin of a
microprocessor and communicates at up to
16.3kbits per secondOverdrive mode boosts communication speedto 142kbits per second8-bit family code specifies device
communication requirements to readerPresence detector acknowledges when readerfirst applies voltageCompact, low cost 6-pin TSOC surface mount
packageReads, writes and counts over a wide voltage
range of 2.8V to 5.5V from -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONPin 1Ground
Pin 2Data
Pin 3Vbat
Pin 4NCPin 5Input channel B
Pin 6Input channel A
ORDERING INFORMATIONDS2423P6-pin TSOC package
DS2423P/T&RTape & Reel Version ofDS2423P
DS2423XChip Scale Pkg., Tape &
Reel
DESCRIPTIONThe DS2423 1-Wire® RAM with Counters is a fully static, read/write memory for battery operation in a
low-cost, six-lead TSOC, surface-mount package. The memory is organized as 16 pages of 256 bits each.
In addition, the device has four counters, two of them with external trigger inputs called A and B. Each ofthe counters is associated with a memory page. A counter without external trigger input increments each
time data is written to the page it is associated with (write cycle counter). The counters triggered by
DS2423
4kbit 1-Wire
RAM with CounterTOP VIEW
3.7mm x 4.0mm x 1.5mm
TSOC PACKAGE
DS2423
The battery-backed memory offers a simple solution to storing and retrieving information pertaining to
the equipment where the DS2423 is installed and its frequency of use. The scratchpad is an additional
page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it may be
read back for verification. A copy scratchpad command will then transfer the data to memory. Thisprocess ensures data integrity when modifying the memory. A 64-bit registration number is factory
lasered into each DS2423 to provide a guaranteed unique identity which allows for absolute traceability
and acts as node address if multiple DS2423 are connected in parallel to form a local network. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.
The DS2423 1-Wire RAM with Counters can store encrypted data. The unique registration number and
the page write cycle counter(s) prevent unauthorized manipulation of data stored in a page with a write
cycle counter associated.
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2423. The DS2423 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,3) 4096-bit SRAM, and 4) four 32-bit read-only counters. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. Each of these counters is associated with one of the 256-bit memory pages.
The four counters of the DS2423 are associated with pages 12 to 15. The contents of the counter is read
together with the memory data using a special command. The bus master must first provide one of the
six ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5)Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command
byte executed at standard speed, the device will enter Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is
described in Figure 9. After a ROM function command is successfully executed, the memory functions
become accessible and the master may provide any one of the five memory function commands. Theprotocol for these memory function commands is described in Figure 7. All data is read and written least
significant bit first.
PARASITE POWERThe block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever
the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltagerequirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
lithium is conserved, and 2) if the battery is exhausted for any reason, the ROM may still be read
normally.
64-BIT LASERED ROMEach DS2423 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3).
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-
Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton® Standards.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number
is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the 8 bits of CRC should return the shift register to all 0s.
DS2423
BLOCK DIAGRAM Figure 1
ADDRESS REGISTERS AND TRANSFER STATUSBecause of the serial data transfer, the DS2423 employs three address registers called TA1, TA2, and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will bewritten or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,
the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of
the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S
register, called PF or “partial byte flag,” is set if the number of data bits sent by the master is not aninteger multiple of 8. Bit 6 has no function; it always reads 0. Note that the lowest 5 bits of the target
address also determine the address within the scratchpad, where intermediate storage of data will begin.
This address is called byte offset. If the target address (TA1) for a Write command is 03CH for example,
then the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only 4
bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency,the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0.
Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH.
However, it is possible to write one or several contiguous bytes somewhere within a page. The ending
offset together with the Partial Flag support the master checking the data integrity after a Write command.
The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag to indicatethat the data stored in the scratchpad has already been copied to the target memory address. Writing data
to the scratchpad clears this flag.
DS2423
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3MSBLSB
MSBLSBMSBLSBMSBLSB
1-WIRE CRC GENERATOR Figure 4
DS2423
WRITING WITH VERIFICATIONTo write data to the DS2423, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address and data at the end of the Write Scratchpad command
sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself todecide if the communication was successful and proceed to the Copy Scratchpad command. If the master
could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to
verify data integrity. As preamble to the scratchpad data, the DS2423 repeats the target address TA1 and
TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad. The master does not need to continue reading; it can start a new trial to write data to thescratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the device.
If everything went correctly, both flags are cleared and the ending offset indicates the address of the last
byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain thecontents of these registers by reading the scratchpad or derive it from the target address and the amount of
data to be written. As soon as the DS2423 has received these bytes correctly, it will copy the data to the
requested location beginning at the target address.
MEMORY FUNCTION COMMANDSThe Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory.An example follows the flowchart. The communication between master and DS2423 takes place either at
regular speed (default, OD = 0) or at Overdrive speed (OD = 1). If not explicitly set into the Overdrive
mode the DS2423 assumes regular speed.
Write Scratchpad Command [0FH]After issuing the Write Scratchpad command, the master must first provide the 2-byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting atthe byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the master stops
writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be
ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command the CRC generator inside the DS2423 (see Figure 12)
calculates a CRC over the entire data stream, starting at the command code and ending at the last data
byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC
generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target
Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the WriteScratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read
time slots and will receive the CRC generated by the DS2423.
The memory address range of the DS2423 is 0000H to 01FFH. If the bus master sends a target address
higher than this, the internal circuitry of the chip will set seven most significant address bits to 0 as theyare shifted into the internal address register. The Read Scratchpad command will reveal the target address
as it will be used by the DS2423. The master will identify such address modifications by comparing the
target address read back to the target address transmitted. If the master does not read the scratchpad, a
subsequent Copy Scratchpad command will not work since the most significant bits of the target address
DS2423
Read Scratchpad Command [AAH]This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad
command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the
ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0).
The master may read data until the end of the scratchpad after which the data read will be all logic 1s.
Copy Scratchpad [5AH]This command is used to copy data from the scratchpad to memory. After issuing the Copy Scratchpadcommand, the master must provide a 3-byte authorization pattern which can be obtained by reading the
scratchpad for verification. This pattern must exactly match the data contained in the three address
registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag
will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has
been copied until a Reset Pulse is issued by the master. Any attempt to reset the part will be ignored whilethe copy is in progress. Copy typically takes 30µs. The data to be copied is determined by the three
address registers. The scratchpad data from the beginning offset through the ending offset will be copied
to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with
this command. The AA flag will be cleared only by executing a Write Scratchpad command.
DS2423
DS2423 MEMORY MAP Figure 5
ADDRESS REGISTERS Figure 6
DS2423
Read Memory [F0H]The read memory command may be used to read the entire memory. After issuing the command, the
master must provide the 2-byte target address. After the two bytes, the master reads data beginning from
the target address and may continue until the end of memory, at which point logic 1s will be read. It is
important to realize that the target address registers will contain the address provided. The ending
offset/data status byte is unaffected.
The hardware of the DS2423 provides a means to accomplish error-free writing to the memory section.To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets of the size of one memory page each. Such a packet
would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that
eliminate having to read a page multiple times to determine if the received data is correct or not. (See the
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure.)
Read Memory + Counter [A5H]The Read Memory + Counter command is used to read memory data together with the write cycle counteror externally triggered counter associated with the addressed page of data memory. The additional
information is transmitted by the DS2423 as the end of a memory page is encountered. Following the
current value of the counter the DS2423 transmits 32 0-bits and a 16-bit CRC generated by the DS2423.
After having sent the command code of the Read Memory + Counter command, the bus master sends a
two-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data
field. With the subsequent read data time slots the master receives data from the DS2423 starting at theinitial address and continuing until the end of a 32-byte page is reached. At that point the bus master will
send 80 additional read data time slots and receive the contents of the 32-bit counter associated with the
addressed page, 32 0-bits and a 16-bit CRC. With subsequent read data time slots the master will receive
data starting at the beginning of the next page followed by the contents of the counter associated with the
page, 0-bits and CRC for that page. This sequence will continue until the final page and its accompanyingdata is read by the bus master. When applying the Read Memory + Counter command to a page that does
not have a counter associated, the master will read FFFFFFFFH instead of a valid count.
With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC generator, followed by the two address bytes, the
contents of the data memory, the counter and the 0-bits. Subsequent passes through the Read Memory +
Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and thenshifting in the contents of the data memory page, its associated counter and 0-bits. After the 16-bit CRC
of the last page is read, the bus master will receive logical 1s from the DS2423 until a Reset Pulse is
issued. The Read Memory + Counter command sequence can be ended at any point by issuing a Reset
Pulse.
DS2423
MEMORY FUNCTION FLOW CHART Figure 7nd Part
From Figure 7nd Part
DS2423
MEMORY FUNCTION FLOW CHART Figure 7 cont’dFrom Figure 7st Part
To Figure 7st Part
From Figure 7rd Part
DS2423
MEMORY FUNCTION FLOW CHART Figure 7 cont’dFrom Figure 7nd Part
To Figure 7nd Part
DS2423
MEMORY FUNCTION EXAMPLEExample: Write two data bytes to memory location 0026 and 0027. Read entire memory.
DS2423
MEMORY FUNCTION EXAMPLERead page 14 and counts of Input A. Rewrite page 14 with 32 bytes. Read Memory + Counter, WriteScratchpad, Copy Scratchpad.
