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DS2413DG-100-3C0+T-DS2413P+
1-Wire Dual Channel Addressable Switch
GENERAL DESCRIPTION The DS2413 is a dual-channel programmable I/O
1-Wire® chip. The PIO outputs are configured as
open-drain and provide up to 20mA continuous sink
capability and off-state operating voltage up to 28V.
Control and sensing of the PIO pins is performed with dedicated device-level command protocol. To
provide a high level of fault tolerance in the end
application, the 1-Wire IO and PIO pins are all
capable of withstanding continuous application of
voltages up to 28V max. Communication and
operation of the DS2413 is performed with the single
contact Maxim/Dallas 1-Wire serial interface.
APPLICATIONS LED Control Accessory Identification and Control General Purpose Input/Output Key-Pick Systems Industrial Controllers System Monitoring
TYPICAL OPERATING CIRCUIT PX.Y
RPUP
VCC
Local
PowerLED
Switch
PIOA
PIOB
GND
DS2413
PIN CONFIGURATION
2413 ymrrF4
DS 2413 ywwrr
TSOC TDFN Top View with Marking. TDFN Contacts
Not Visible in this View.
Exposed Paddle
BENEFITS AND FEATURES • Controls Dual Programmable High Voltage, High
Current I/O Port Pins from a Single Micro Port Pin Open-Drain Programmable I/O Pins Support
20mA max Continuous Current Sink 28V (max) PIO Pin Operating Voltage On-Resistance of PIO Pulldown Transistor 20Ω max; OFF Resistance 1MΩ min Parasitic Power Supply Through 1-Wire • Minimalist 1-Wire Interface Lowers Cost and
Interface Complexity Communicates to Host with a Single Digital
Signal at 14.9kb or 100kbps Switchpoint Hysteresis and Filtering to
Optimize Performance in the Presence of
Noise 1-Wire IO Pin Supports 28V Absolute
Maximum DC Level for Fault Conditions Unique 64-bit ROM Serial Number Factory
Lasered Into Each Device High ESD Immunity of 1-Wire IO Pin: 8kV
HBM Typical TSOC and TDFN Packages Available • Wide Voltage and Temperature Operating Ranges
Enables Robust System Performance 2.8V to 5.25V 0°C to +70°C
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2413P+ 0°C to +70°C TSOC
DS2413P+T&R 0°C to +70°C TSOC
DS2413Q+T&R 0°C to +70°C TDFN
+ Denotes a lead(Pb)-free package/RoHS-compliant
package.
T&R = Tape and reel.
Commands, Registers, and Modes are capitalized for
clarity.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-5316; 3/15
DS2413
1-Wire Dual Channel
Addressable Switch
DS2413: 1-Wire Dual Channel Addressable Switch
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin to GND -0.5V, +30V
Maximum Current into IO Pin ±25mA
Maximum Current into PIO Pin ±30mA
Maximum Current Through GND Pins (Both Pins Tied Together) ±60mA
Operating Temperature Range 0°C to +70°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
+300°C
+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS TA = 0°C to +70°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN GENERAL DATA 1-Wire Pullup Voltage
(Note 1) VPUP
Standard speed 2.8 5.25 Overdrive speed 2.9 5.25
DC only; no 1-Wire communication 28
1-Wire Pullup Resistance RPUP (Notes 1, 2) 1.5 2.2 kΩ
Input Load Current IL
VPUP ≤ 5.25V 3.5 70
μA VPUP ≤ 3.30V 3.5 15
V(IO) = 28V (Note 3) 400 950
Input Capacitance CIO At 25°C (Notes 4, 5) 800 pF
Input Low Voltage VIL (Notes 1, 6) 0.4 V
High-to-Low Switching
Threshold VTL (Notes 5, 7, 8) 0.4 3.2 V
Low-to-High Switching
Threshold VTH (Notes 5, 7, 9) 0.7 3.6 V
Switching Hysteresis VHY (Notes 5, 10) 0.2 V
Output Low Voltage VOL At 4mA Current Load (Note 11) 0.4 V
Recovery Time
(Notes 1, 12) tREC
Standard speed, RPUP = 2.2kΩ 5
μs Overdrive speed, RPUP = 2.2kΩ 2
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2kΩ 5
Rising-Edge Hold-off Time
(Notes 5, 13) tREH Standard speed 0.5 5.0 μs Overdrive speed Not applicable (0)
Time slot Duration
(Note 1, 5) tSLOT
Standard speed, VPUP ≥ 4.5V 65
μs
Standard speed (Note 14) 67
Overdrive speed, VPUP ≥ 4.5V
(Note 14) 9
Overdrive speed (Note 14) 10
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time (Note 1) tRSTL
Standard speed, VPUP ≥ 4.5V 480 960
μs Standard speed (Note 14) 600 960
Overdrive speed, VPUP ≥ 4.5V 48 80
Overdrive speed (Note 14) 63 80
Presence Detect High
Time (Notes 14, 15) tPDH
Standard speed, VPUP ≥ 4.5V 15 66
μs Standard speed 15 68
Overdrive speed, VPUP ≥ 4.5V 2 7.0
Overdrive speed 2 8.2
Presence Detect Fall Time
(Notes 5, 16) tFPD
Standard speed, VPUP > 4.5V 0.24 1.4
μs Standard speed 0.24 1.6
Overdrive speed, VPUP ≥ 4.5V 0 0.7
Overdrive speed 0 0.9
Presence Detect Low
Standard speed, VPUP > 4.5V 60 240
Standard speed (Note 14) 60 260
DS2413: 1-Wire Dual Channel Addressable Switch
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Presence Detect Sample
Time (Notes 1, 20) tMSP
Standard speed, VPUP > 4.5V 67.4 75
μs Standard speed 69.6 75
Overdrive speed, VPUP ≥ 4.5V 7.7 10
Overdrive speed 9.1 10
IO PIN, 1-Wire WRITE Write-0 Low Time
(Notes 1, 17) tW0L
Standard speed, VPUP > 4.5V 60 120
μs
Standard speed (Note 14) 62 120
Overdrive speed, VPUP ≥ 4.5V
(Note 14) 16
Overdrive speed (Note 14) 8 16
Write-1 Low Time
(Notes 1, 17) tW1L Standard speed 5 15 μs Overdrive speed 1 2
IO PIN, 1-Wire READ Read Low Time
(Notes 1, 18) tRL Standard speed 5 15 - δ μs Overdrive speed 1 2 - δ
Read Sample Time
(Notes 1, 18) tMSR Standard speed tRL + δ 15 μs Overdrive speed tRL + δ 2
PIO Pins Leakage Current ILP Pin at 28V (Note 19) 8.5 24 μA
Input Capacitance CP (Note 5) 100 pF
Output low voltage VOLP 20mA load current 0.4 V
Input Low Voltage VILP (Note 1) 0.8 V
Input High Voltage
(Note 21) VIHP (Note 1) VPUP –
0.3V 28 V
Note 1: System requirement.
Note 2: Full RPUP range guaranteed by design and simulation. not production tested. Production testing performed at a fixed RPUP value.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00 or DS2480B may be required. The DS2482-x00 may not
always detect the DS2413 presence pulse. For proper operation it may be necessary to disregard (force to 1) the PPD bit in the
DS2482-x00 status register.
Note 3: The I-V characteristic is linear for voltages greater than 10V.
Note 4: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5μs
after VPUP has been applied the parasite capacitance will not affect normal communications.
Note 5: Guaranteed by design and simulation. Not production tested.
Note 6: The voltage on IO needs to be less than or equal to VILMAX whenever the master drives the line low.
Note 7: VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire Recovery Times. The VTH and
VTL maximum specifications are valid at VPUPmax (5.25V). In any case, VTL < VTH < VPUP.
Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single DS2413 attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 14: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Note 15: tPDH is deemed to have ended when the voltage on IO drops below 80% of VPUP on the leading edge of the presence-detect low
pulse. tPDL is deemed to have begun when the voltage on IO drops below 20% of VPUP on the leading edge of the pulse.
Note 16: Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 17: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum
duration for the master to pull the line low is tW1Lmax + tF - ε and tW0Lmax + tF - ε respectively.
Note 18: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF.
Note 19: The I-V characteristic is linear for voltages greater than 7V.
Note 20: tMSP is a system required sample point and not directly production tested. Production testing is performed on related parameters
tPDH and tPDL. Parameter tFPD is guaranteed by design and simulation, not production tested.
Note 21: Production tested for VIHP(min). VIHP(max) is guaranteed by design and simulation, not production tested.
DS2413: 1-Wire Dual Channel Addressable Switch
LEGACY VALUES DS2413 VALUES
PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61μs (undef.) 7μs (undef.) 67μs (undef.) 10μs (undef.)
tRSTL 480μs (undef.) 48μs 80μs 600μs 960μs 63μs 80μs
tPDH 15μs 60μs 2μs 6μs 15μs 68μs 2μs 8.2μs
tPDL 60μs 240μs 8μs 24μs 60μs 260μs 8μs 32μs
tW0L 60μs 120μs 6μs 16μs 62μs 120μs 8μs 16μs
PIN DESCRIPTION
NAME TSOC PIN # TDFN PIN # FUNCTION IO 2 2 1-Wire bus interface. Open-drain, requires external pullup resistor.
PIOA 6 4 Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOA = 1).
PIOB 4 6 Programmable I/O pin, open-drain with weak pulldown, power-on
default is off (PIOB = 1).
GND1 1 3 Ground reference 1
GND2 5 5 Ground reference 2; both GND pins must be connected in the
application.
NC 3 1 Not connected
GND — EP
Exposed Paddle (TDFN only). Solder evenly to the board’s ground
plane for proper operation. See Application Note 3273 for additional
information.
DESCRIPTION The DS2413 combines two PIO pins and a fully featured 1-Wire interface in a single chip. PIO outputs are open-
drain, operate at up to 28V and provide an on resistance of 20Ω max. A robust communication protocol ensures
that PIO output changes occur error-free. Each DS2413 has a Registration Number that is 64 bits long. The
Registration Number guarantees unique identification and is used to address the device in a multidrop 1-Wire
network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each
other. Device power is supplied parasitically from the 1-Wire bus. The DS2413’s applications of include accessory
identification and control, system monitoring, and general-purpose input/output.
OVERVIEW The block diagram in Figure 1 shows the relationships between the major sections of the DS2413. The DS2413
has two main components: 64-bit Registration Number, and PIO Control. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)
Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-
Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters
Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these
ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the
PIO functions become accessible and the master may provide one of the two PIO Function commands. The
protocol for these commands is described in Figure 6. All data is read and written least significant bit first.
Figure 1. Block Diagram 1-Wire
Interface
PIO
Control
64-Bit Registration
Number
PIOA
Internal VDDPIOB
DS2413: 1-Wire Dual Channel Addressable Switch
64-BIT LASERED ROM Each DS2413 has a unique ROM Registration Number that is 64 bits long, as shown in Figure 3. The first eight bits
are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC (Cyclic
Redundancy Check) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator consisting of a
shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about
the Dallas 1-Wire CRC is available in Application Note 27. The shift register bits are initialized to zero. Then
starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been
entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.
Figure 2. Hierarchical Structure for 1-Wire Protocol
DS2413 Command
Level:
1-Wire ROM Function
Commands (see Figure 10)
DS2413-specific
PIO Function Commands
(see Figure 6)
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
PIO Access Read
PIO Access Write
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag,
OD-Flag
PIO Pins
PIO Pins
Command
Codes:
33h
55h
F0h
CCh
A5h
3Ch
69h
F5h
5Ah
Figure 3. 64-Bit LASERED ROM MSB LSB
8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (3Ah)
MSB LSB MSB LSB MSB LSB
Figure 4. 1-Wire CRC Generator 0X1X2X3X4X5X6X7X8
Polynomial = X8 + X5 + X4 + 1st
STAGEnd
STAGErd
STAGEth
STAGEth
STAGEth
STAGEth
STAGEth
STAGE
INPUT DATA
DS2413: 1-Wire Dual Channel Addressable Switch
PIO STUCTURE Each PIO consists of an open-drain pulldown transistor with 28V capability. The transistor is controlled by the PIO
Output Latch, as shown in Figure 5. The PIO Control unit connects the PIOs to the 1-Wire interface.
Figure 5. PIO Simplified Logic Diagram PIO Pin
StatePIO Pin
PIO Out-
put Latch
PIO Output
Latch State.D
PIO Data
PIO Clock
CLOCK
PIO FUNCTION COMMANDS The PIO Function Flow Chart (Figure 6) describes the protocols necessary to access the PIO pins of the DS2413.
Examples on how to use these functions are included at the end of this document. The communication between
master and DS2413 takes place either at standard speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not
explicitly set into the Overdrive Mode, the DS2413 powers up in standard speed.
PIO ACCESS READ [F5h] This command reads the PIO logical status and reports it together with the state of the PIO Output Latch in an
endless loop. A PIO Access Read can be terminated at any time with a 1-Wire Reset.
PIO Status Bit Assignment b7 b6 b5 b4 b3 b2 b1 b0
Complement of b3 to b0 PIOB Output
Latch State
PIOB Pin
State
PIOA Output
Latch State
PIOA Pin
State
The state of both PIO channels is sampled at the same time. The first sampling occurs during the last (most
significant) bit of the command code F5h. The PIO status is then reported to the bus master. While the master
receives the last (most significant) bit of the PIO status byte, the next sampling occurs and so on until the master
generates a 1-Wire Reset. The sampling occurs with a delay of tREH+x from the rising edge of the MS bit of the
previous byte, as shown in Figure 7. The value of "x" is approximately 0.2μs.
Figure 7. PIO Access Read Timing Diagram MS 2 bits of
previous byte
LS 2 bits of PIO
Status byte
VTH
Sampling Point
tREH+x
Notes: The "previous byte" could be the command code or the data byte resulting from the previous PIO sample. The sample point timing also applies to the PIO Access Write command, with the "previous byte" being the
DS2413: 1-Wire Dual Channel Addressable Switch
Figure 6. PIO Function Flow Chart DS2413: 1-Wire Dual Channel Addressable Switch
PIO ACCESS WRITE [5Ah] The PIO Access Write command writes to the PIO output latches, which control the pulldown transistors of the PIO
channels. In an endless loop this command first writes new data to the PIO and then reads back the PIO status.
This implicit read-after-write can be used by the master for status verification. A PIO Access Write can be
terminated at any time with a 1-Wire Reset.
PIO Output Data Bit Assignment b7 b6 b5 b4 b3 b2 b1 b0 X X X X X PIOB PIOA
After the command code the master transmits a PIO Output Data byte that determines the new state of the PIO
output transistors. The first (least significant) bit is associated to PIOA; the next bit affects PIOB. The other 6 bits of
the new state byte do not have corresponding PIO pins. These bits should always be transmitted as "1"s. To switch
the output transistor on, the corresponding bit value is 0. To switch the output transistor off (non-conducting) the bit
must be 1. This way the bit transmitted as the new PIO output state arrives in its true form at the PIO pin. To
protect the transmission against data errors, the master must repeat the PIO Output Data byte in its inverted form.
Only if the transmission was error-free will the PIO status change. The actual PIO transition to the new state occurs
with a delay of tREH+x from the rising edge of the MS bit of the inverted PIO byte, as shown in Figure 8. The value
of "x" is approximately 0.2μs. To inform the master about the successful communication of the PIO byte, the
DS2413 transmits a confirmation byte with the data pattern AAh. While the MS bit of the confirmation byte is
transmitted, the DS2413 samples the state of the PIO pins, as shown in Figure 7, and sends it to the master. The
master can either continue writing more data to the PIO or issue a 1-Wire Reset to end the command.
Figure 8. PIO Access Write Timing Diagram PIO
MS 2 bits of inverted
PIO Output Data byte
LS 2 bits of confir-
mation byte (AAh)
VTH
tREH+x
1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2413 is a
slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into
three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The
1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on
the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state
outputs. The 1-Wire port of the DS2413 is open drain with an internal circuit equivalent to that shown in Figure 9.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS2413 supports both a Standard and
Overdrive communication speed of 14.9kbps (max) and 100kbps (max), respectively. Note that legacy 1-Wire
products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The value of the pullup
resistor primarily depends on the network size and load conditions. The DS2413 requires a pullup resistor of 2.2kΩ
(max) at any speed.
DS2413: 1-Wire Dual Channel Addressable Switch
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16μs
(Overdrive speed) or more than 120μs (standard speed), one or more devices on the bus may be reset.
Figure 9. Hardware Configuration Open Drain
Port Pin
RX = RECEIVE
TX = TRANSMIT100 Ω
MOSFET
VPUPDATA
RPUP
BUS MASTERDS2413 1-Wire PORT
TRANSACTION SEQUENCE The protocol for accessing the DS2413 through the 1-Wire port is as follows: Initialization ROM Function Command PIO Function Command Data
INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS2413 is on the bus and is ready to operate. For more details, see the 1-
Wire Signaling section.
1-Wire ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the
DS2413 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to the flow
chart in Figure 10).
READ ROM [33h] This command allows the bus master to read the DS2413’s 8-bit family code, unique 48-bit serial number, and 8-bit
CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the
bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND
result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.
MATCH ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific
DS2413 on a multidrop bus. Only the DS2413 that exactly matches the 64-bit ROM sequence, including the
external address, responds to the following PIO Function command. All other slaves wait for a reset pulse. This
command can be used with a single or multiple devices on the bus.
