DS2411 ,Silicon Serial Number with VFEATURES PIN CONFIGURATION Unique, Factory-Lasered and Tested 64-Bit 3 Registration Number (8-B ..
DS2411 ,Silicon Serial Number with VPIN DESCRIPTION *The DS2411X is RoHS qualified and comes in tape and reel. PIN NAME FLIP SOT23 ..
DS2411P ,Silicon Serial Number with VCC InputPIN DESCRIPTIONPART TEMP RANGE PACKAGEPINDS2411R/ SOT23-3,NAME FLIP-40C to +85CSOT23 TSOCT&R Tape ..
DS2411P+ ,Silicon Serial Number with VCC InputFEATURES PIN CONFIGURATION Unique, Factory-Lasered and Tested 64-Bit 3 Registration Number (8-B ..
DS2411R+T&R ,Silicon Serial Number with VCC InputPIN DESCRIPTION *The DS2411X is RoHS qualified and comes in tape and reel. PIN NAME FLIP SOT23 ..
DS2411R+U ,Silicon Serial Number with VCC Input19-6131; Rev 11/11 DS2411 Silicon Serial Number with V InputCC
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2411
Silicon Serial Number with V
FEATURES Unique, Factory-Lasered and Tested 64-Bit
Registration Number (8-Bit Family Code
Plus 48-Bit Serial Number Plus 8-Bit CRC
Tester); Guaranteed No Two Parts Alike Standby Current <1μA Built-In Multidrop Controller Enables
Multiple DS2411s to Reside on a Common
1-Wire Network Multidrop Compatible with Other 1-Wire
Products 8-Bit Family Code Identifies Device as
DS2411 to the 1-Wire Master Low-Cost TSOC, SOT23-3, and Flip-Chip
Surface-Mount Packages Directly Connects to a Single-Port Pin of a
Microprocessor and Communicates at up to
15.4kbps Overdrive Mode Boosts Communication
Speed to 125kbps Operating Range: 1.5V to 5.25V, -40°C to
+85°C
PIN DESCRIPTION
NAME PIN
SOT23 TSOC FLIP
CHIP I/O 1 2 A1
VCC 2 6 B2
GND 3 1 B1
N.C. — 3, 4, 5 A2
PIN CONFIGURATION 2
SOT23-3, Top View
TSOC, Top View Flip Chip, Top View with
Laser Mark, Contacts
Not Visible.
“rrd” = Revision/Date
-1rrd B
ORDERING INFORMATION
PART TEMP
RANGE
PIN-
PACKAGE DS2411R+T&R -40°C to +85°C 3 SOT23-3
DS2411P+ -40°C to +85°C 6 TSOC
DS2411P+T&R -40°C to +85°C 6 TSOC
DS2411X -40°C to +85°C 4 Flip Chip*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*The DS2411X is RoHS qualified and comes in tape and reel.
DESCRIPTION The DS2411 silicon serial number is a low-cost, electronic registration number with external power
supply. It provides an absolutely unique identity that can be determined with a minimal electronic
interface (typically, a single port pin of a microcontroller). The DS2411’s registration number is a
factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit
family code (01h). Data is transferred serially through the Maxim 1-Wire protocol. The external power
supply is required, extending the operating voltage range of the device below typical 1-Wire devices.
DS2411
Silicon Serial Number with VCC Input 19-6131; Rev 11/11
DS2411
ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.5V to +6V
VCC Voltage to GND -0.5V to +6V
I/O, VCC Current ±20mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (TSOC, SOT23-3 only; soldering, 10s) +300°C
Soldering Temperature (reflow)
TSOC, SOT-23-3
Flip Chip
+260°C
+240°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
ELECTRICAL CHARACTERISTICS (VCC = 1.5V to 5.25V; TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Operating Temperature TA (Note 1) -40 +85 °C
Supply Voltage VCC (Note 1) 1.5 5.25 V
1-Wire Pullup VCC = VPUP (Note 1) 1.5 5.25 V
I/O PIN GENERAL DATA 1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.3 2.2 kΩ
Power-Up Delay tPWRP VCC stable to first
1-Wire command (Notes 1, 3) 1200 µs
Input Capacitance CIO (Note 3) 100 pF
Input Load Current IL 0V ≤ V(I/O) ≤ VCC -1 +1 µA
Standby Supply Current ICCS V(I/O) ≤ VIL, or V(I/O) ≥ VIH 1 µA
Active Supply Current ICCA 100 µA
High-to-Low Switching
Threshold VTL (Notes 3, 4, 5) 0.4 3.2 V
Input Low Voltage VIL (Note 1) 0.30 V
Input High Voltage VIH (Note 1) VCC -
0.3 V
Low-to-High Switching
Threshold VTH (Notes 3, 4, 6) 0.75 3.4 V
Switching Hysteresis VHY (Notes 3, 7) 0.18 V
Output Low Voltage at 4mA VOL (Note 8) 0.4 V
Rising Edge Holdoff tREH Standard speed (Note 9, 3) 1.25 5 µs Overdrive speed (Note 9, 3) 0.5 2
Recovery Time tREC
Standard speed,
RPUP = 2.2kΩ (Note 1) 5
µs Overdrive speed,
RPUP = 2.2kΩ (Note 1) 2
Overdrive speed, directly prior to
reset pulse; RPUP = 2.2kΩ (Note 1) 5
DS2411
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Timeslot Duration tSLOT
Standard speed 65
µs Overdrive VCC ≥ 2.2V 8
Overdrive VCC ≥ 1.5V 10
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time
tRSTL
Standard speed 480 640 µs Overdrive speed 60 80
Presence-Detect High Time tPDH
Standard speed 15 60
µs Overdrive VCC ≥ 2.2V 2 6
Overdrive VCC ≥ 1.5V 2 8.5
Presence-Detect Low Time tPDL
Standard speed 60 240
µs Overdrive VCC ≥ 2.2V 8 24
Overdrive VCC ≥ 1.5V 8 30
Presence-Detect Fall Time tFPD Standard speed (Note 10, 3) 0.4 8 µs Overdrive speed (Note 10, 3) 0.05 1
Presence-Detect Sample
Time tMSP
Standard speed (Note 1) 60 75
µs Overdrive VCC ≥ 2.2V (Note 1) 6 10
Overdrive VCC ≥ 1.5V (Note 1) 8.5 10
I/O PIN, 1-Wire WRITE Write-0 Low Time tW0L
Standard speed (Notes 1, 11, 13) 60 120
µs
Overdrive VCC ≥ 2.2V
(Notes 1, 11, 13) 6 16
Overdrive VCC ≥ 1.5V
(Notes 1, 11, 13) 8 16
Write-1 Low Time tW1L Standard speed (Notes 1, 11, 13) 5 15 µs Overdrive speed (Notes 1, 11, 13) 1 2
I/O PIN, 1-Wire READ Read Low Time tRL Standard speed (Notes 1, 12) 5 15 - δ µs Overdrive speed (Notes 1, 12) 1 2 - δ
Read Sample Time tMSR Standard speed (Notes 1, 12) tRL + δ 15 µs Overdrive speed (Notes 1, 12) tRL + δ 2
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at VPUP = 5.25V assuming
VOL = 0V.
Note 3: Not production tested.
Note 4: VTL and VTH are functions of VCC and temperature. The VTH and VTL maximum specifica-
tions are valid at VCC = 5.25V. In any case, VTL < VTH < VCC.
Note 5: Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Note 6: Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
Note 7: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to
be detected as logic ‘0’.
DS2411
Note 9: The earliest recognition of a negative edge is possible at tREH after VTH has been reached
on the previous edge.
Note 10: Interval during the negative edge on I/O at the beginning of a presence-detect pulse
between the time at which the voltage is 90% of VPUP and the time at which the voltage is
10% of VPUP.
Note 11: ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on I/O
up VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX
+ tF - ε and tW0LMAX + tF - ε, respectively.
Note 12: δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on I/O
up from VIL to the input-high threshold of the bus master. The actual maximum duration
for the master to pull the line low is tRLMAX + tF.
Note 13: Interval begins when the voltage drops below VTL during a negative edge on I/O and ends
when the voltage rises above VTH during a positive edge on I/O.
OPERATION The DS2411’s registration number is accessed through a single data line. The 48-bit serial number, 8-bit
family code, and 8-bit CRC are retrieved using the Maxim 1-Wire protocol. This protocol defines bus
transactions in terms of the bus state during specified time slots that are bus-master-generated falling
edges on the I/O pin. All data is read and written least significant bit first. The device requires a delay
between VCC power-up and initial 1-Wire communication, tPWRP (1200µs). During this time the device
may issue presence-detect pulses.
1-Wire BUS SYSTEM The 1-Wire bus has a single bus master and one or more slaves. In all instances, the DS2411 is a slave
device. The bus master is typically a microcontroller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and
timing).
Hardware Configuration The 1-Wire bus has a single data line, I/O. It is important that each device on the bus be able to drive I/O
at the appropriate time. To facilitate this, each device has an open-drain or three-state output. The
DS2411 has an open-drain output with an internal circuit equivalent to that shown in Figure 3. The bus
master can have the same equivalent circuit. If a bidirectional pin is not available on the master, separate
output and input pins can be connected together. The bus requires a pullup resistor at the master end of
the bus, as shown in Figure 4. A multidrop bus consists of a 1-Wire bus with multiple slaves attached.
The 1-Wire bus has a maximum data rate of 15.4kbps in standard speed and 125kbps in overdrive.
The idle state for the 1-Wire bus is high. If a transaction needs to be suspended for any reason, I/O must
remain high if the transaction is to be resumed. If the bus is pulled low, slave devices on the bus will
interpret the low as either a timeslot, or a reset depending on the duration.
Figure 1. DS2411 REGISTRATION NUMBER MSB LSB
8-BIT CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE
(01h)
MSB LSB MSB LSB MSB LSB
DS2411
Figure 2. 1-WIRE CRC GENERATOR 0X1X2X3X4X5X6X7X8
POLYNOMIAL = X8 + X5 + X4 + 1
1st
STAGE
2nd
STAGE
3rd
STAGE
4th
STAGE
6th
STAGE
5th
STAGE
7th
STAGE
8th
STAGE
INPUT DATA
Figure 3. DS2411 EQUIVALENT CIRCUIT 100Ω
MOSFET
Rx
Tx
VCC
I/O
-1µA ≤ IL ≤ 1µA
GROUND
Figure 4. BUS MASTER CIRCUIT OPEN-DRAIN
PORT PIN
BUS MASTER
DS5000 OR 8051
EQUIVALENT
VCC to DS2411
Rx
Tx
RPUP
I/O to DS2411
Ground to DS2411
RPUP must be between 0.3 kΩ and 2.2 kΩ. The optimal
value depends on the 1-Wire communication speed and
the bus load characteristics.
DS2411
TRANSACTION SEQUENCE The communication sequence for accessing the DS2411 through the 1-Wire bus is as follows: Initialization ROM Function Command Read Data
INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2411 is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the three ROM function commands. All
ROM function command codes are 1 byte long. A list of these commands follows (see the flowchart in
Figure 5).
Read ROM [33h] This command allows the bus master to read the DS2411’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single slave device on the bus. If
more than one slave is present on the bus, a data collision results when all slaves try to transmit at the
same time (open drain produces a wired-AND result), and the resulting registration number read by the
master will be invalid.
Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the
1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the
master can use a process of elimination to identify the registration numbers of all slave devices. For each
bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time
slots. On the first slot, each slave device participating in the search outputs the true value of its
registration number bit. On the second slot, each slave device participating in the search outputs the
complemented value of its registration number bit. On the third slot, the master writes the true value of
the bit to be selected. All slave devices that do not match the bit written by the master stop participating
in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of
the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete
pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
Overdrive Skip ROM [3Ch] This command causes all overdrive-capable slave devices on the 1-Wire network to enter overdrive speed
(OD = 1). All communication following this command has to occur at overdrive speed until a reset pulse
of minimum 480µs duration resets all devices on the bus to regular speed (OD = 0).
To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be
issued followed by a read ROM or search ROM command sequence. Overdrive speeds up the time for the
search process.
