DS2408S+ ,1-Wire 8-Channel Addressable SwitchFEATURES PIN CONFIGURATION Control Eight Independent I/O Port Pins from a Single Micro Port Pin o ..
DS2409P+ ,MicroLAN CouplerPIN DESCRIPTIONcontrol outputPin 1 GND Communicates at 16.3kbits per secondPin 2 1-Wire in Unique ..
DS2411 ,Silicon Serial Number with VFEATURES PIN CONFIGURATION Unique, Factory-Lasered and Tested 64-Bit 3 Registration Number (8-B ..
DS2411 ,Silicon Serial Number with VPIN DESCRIPTION *The DS2411X is RoHS qualified and comes in tape and reel. PIN NAME FLIP SOT23 ..
DS2411P ,Silicon Serial Number with VCC InputPIN DESCRIPTIONPART TEMP RANGE PACKAGEPINDS2411R/ SOT23-3,NAME FLIP-40C to +85CSOT23 TSOCT&R Tape ..
DS2411P+ ,Silicon Serial Number with VCC InputFEATURES PIN CONFIGURATION Unique, Factory-Lasered and Tested 64-Bit 3 Registration Number (8-B ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2408S+
1-Wire 8-Channel Addressable Switch
DS2408
1-Wire 8-Channel Addressable Switch
BENEFITS AND FEATURES Control Eight Independent I/O Port Pins from a Single
Micro Port Pin Eight Channels of Programmable I/O with
Open-Drain Outputs On-Resistance of PIO Pulldown Transistor 100Ω
(max); Off-Resistance 10MΩ (typ) Individual Activity Latches Capture
Asynchronous State Changes at PIO Inputs for
Interrogation by the Bus Master Data-Strobe Output to Synchronize PIO Logic
States to External Read/Write Circuitry Minimalist 1-Wire Interface Lowers Cost and
Interface Complexity Built-in Multidrop Controller Ensures
Compatibility with Other 1-Wire® Net Products Supports 1-Wire Conditional Search Command
with Response Controlled by Programmable PIO
Conditions Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection and
Absolute Part Identity Communicates to Host with a Single Digital
Signal at 15.3kbps or 100kbps Wide Voltage and Temperature Operating Ranges
Enables Robust System Performance 2.8V to 5.25V -40°C to +85°C Industrial Temperature Range
PIN CONFIGURATION 150-mil SO
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2408S+ -40°C to +85°C 16 SO
DS2408S+T&R -40°C to +85°C 16 SO
+Denotes a lead(Pb)-free package.
T&R = Tape and reel.
DESCRIPTION The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain and
provide an on resistance of 100Ω max. A robust PIO channel-access communication protocol ensures that PIO
output-setting changes occur error-free. A data-valid strobe output can be used to latch PIO logic states into
external circuitry such as a D/A converter (DAC) or microcontroller data bus.
DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the
standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit
ROM registration number that is factory lasered into the chip. The registration number guarantees unique
identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408
devices can reside on a common 1-Wire bus and can operate independently of each other. The DS2408 also
supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity; the
conditions to cause participation in the conditional search are programmable. The DS2408 has an optional VCC
supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire
bus. When an external supply is present, PIO states are maintained in the absence of the 1-Wire bus power
source. The RSTZ signal is configurable to serve as either a hard-wired reset for the PIO output or as a strobe
DS2408
ABSOLUTE MAXIMUM RATINGS* P0 to P7, RSTZ, I/O Voltage to GND -0.5V, +6V
P0 to P7, RSTZ, I/O combined sink current 20mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Lead temperature (soldering 10s) +300°C
Soldering Temperature (reflow) +260°C This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTERISTICS (VCC = 0V or ≥ VPUP, TA = -40°C or +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1-Wire Pullup
Voltage VPUP Standard speed 2.8 5.25 V Overdrive speed 3.3 5.25
Standby Supply
Current ICCS VCC at VPUP,
I/O pin at 0.3V 1 μA
I/O Pin General Data 1-Wire Pullup
Resistance RPUP (Notes 1, 2) 2.2 kΩ
Input Capacitance CIO (Notes 3, 4) 1200 pF
Input Load Current IL I/O pin at VPUP,
VCC at 0V 1 μA
High-to-Low
Switching Threshold VTL (Notes 4, 5, 6) 0.5 3.2 V
Input-Low Voltage VIL (Notes 1, 7) 0.30 V
Low-to-High
Switching Threshold VTH (Notes 4, 5, 8) 0.8 3.4 V
Switching Hysteresis VHY (Notes 9, 4) 0.16 0.73 V
Output-Low Voltage
at 4mA VOL (Note 10) 0.4 V
Recovery Time
(Note 1) tREC
Standard speed, RPUP =
2.2kΩ 5
μs
Overdrive speed, RPUP =
2.2kΩ 2
Overdrive speed, Directly
prior to reset pulse; RPUP
= 2.2kΩ
Rising-Edge Hold-off
Time (Notes 11, 4) tREH Standard speed 0.5 5 μs Overdrive speed 0.5 2
Timeslot Duration
(Notes 1, 12) tSLOT Standard speed 65 μs Overdrive speed 10
DS2408
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O Pin, 1-Wire Reset, Presence-Detect Cycle Reset-Low Time
(Notes 1, 12) tRSTL
Standard speed, VPUP >
4.5V 480 720
μs Standard speed 660 720
Overdrive speed 53 80
Presence-Detect High
Time (Note 12) tPDH Standard speed 15 60 μs Overdrive speed 2 7
Presence-Detect Fall
Time (Note 13) tFPD
Standard speed, VPUP >
4.5V 1 5
μs Standard speed 1 8
Overdrive speed 1
Presence-Detect Low
Time (Note 12) tPDL
Standard speed, VPUP >
4.5V 60 240
μs Standard speed 60 280
Overdrive speed 7 27
Presence-Detect
Sample Time (Note 1) tMSP
Standard speed, VPUP >
4.5V 65 75
μs Standard speed 68 75
Overdrive speed 8 9
I/O Pin, 1-Wire Write Write-0 Low Time
(Notes 1, 12, 14) tW0L Standard speed 60 120 μs Overdrive speed 8 13
Write-1 Low Time
(Notes 1, 12, 14) tW1L Standard speed 5 15 μs Overdrive speed 1 1.8
Write Sample Time
(Slave Sampling)
(Note 12)
tSLS
Standard speed 15 60
μs Overdrive speed 1.8 8
I/O Pin, 1-Wire Read Read-Low Time
(Notes 1, 15) tRL Standard speed 5 15 - δ μs Overdrive speed 1 1.8 - δ
Read-0 Low Time
(Data From Slave)
(Note 12)
tSPD
Standard speed 15 60
μs Overdrive speed 1.8 8
Read-Sample Time
(Notes 1, 12, 15) tMSR Standard speed tRL + δ 15 μs Overdrive speed tRL + δ 1.8
P0 to P7, RSTZ Pin Input-Low Voltage VIL (Notes 1, 7) 0.30 V
Input-High Voltage VIH VX = max (VPUP,VCC)
(Note 1) VX - 0.8 5.25 V
Output-Low Voltage
at 4mA VOL (Note 10) 0.4 V
Leakage Current ILP 5.25V at the pin 1 μA
Output Fall Time tFPIO (Notes 4, 16) 100 ns
Minimum-Sensed
PIO Pulse tPWMIN (Notes 4, 17) 1 5 μs
DS2408
Note 1: System Requirement
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
Note 3: If a 2.2kΩ resistor is used to pull up the data line to VPUP, 5μs after power has been applied,
the parasite capacitance does not affect normal communications.
Note 4: Guaranteed by design—not production tested.
Note 5: VTL and VTH are functions of the internal supply voltage, which in parasitic power mode, is a
function of VPUP and the 1-Wire recovery times. The VTH and VTL maximum specifications
are valid at VPUP = 5.25V. In any case, VTL < VTH < VPUP.
Note 6: Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 7: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line
low.
Note 8: Voltage above which, during a rising edge on I/O, a logic '1' is detected.
Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be
detected as logic '0'.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: The earliest recognition of a negative edge is possible at tREH after VTH has been reached
before.
Note 12: Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
comparison table below.
Note 13: Interval during the negative edge on I/O at the beginning of a presence detect pulse between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP.
Note 14: ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from VIL to VTH. The actual maximum duration for the master to pull the line low is
tW1LMAX + tF - ε and tW0LMAX + tF - ε respectively.
Note 15: δ in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from VIL to the input high threshold of the bus master. The actual maximum duration for
the master to pull the line low is tRLMAX + tF.
Note 16: Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP. PIO pullup resistor = 2.2kΩ.
Note 17: Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
(for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If
tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the
pulse will be recognized and latched.
Note 18: Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requirement for current balance among different pins.
DS2408
PARAMETER
NAME
STANDARD VALUES DS2408 VALUES
STANDARD
SPEED
OVERDRIVE
SPEED
STANDARD
SPEED
OVERDRIVE
SPEED
MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61μs (undef.) 7μs (undef.) 65μs 1) (undef.) 10μs (undef.)
tRSTL 480μs (undef.) 48μs 80μs 660μs 720μs 53μs 80μs
tPDH 15μs 60μs 2μs 6μs 15μs 60μs 2μs 7μs
tPDL 60μs 240μs 8μs 24μs 60μs 280μs 7μs 27μs
tW0L 60μs 120μs 6μs 16μs 60μs 120μs 8μs 13μs
tSLS, tSPD 15μs 60μs 2μs 6μs 15μs 60μs 1.8μs 8μs
1) Intentional change, longer recovery-time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
PIN NAME DESCRIPTION N.C. Not Connected P0
I/O Pin of Channel 0. Logic input/open-drain output with 100Ω maximum
on-resistance; 0V to 5.25V operating range. Power-on default is
indeterminate. If it is application-critical for the outputs to power up in the
"off" state, the user should attach an appropriate power-on-reset circuit or
supervisor IC to the RSTZ pin. VCC Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND
if not used. I/O 1-Wire Interface. Open-drain, requires external pullup resistor. GND Ground N.C. Not Connected P7 I/O Pin of Channel 7. Same characteristics as P0. P6 I/O Pin of Channel 6. Same characteristics as P0. P5 I/O Pin of Channel 5. Same characteristics as P0.
10 RSTZ
SW configurable PIO reset input (RST) or open-drain strobe output
(STRB). When configured as RST, a LOW input sets all PIO outputs to
the "off" state by setting all bits in the PIO Output Latch State Register.
When configured as STRB, an output strobe will occur after a PIO write
(see Channel-Access Write command) or after a PIO Read (see Channel-
Access Read command). The power-on default function of this pin is
RST.
11 P4 I/O pin of channel 4; same characteristics as P0
12 P3 I/O pin of channel 3; same characteristics as P0
13 P2 I/O pin of channel 2; same characteristics as P0
14 P1 I/O pin of channel 1; same characteristics as P0
15 N.C. Not connected
16 N.C. Not connected
DS2408
APPLICATION The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers,
remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network
interface of a microcontroller. Typical application circuits and communication examples are found later
in this data sheet (Figures 17 to 22).
OVERVIEW Figure 1 shows the relationships between the major function blocks of the DS2408. The device has two
main data components: 1) 64-bit lasered ROM, and 2) 64-bit register page of control and status registers.
Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of
the eight ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional
Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM, 7) Overdrive-Match ROM, or 8) Resume. Upon
completion of an Overdrive ROM command byte executed at standard speed, the device will enter
overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for
these ROM function commands is described in Figure 12. After a ROM function command is success-
fully executed, the control functions become accessible and the master may provide any one of the five
available commands. The protocol for these control commands is described in Figure 8. All data is read
and written least significant bit first.
Figure 1. DS2408 BLOCK DIAGRAM VCC
64-BIT
LASERED ROM
CRC16
GENERATOR
REGISTER
PAGE
REGISTER
FUNCTION
CONTROL
1-WIRE
FUNCTION
CONTROL
PORT
FUNCTION
CONTROL
I/O
GND
PARASITE POWER
INTERNAL VCC
PORT
INTER-
FACE
RSTZ
DS2408
Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL 1-Wire NetOther
Devices
Bus
Master
Command
Level:
1-Wire ROM Function
Commands
DS2408-Specific
Control Function
Commands
DS2408Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Conditional Search
ROM
Overdrive Match
Overdrive Skip
Resume
Read PIO Registers
Channel Access Read
Channel Access Write
Write Conditional
Search Register
Reset Activity Latches
Data Field
Affected:
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
RC-FLAG
64-BIT ROM, RC-FLAG, Port Status,
Cond. Search Settings,
64-BIT ROM, RC-FLAG, OD-Flag
RC-FLAG, OD-Flag
RC-FLAG
PIO Registers
Port Input Latches
Port Output Latches
Conditional Search Register
Activity Latches
Cmd.
Codes:
33h
55h
F0h
CCh
ECh
69h
3Ch
A5h
F0h
F5h
5Ah
CCh
C3h
PARASITE POWER The DS2408 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor
during periods of time when the signal line is high. During low times the device continues to operate from
this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor) supply.
If power is available, the VCC pin should be connected to the external voltage supply.
Figure 3. 64-BIT LASERED ROM MSB LSB
8-BIT
CRC CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY
CODE (29h)
MSB LSB MSB LSB MSB LSB
64-BIT LASERED ROM Each DS2408 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. See Figure 3
for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27.
DS2408
The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code,
one bit at a time is shifted in. After the eighth bit of the family code has been entered, the serial number is
entered. After the serial number has been entered, the shift register contains the CRC value. Shifting in
the eight bits of CRC returns the shift register to all 0s.
Figure 4. 1-Wire CRC GENERATOR 0X1X2X3X4X5X6X7X8
POLYNOMIAL = X8 + X5 + X4 + 1st
STAGEnd
STAGErd
STAGEth
STAGEth
STAGEth
STAGEth
STAGEth
STAGE
INPUT DATA
REGISTER ACCESS The registers needed to operate the DS2408 are organized as a Register Page, as shown in Figure 5. All
registers are volatile, i. e., they lose their state when the device is powered down. PIO, Conditional
Search, and Control/Status registers are read/written using the device level Read PIO Registers and Write
Conditional Search Register commands described in subsequent sections and Figure 8 of this document.
Figure 5. DS2408 REGISTER ADDRESS MAP
ADDRESS RANGE ACCESS TYPE DESCRIPTION 0000h to 0087h R Undefined Data
0088h R PIO Logic State
0089h R PIO Output Latch State Register
008Ah R PIO Activity Latch State Register
008Bh R/W Conditional Search Channel Selection Mask
008Ch R/W Conditional Search Channel Polarity Selection
008Dh R/W Control/Status Register
008Eh to 008Fh R These Bytes Always Read FFh
DS2408
PIO Logic-State Register The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as
STRB. See the Channel-Access commands description for details on STRB.
PIO Logic State Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
0088h P7 P6 P5 P4 P3 P2 P1 P0
This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in
Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds
reading the first (least significant) bit of this register. See the Read PIO Registers command description
for details.
PIO Output Latch State Register The data in this register represents the latest data written to the PIO through the Channel-access Write
command. This register is read using the Read PIO Registers command. Reading this register does not
generate a signal at the RSTZ pin, even if it is configured as STRB. See the Channel-access commands
description for details on STRB. This register is not affected if the device reinitializes itself after an ESD
hit.
PIO Output Latch State Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
0089h PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
This register is read-only. Each bit is associated with the output latch of the respective PIO channel as
shown in Figure 6.
The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO
channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
PIO Activity Latch State Register The data in this register represents the current state of the PIO activity latches. This register is read using
the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even
if it is configured as STRB. See the Channel-access commands description for details on STRB.
PIO Activity Latch State Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Ah AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as
shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin
(only if RSTZ is configured as RSTinput), or by successful execution of the Reset Activity Latches
command.
DS2408
Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM PIO
OUTPUT
LATCH
PIO ACTIVITY
LATCH
EDGE
DETECTOR
PORT
FUNCTION
CONTROL
TO ACTIVITY LATCH
STATE REGISTER
TO PIO LOGIC
STATE REGISTER
TO PIO
OUTPUT LATCH
STATE REG.DQ
"1"
CLR ACT LATCH
ROS
STRB
CHANNEL
I/O PIN
RSTZ
PIN
DATA
CLOCK
POWER ON
RESET
Conditional Search Channel Selection Mask Register The data in this register controls whether a PIO channel qualifies for participation in the conditional
search command. To include one or more of the PIO channels, the bits in this register that correspond to
those channels need to be set to 1. This register can only be written through the Write Conditional Search
Registers command.
Conditional Search Channel Selection Mask Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Bh SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0
This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.
This register is cleared to 00h by a power-on reset
DS2408
Conditional Search Channel Polarity Selection Register The data in this register specifies the polarity of each selected PIO channel for the device to respond to
the conditional search command. Within a PIO channel, the data source may be either the channel's input
signal (pin) or the channel's activity latch, as specified by the PLS bit in the Control/Status register at ad-
dress 008Dh. This register can only be written through the Write Conditional Search Registers command.
Conditional Search Channel Polarity Selection Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Ch SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.
This register is cleared to 00h by a power-on reset.
Figure 7. Conditional Search Logic AL7
PLSSP0SM0CT
SM7SP7
AL0
CSR
INPUT FROM
CHANNELS 1 TO 6
(NOT SHOWN)
CHANNEL 0
CHANNEL 7
DS2408
Control/Status Register The data in this register reports status information, determines the function of the RSTZ pin and further
configures the device for conditional search. This register can only be written through the Write Condi-
tional Search Registers command.
Control/Status Register Bitmap ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Dh VCCP 0 0 0 PORL ROS CT PLS
This register is read/write. Without VCC supply, this register reads 08h after a power-on reset. The func-
tional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function;
they will always read 0 and cannot be set to 1.
Control/Status Register Details
BIT DESCRIPTION BIT(S) DEFINITION PLS: Pin or Activity
Latch Select
b0 Selects either the PIO pins or the PIO activity latches as input for the
conditional search. 0: pin selected (default) 1: activity latch selected
CT: Conditional Search
Logical Term
b1 Specifies whether the data of two or more channels needs to be OR’ed
or AND’ed to meet the qualifying condition for the device to respond to a
conditional search. If only a single channel is selected in the channel
selection mask (008Bh) this bit is a don't care. 0: bitwise OR (default) 1: bitwise AND
ROS: RSTZ Pin Mode
Control
b2 Configures RSTZ as either RSTinput or STRBoutput 0: configured as RSTinput (default) 1: configured as STRBoutput
PORL: Power-On Reset
Latch
b3 Specifies whether the device has performed a power-on reset. This bit
can only be cleared to 0 under software control. As long as this bit is 1
the device will always respond to a conditional search.
VCCP: VCC Power
Status (Read-Only)
b7 For VCC powered operation the VCC pin needs to be tied to a voltage
source ≥ VPUP. 0: VCC pin is grounded 1: VCC -powered operation
The interaction of the various signals that determine whether the device responds to a conditional search
is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection
SP determines for each channel whether the channel signal needs to be 1 or 0 to qualify. The PLS bit
determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all
channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or
OR’ed result as the conditional search response signal CSR.
Note on CT bit: OR The qualifying condition is met if the input (pin state or activity latch) for one or more selected
channels matches the corresponding polarity.
AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected
channel must match the corresponding polarity.
DS2408
Figure 8-1. CONTROL FUNCTIONS FLOW CHART Bus Master TX
TA1 (T7:T0), TA2 (T15:T8)N
F0h
Read PIO Reg.
Address
< 90h
To Figure 8nd Part
From Figure 8nd Part
Bus Master TX Control
Function Command
To ROM Functions
From ROM Functions
Flow Chart (Figure 12)
DS2408 sets Register
Address = (T15:T0)
Bus Master RX Data Byte
from Register Address
Bus Master RX CRC16
of Command, Address,
Data Bytes
Bus Master
RX “1”s
DS2408 Incre-
ments Address
Counter
Master
TX Reset
Address
< 90h
Master
TX Reset
Master
TX Reset
Note:To read the three PIO state and latch
register bytes, the target address should
be 0088h. Returned data for a target
address <0088h is undefined.
Address
= 88h
DS2408 Samples
PIO Pin Status
Note 1)See the command
description for the
exact timing of the
PIO pin sampling.
DS2408
Figure 8-2. CONTROL FUNCTIONS FLOW CHART DS2408
Figure 8-3. CONTROL FUNCTIONS FLOW CHART DS2408
CONTROL FUNCTION COMMANDS Once a ROM function command is completed, the Control Function Commands can be issued. The
Control Functions Flow Chart (Figure 8) describes the protocols necessary for accessing the PIO
channels and the special function registers of the DS2408. The communication between the master and
the DS2408 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not
explicitly set into the overdrive mode, the device operates at standard speed.
Read PIO Registers [F0h] The Read PIO Registers command is used to read any of the device's registers. After issuing the
command, the master must provide the 2-byte target address. After these two bytes, the master reads data
beginning from the target address and may continue until address 008Fh. If the master continues reading,
it will receive an inverted 16-bit CRC of the command, address bytes, and all data bytes read from the
initial starting byte through the end of the register page. This CRC16 is the result of clearing the CRC
generator and then shifting in the command byte followed by the two address bytes and the data bytes
beginning at the first addressed location and continuing through to the last byte of the register page. After
the bus master has received the CRC16, the DS2408 responds to any subsequent read-time slots with
logical 1’s until a 1-Wire Reset command is issued. If this command is issued with target address 0088h
(PIO Logic State Register), the PIO sampling takes place during the transmission of the MS bit of TA2. If
the target address is lower than 0088h, the sampling takes place while the master reads the MS bit from
address 0087h.
Channel-Access Read [F5h] In contrast to reading the PIO logical state from address 88h, this command reads the status in an endless
loop. After 32 bytes of PIO pin status the DS2408 inserts an inverted CRC16 into the data stream, which
allows the master to verify whether the data was received error-free. A Channel-Access Read can be
terminated at any time with a 1-Wire Reset.
Figure 9. CHANNEL-ACCESS READ TIMING IO (1-Wire)
STRB\
Example - Sampled State = 72h
MS 2 bits of pre-
vious byte (8Dh)
LS 2 bits of data
byte (72h)
tSPDtSPD
tSPDSampling Point
Notes: 1) The "previous byte" could be the command code, the data byte resulting from the previous PIO
sample, or the MS byte of a CRC16. The example shows a read-1 time slot.
2) The sample point timing also applies to the Channel-access Write command, with the "previous byte"
being the write confirmation byte (AAh). No STRB pulse results when sampling occurs during a
Channel-Access Write command.
DS2408
The status of all eight PIO channels is sampled at the same time. The first sampling occurs during the last
(most significant) bit of the command code F5h. While the master receives the MSB of the PIO status
(i.e., the status of pin P7) the next sampling occurs and so on until the master has received 31 PIO
samples. Next, the master receives the inverted CRC16 of the command byte and 32 PIO samples (first
pass) or the CRC of 32 PIO samples (subsequent passes). While the last (most significant) bit of the CRC
is transmitted the next PIO sampling takes place. The delay between the beginning of the time slot and
the sampling point is independent of the bit value being transmitted and the data direction (see Figure 9).
If the RSTZ pin is configured as STRB, a strobe signal will be generated during the transmission of the
first two (least significant) bits of PIO data. The strobe can signal a FIFO or a microcontroller to apply
the next data byte at the PIO for the master to read through the 1-Wire line.
Channel-Access Write [5Ah] The Channel-Access Write command is the only way to write to the PIO output-latch state register
(address 0089h), which controls the open-drain output transistors of the PIO channels. In an endless loop
this command first writes new data to the PIO and then reads back the PIO status. The implicit read-after-
write can be used by the master for status verification or for a fast communication with a microcontroller
that is connected to the port pins and RSTZ for synchronization. A Channel-Access Write can be termi-
nated at any time with a 1-Wire Reset.
Figure 10. CHANNEL-ACCESS WRITE TIMING IO (1-Wire)
PIO
STRB\
39h72h
tSLS
tSPD
tSPD
Case #1 - MS Bit of new PIO state is 0Example - Old State = 39h, New state = 72h
MS 2 bits of inverted
new-state byte (8Dh)
LS 2 bits of confir-
mation byte (AAh)
Case #2 - MS Bit of new PIO state is 1Example - Old State = 72h, New state = 93h
MS 2 bits of inverted
new-state byte (6Ch)
LS 2 bits of confir-
mation byte (AAh)
72h93h
tSPD
tSPD
VTH
Note: Both examples assume that the RSTZ pin is configured as STRBoutput. If RSTZ is configured as RST
input (default), the RSTZ pin needs to be tied high (to VCC or VPUP) for the Channel-Access Write to
function properly. Leaving the pin unconnected will force the output transistors of the PIO channels to the
"off" state and the PIO output latches will all read "1". See Figure 6 for a schematic of the logic.
After the command code the master transmits a byte that determines the new state of the PIO output
transistors. The first (least significant) bit is associated to P0. To switch the output transistor off (non-
conducting) the corresponding bit value is 1. To switch the transistor on that bit needs to be 0. This way
the data byte transmitted as the new PIO output state arrives in its true form at the PIO pins. To protect
the transmission against data errors, the master has to repeat the new PIO byte in its inverted form. Only
if the transmission was successful will the PIO status change. The actual transition at the PIO to the new
state occurs during the last (most significant) bit of the inverted new PIO data byte and depends on the
polarity of that bit, as shown in Figure 10. If this bit is a 1, the transition begins after tSLS is expired; in
DS2408
the data pattern AAh. If the RSTZ pin is configured as STRB, a strobe signal will be generated during the
transmission of the first two (least significant) bits of the confirmation byte. The strobe can signal a FIFO
or a microcontroller to read the new data byte from the PIO. While the last bit of the confirmation byte is
transmitted, the DS2408 samples the status of the PIO pins, as shown in Figure 9, and sends it to the
master. Depending on the data, the master can either continue writing more data to the PIO or issue a 1-
Wire reset to end the command.
Write Conditional Search Register [CCh] This command is used to tell the DS2408 the conditions that need to be met for the device to respond to a
Conditional Search command, to define the function of the RSTZ pin and to clear the power-on reset flag.
After issuing the command the master sends the 2-byte target address, which must be a value between
008Bh and 008Dh. Next the master sends the byte to be written to the addressed cell. If the address was
valid, the byte is immediately written to its location in the register page. The master now can either end
the command by issuing a 1-Wire reset or send another byte for the next higher address. Once register
address 008Dh has been written, any subsequent data bytes will be ignored. The master has to send a 1-
Wire reset to end the command. Since the Write Conditional Search Register flow does not include any
error-checking for the new register data, it is important to verify correct writing by reading the registers
using the Read PIO Registers command.
Reset Activity Latches [C3h] Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin.
This change may be caused by an external event/signal or by writing to the PIO. Depending on the
application there may be a need to reset the activity latch after having captured and serviced an external
event. Since there is only read access to the PIO Activity Latch State Register, the DS2408 supports a
special command to reset the latches. After having received the command code, the device resets all
activity latches simultaneously. There are two ways for the master to verify the execution of the Reset
Activity Latches command. The easiest way is to start reading from the 1-Wire line right after the
command code is transmitted. In this case the master will read AAh bytes until it sends a 1-Wire reset.
The other way to verify execution is to read register address 008Ah.
1-WIRE BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS2408 is a slave device. The bus master is typically a microcontroller or PC. For small configurations
the 1-Wire communication signals can be generated under software control using a single port pin. For
multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip
(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor
from responding in real time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from
the bus master.
HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
DS2408
Figure 11. HARDWARE CONFIGURATION OPEN-DRAIN
PORT PIN
RX = RECEIVE
TX = TRANSMIT100Ω
MOSFET
VPUPDATA
SEE
TEXT
SIMPLE BUS MASTERDS2408 1-Wire PORT
RPUP
DS2480B
+5V
HOST CPUVDD
POL
RXD
TXD
VPP
1-W
GND
SERIAL IN
SERIAL OUT
SERIAL
PORT
TO 1-Wire DATA
DS2480B BUS MASTER
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus
has a maximum data rate of 15.3kbps. Communication speed for 1-Wire devices can be typically boosted
to 142kbps by activating the overdrive mode; however, the maximum overdrive data rate for the DS2408
is 100kbps. The value of the pullup resistor primarily depends on the network size and load conditions.
For most applications the optimal value of the pullup resistor will be approximately 2.2kΩ for standard
speed and 1.5kΩ for overdrive speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16μs (overdrive speed) or more than 120μs (standard speed), one or more devices on the
bus may be reset. With the DS2408 the bus must be left low for no longer than 13μs at overdrive speed to
ensure that none of the slave devices on the 1-Wire bus performs a reset. The DS2408 communicates
properly when used in conjunction with a DS2480B 1-Wire driver and serial port adapters that are based
on this driver chip. When operating the device in overdrive or below 4.5V, some 1-Wire I/O timing
values must be modified (see EC table).
DS2408
TRANSACTION SEQUENCE The protocol for accessing the DS2408 through the 1-Wire port is as follows: Initialization ROM Function Command Control Function Command Transaction/Data
Illustrations of the transaction sequence for the various control function commands are found later in this
document.
INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2408 is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (see the flowchart in
Figure 12).
Read ROM [33h] This command allows the bus master to read the DS2408's 8-bit family code, unique 48-bit serial number,
and 8-bit CRC. This command can only be used if there is a single device on the bus. If more than one
slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will
result in a mismatch of the CRC.
Match ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a spe-
cific DS2408 on a multidrop bus. Only the DS2408 that exactly matches the 64-bit ROM sequence will
respond to the following control function command. All slaves that do not match the 64-bit ROM se-
quence will wait for a reset pulse. This command can be used with either single or multiple devices on the
bus.
Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the
1-Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a
process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM
process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then
write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of
the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may be identified by additional passes. See
Application Note 187 for a detailed discussion on the Search ROM command process including a
software example.
Conditional Search [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only
