DS2406 ,Dual Addressable Switch Plus 1-kbit MemoryFEATURES PIN ASSIGNMENTTO-92 6-PIN TSOC PACKAGE Open drain PIO pins are controlled and their®logic ..
DS2406 ,Dual Addressable Switch Plus 1-kbit MemoryPIN DESCRIPTIONindependently of other devices on the busTO-92 TSOC/CSP Unique, factory-lasered and ..
DS2406+ ,Dual Addressable Switch Plus 1Kb MemoryFEATURES PIN ASSIGNMENTTO-92 6-PIN TSOC PACKAGE Open drain PIO pins are controlled and their®logic ..
DS2406P ,Dual Addressable Switch Plus 1-kbit MemoryPIN DESCRIPTIONindependently of other devices on the bus TO-92 TSOC/CSP Unique, factory-lasered an ..
DS2406P+ ,Dual Addressable Switch Plus 1Kb MemoryPIN DESCRIPTIONindependently of other devices on the busTO-92 TSOC/CSP Unique, factory-lasered and ..
DS2406X ,Dual Addressable Switch Plus 1-kbit MemoryFEATURES PIN ASSIGNMENTTO-92 6-PIN TSOC PACKAGE Open drain PIO pins are controlled and theirlogic ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2406
Dual Addressable Switch Plus 1-kbit Memory
FEATURESOpen drain PIO pins are controlled and their
logic level can be determined over 1-Wire®
bus for closed-loop controlReplaces and is fully compatible with
DS2407 but no user-programmable power-onsettings and no Hidden ModePIO channel A sink capability of 50mA at
0.4V with soft turn-on; channel B 8mA at
0.4VMaximum operating voltage of 13V atPIO-A, 6.5V at PIO-B1024 bits user-programmable OTP EPROMUser-programmable status memory to
control the deviceMultiple DS2406’s can be identified on acommon 1-Wire bus and be turned on or off
independently of other devices on the busUnique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)assures error-free selection and absolute
identity because no two parts are alikeOn-chip CRC16 generator allows detection
of data transfer errorsBuilt-in multidrop controller ensurescompatibility with other 1-Wire net productsReduces control, address, data, programming
and power to a single data pinDirectly connects to a single port pin of amicroprocessor and communicates at up to
16.3 kbits/sSupports Conditional Search with user-
selectable conditionVcc bondout for optional external supply tothe device (TSOC package only)1-Wire communication operates over a wide
voltage range of 2.8V to 6.0V from -40°C to
+85°CLow cost TO-92 or 6-pin TSOC surface
PIN ASSIGNMENT6-PIN TSOC PACKAGE
TOP VIEW25
SIDE VIEW
BOTTOM VIEW
TO-92
See Mech. DrawingsSection3
PIN DESCRIPTION
TO-92TSOC/CSPPin 1GroundGround
Pin 2DataDataPin 3PIO-APIO-A
Pin 4---Vcc
Pin 5---NC
Pin 6---PIO-B
ORDERING INFORMATIONDS2406TO-92 package
DS2406P6-pin TSOC package
DS2406/T&R Tape & Reel of DS2406
DS2406P/T&RTape & Reel of DS2406P
DS2406XChip Scale Pkg., Tape &Reel
DS2406
Dual Addressable Switch
Plus 1kbit Memory
DS2406
ADDRESSABLE SWITCH DESCRIPTIONThe DS2406 Dual Addressable Switch™ Plus Memory offers a simple way to remotely control a pair of
open drain transistors and to monitor the logic level at each transistor’s output via the 1-Wire bus forclosed loop control. Each DS2406 has its own 64-bit ROM registration number that is factory lasered into
the chip to provide a guaranteed unique identity for absolute traceability. The device’s 1024 bits of
EPROM can be used as electronic label to store information such as switch function, physical location,
and installation date. Communication with the DS2406 follows the standard Dallas Semiconductor
1-Wire protocol and can be accomplished with minimal hardware such as a single port pin of amicrocontroller. Multiple DS2406 devices can reside on a common 1-Wire network and be operated
independently of each other. Individual devices will respond to a Conditional Search command if they
qualify for certain user-specified conditions, which include the state of the output transistor, the static
logic level or a voltage transition at the transistor’s output.
DS2406 BLOCK DIAGRAM Figure 1PIO-A
PIO-B
1-WIRE BUS
DS2406
OVERVIEWThe block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2406. The device has four major data components: 64-bit lasered ROM, 1024 bits of EPROM datamemory, status memory, and the PIO-control block. The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide one of the five ROM function commands: Read
ROM, Match ROM, Search ROM, Skip ROM, or Conditional Search ROM. The protocol required for
these ROM functions is described in Figure 13. After a ROM functions command is successfully
executed, the PIO-control and memory functions become accessible and the master may provide any oneof the six memory- and control function commands. The protocol for these functions is described in
Figure 7. All data is read and written least significant bit first.
HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL Figure 2Other
DS2406
PARASITE POWERThe DS2406 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor
during periods of time when the signal line is high. During low times the device continues to operate offof this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor)
supply. In applications where the device may be temporarily disconnected from the 1-Wire bus or where
the low-times of the 1-Wire bus may be very long the VCC pin may be connected to an external voltage
supply to maintain the device status.
When writing to the EPROM memory, the 1-Wire communication occurs at normal voltage levels and
then is pulsed momentarily to the programming voltage to cause the selected EPROM bits to be
programmed. The bus master must be able to provide 12V and 10mA to adequately program the EPROM
portions of the device. During programming, only EPROM-based devices are allowed to be present on
the 1-Wire bus.
64-BIT LASERED ROMEach DS2406 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X + X + X + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27 or the Book of DS19xx iButton®
Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the
family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the
serial number is entered. After the 48th bit of the serial number has been entered, the shift register
contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all zeros. The64-bit ROM and the 1-Wire Function Control section allow the DS2406 to operate as a 1-Wire device and
follow the protocol detailed in the section “1-Wire Bus System”.
64-BIT LASERED ROM Figure 3MSBLSB
MSBLSBMSBLSBMSBLSB
1-WIRE CRC GENERATOR Figure 42X1X0X7X6X5X4X3
INPUT DATA
Polynomial = X8 + X5 + X4 + 1
DS2406
MEMORY MAPThe DS2406 has two memory sections, called data memory and status memory. The data memory
consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. Theaddress range of the device’s status memory is 8 bytes. The first seven bytes of status memory (addresses
0 to 6) are implemented as EPROM. The eighth byte (address 7) consists of static RAM. The complete
memory map is shown in Figure 5. The 8-bit scratchpad is an additional register that acts as a buffer when
writing the memory. Data is first written to the scratchpad and then verified by reading a 16-bit CRC
from the DS2406 that confirms proper receipt of the data and address. This process ensures data integritywhen programming the memory. If the buffer contents are correct, the bus master should transmit a
programming pulse (EPROM) or a dummy byte FFh (RAM) to transfer the data from the scratchpad to
the addressed memory location. The details for reading and programming the DS2406 are given in the
Memory Function Commands section.
DS2406 MEMORY MAP Figure 5
Page #Address RangeDescription
DS2406 STATUS MEMORY MAP Figure 6
DS2406
STATUS MEMORYThe Status Memory can be read or written to indicate various conditions to the software interrogating the
DS2406. These conditions include special features for the data memory, definition of the settings for theConditional Search as well as the channel flip-flops and the external power supply indication. How these
functions are assigned to the bits of the Status Memory is detailed in Figure 6.
The first 4 bits of the Status Memory (address 0, bits 0 to 3) contain the Write Protect Page bits which
inhibit programming of the corresponding page in the 1024-bit data memory area if the appropriate writeprotection bit is programmed. Once a bit has been programmed in the Write Protect Page section of the
Status Memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still
be read. The remaining 4 bits of Status Memory location 0 are reserved for use by the iButton operating
software TMEX. Their purpose is to indicate which memory pages are already in use. Originally, all of
these bits are unprogrammed, indicating that the device does not contain any data. As soon as data iswritten to any page of the device under control of TMEX, the bit inside this bitmap corresponding to that
page will be programmed to 0, marking this page as used. These bits are application flags only and have
no impact on the internal logic of the DS2406.
The next four bytes of the Status Memory (addresses 1 to 4) contain the Page Address Redirection Bytes
which indicate if one or more of the pages of data in the 1024-bits EPROM memory section have been
invalidated by software and redirected to the page address contained in the appropriate redirection byte.
The hardware of the DS2406 makes no decisions based on the contents of the Page Address Redirection
Bytes. Since with EPROM technology bits can only be changed from a logical 1 to a logical 0 byprogramming, it is not possible to simply rewrite a page if the data requires changing or updating. But
with space permitting, an entire page of data can be redirected to another page within the DS2406. Under
TMEX, a page is redirected by writing the one’s complement of the new page address into the Page
Address Redirection Byte that corresponds to the original (replaced) page. This architecture allows the
user’s software to make a “data patch” to the EPROM by indicating that a particular page or pages shouldbe replaced with those indicated in the Page Address Redirection Bytes.
Under TMEX, if a Page Address Redirection Byte has a FFh value, the data in the main memory that
corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value than FFh,
the data in the page corresponding to that redirection byte is invalid. According to the TMEX definitions,the valid data will now be found at the one’s complement of the page address indicated by the hex value
stored in the associated Page Address Redirection Byte. A value of FDh in the redirection byte for page 1,
for example, would indicate that the updated data is now in page 2. Since the data memory consists of
four pages only, the 6 most significant bits of the redirection bytes cannot be programmed to zeros.
Status Memory location 5 serves as a test byte and is programmed to 00h at the factory. Status Memory
location 6 has no function with the DS2406. It is factory-programmed to 00h to distinguish the DS2406
from the DS2407, which both share the same family code. A DS2407 with Status Memory location 6
programmed to 00h will power-up into hidden mode and will only respond if the bus master addresses it
by a Match ROM command followed by the correct device ROM code. Conversely, a device that doesrespond to a Read ROM command with family code 12h can only be a DS2406 if its Status Memory
location 6 reads 00h.
DS2406
Status Memory location 7 serves three purposes: 1) it holds the selection code for the Conditional Searchfunction, 2) provides the bus master a memory mapped access to the channel flip-flops that control the
PIO output transistors, and 3) allows the bus master to determine whether the device is hooked up to a
VCC power supply. Bit locations 0 to 4 store the conditional search settings. Their codes are explained in
the section “ROM Function Commands” later in this document. The channel flip-flops are accessible
through bit locations 5 and 6 as well as through the Channel Access function. The power-on default forthe conditional search settings and the channel flip-flops is all 1’s. Setting a channel flip-flop to 0 will
make the associated PIO-transistor conducting or on; setting the flip-flop to 1 will switch the transistor
off, which is identical to the power-on default. With the VCC pin connected to a suitable power supply the
power indicator bit 7 will read 1. The power supply indicator can also be read through the Channel
Access function.
MEMORY FUNCTION COMMANDSThe “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
various data fields and PIO channels within the DS2406. The Memory Function Control section, 8-bit
scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus
master and create the correct control signals within the device. A three-byte protocol is issued by the busmaster. It is comprised of a command byte to determine the type of operation and two address bytes to
determine the specific starting byte location within a data field or to supply and exchange setup and status
data when accessing the PIO channels. The command byte indicates if the device is to be read or written
or if the PIO channels are to be accessed. Writing data involves not only issuing the correct command
sequence but also providing a 12-volt programming voltage at the appropriate times. To execute a writesequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address.
Write sequences always occur a byte at a time. To execute a read sequence, the starting address is issued
by the bus master and data is read from the part beginning at that initial location and continuing to the end
of the selected data field or until a reset sequence is issued. All bits transferred to the DS2406 and
received back by the bus master are sent least significant bit first.
Read Memory [F0h]The Read Memory command is used to read data from the 1024-bit EPROM data memory field. The bus
master follows the command byte with a two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates
a starting byte location within the data field. Since the data memory contains 128 bytes, T15:T8 and T7
should all be zero. With every subsequent read data time slot the bus master receives data from theDS2406 starting at the initial address and continuing until the end of the 1024-bits data field is reached or
until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may
issue sixteen additional read time slots and the DS2406 will respond with a 16-bit CRC of the command,
address bytes and all data bytes read from the initial starting byte through the last byte of memory. This
CRC is the result of clearing the CRC generator and then shifting in the command byte followed by thetwo address bytes and the data bytes beginning at the first addressed memory location and continuing
through to the last byte of the EPROM data memory. After the CRC is received by the bus master, any
subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a
Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available.
Typically the software controlling the device should store a 16-bit CRC with each page of data to insure
rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the
received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended
file structure to be used with the 1-Wire environment). If CRC values are imbedded within the data it is
DS2406
Extended Read Memory [A5h]The Extended Read Memory command supports page redirection when reading data from the 1024-bit
EPROM data field. One major difference between the Extended Read Memory and the basic ReadMemory command is that the bus master receives the Redirection Byte (see description of Status
Memory) first before investing time in reading data from the addressed memory location. This allows the
bus master to quickly decide whether to continue and access the data at the selected starting page or to
terminate and restart the reading process at the redirected page address.
In addition to page redirection, the Extended Read Memory command also supports “bit-oriented”
applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications
the EPROM information may change over time within a page boundary making it impossible to include
an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command
concludes each page with the DS2406 generating and supplying a 16-bit CRC that is based on andtherefore always consistent with the current data stored in each page of the 1024-bit EPROM data field.
After having sent the command code of the Extended Read Memory command, the bus master sends a
two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the datafield. By sending eight read data time slots, the master receives the Redirection Byte associated with the
page given by the starting address. With the next sixteen read data time slots, the bus master receives a
16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the
DS2406 and read back by the bus master to check if the command word, starting address and Redirection
Byte were received correctly.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and
receives data from the DS2406 starting at the initial address and continuing until the end of a 32-byte
page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting
byte to the last byte of the current page.
With the next 24 read data time slots the master will receive the Redirection Byte of the next page
followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 1024-bitsEPROM data field starting at the beginning of the new page. This sequence will continue until the final
page and its accompanying CRC are read by the bus master.
The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction
flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end ofthe memory page is always the result of clearing the CRC generator and shifting in the data bytes
beginning at the first addressed memory location of the EPROM data page until the last byte of this page.
With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value after the
Redirection Byte is the result of shifting the command byte into the cleared CRC generator, followed by
the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memoryflow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in
the Redirection Byte only. After the 16-bit CRC of the last page is read, the bus master will receive
logical 1s from the DS2406 until a Reset Pulse is issued. The Extended Read Memory command
sequence can be ended at any point by issuing a Reset Pulse.
DS2406
WRITING EPROM MEMORYThe function flow for writing to the Data Memory and Status Memory is almost identical. After the
appropriate write command has been issued, the bus master will send a two-byte starting address(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address
bytes, and data byte is computed by the DS2406 and read back by the bus master to confirm that the
correct command word, starting address, and data byte were received.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence mustbe repeated. If the CRC received by the bus master is correct, a programming pulse (12V on the 1-Wire
bus for 480 µs) is issued by the bus master. Prior to programming, the entire unprogrammed EPROM
memory field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set
to a logical 0, the corresponding bit in the selected byte of the EPROM memory is programmed to a
logical 0 after the programming pulse has been applied.
After the 480 µs programming pulse is applied and the data line returns to the idle level (5V), the bus
master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2406
responds with the data from the selected EPROM address sent least significant bit first. This byte containsthe bit-wise logical AND of all data ever written to this address. If the EPROM byte contains 1s in bit
positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current
byte address should be programmed again. If the DS2406 EPROM byte contains 0s in the same bit
positions as the data byte, the programming was successful and the DS2406 will automatically increment
its address counter to select the next byte in the EPROM memory field. The new two-byte address willalso be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte
of data using eight write time slots.
As the DS2406 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte andthe new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2406
with sixteen read time slots to confirm that the address incremented properly and the data byte was
received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the write sequence must be
restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in
memory will be programmed.
Note that the initial pass through the write flow chart will generate an 16-bit CRC value that is the result
of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the
data byte. Subsequent passes through the write flow chart due to the DS2406 automatically incrementing
its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue (to apply a program pulse to the DS2406) is made
entirely by the bus master, since the DS2406 will not be able to determine if the 16-bit CRC calculated by
the bus master agrees with the 16-bit CRC calculated by the DS2406. If an incorrect CRC is ignored andthe bus master applies a program pulse, incorrect programming could occur within the DS2406. Also note
that the DS2406 will always increment its internal address counter after the receipt of the eight read time
slots used to confirm the programming of the selected EPROM byte. The decision to continue is again
made entirely by the bus master. Therefore if the EPROM data byte does not match the supplied data byte
but the master continues with the write command, incorrect programming could occur within the DS2406.
DS2406
Memory Function Flow Chart Figure 7
DS2406
Memory Function Flow Chart (continued) Figure 7
DS2406
Memory Function Flow Chart (continued) Figure 7
DS2406
Write Memory [0Fh]The Write Memory command is used to program the 1024-bit EPROM data memory. The details of the
functional flow chart are described in the section “Writing EPROM Memory”. The data memory addressrange is 0000h to 007Fh. If the bus master sends a starting address higher than this, the nine most
significant address bits are set to zeros by the internal circuitry of the chip. This will result in a mismatch
between the CRC calculated by the DS2406 and the CRC calculated by the bus master, indicating an error
condition.
Write Status [55h]The Write Status command is used to program the Status Memory, which includes the specification of the
Conditional Search Settings. The details of the functional flow chart are described in the section “Writing
EPROM Memory”.
The Status Memory address range is 0000h to 0007h. The general programming algorithm is valid for theEPROM section of the Status Memory (addresses 0 to 4) only. The Status memory locations 5 and 6 are
already pre-programmed to 00h and therefore cannot be altered. Status memory location 7 consists of
static RAM, which can be reprogrammed without limitation and does not require a 12V programming
pulse. The supply indication (bit 7) is read-only; attempts to write to it are ignored. The function flow for
writing to status memory location 7 is basically the same as for the other EPROM Status Memory Bytes.However, instead of a programming pulse the bus master may send a FFh byte (equivalent to 8 Write-One
Time Slots) to transfer the new value from the scratchpad to the status memory.
If the bus master sends a starting address higher than 0007h, the nine most significant address bits are set
to zeros by the internal circuitry of the chip. The address bits T3:T6 remain unchanged and will beignored by the address decoder of the DS2406. Only if one or more of the address bits T8:T15 is set, the
bus master will be able to discover an error condition based on the CRC16 that is calculated by the
DS2406.
Read Status [AAh]The Read Status command is used to read data from the Status Memory field. The functional flow chartof this command is identical to the Read Memory command. Since the Status Memory is only 8 bytes, the
DS2406 will send the 16-bit CRC after the last byte of status information has been transmitted.
Channel Access [F5h]The Channel Access command is used to access the PIO channels to sense the logical status of the output
node and the output transistor and to change the status of the output transistor. The bus master will follow
the command byte with two Channel Control Bytes and will receive back the Channel Info byte. TheChannel Control bytes allow the master to select a PIO-channel to communicate with, to specify
communication parameters, and to reset the activity latches. Figure 8 shows the details Channel Control
Byte 1. The bit assignments of Channel Control Byte 2 are reserved for future development. The bus
master should always send FFh for the second Channel Control Byte.
CHANNEL CONTROL BYTE 1 Figure 8
DS2406
Most easily understood are the bits CHS0 and CHS1, which select the channels to communicate with.One can select one of the two channels or both channels together. The selection codes are shown in the
table below.
When reading only a single channel, the logic level at the selected PIO is sampled at the beginning of
each read time slot (Figure 10a) and is immediately signaled through the 1-Wire line. Because the PIOlogic levels are sensed at the beginning of the time slot, the bus master does not see transitions at the PIO
that occur during the time slot. When writing to a single channel, the selected PIO will show the new
status after (but not necessarily immediately after) the 1-Wire line has returned to its idle level of
typically 5V (see Figure 10a). If the bus master transmits a 1 (Write One Time Slot), the output transistor
of the selected channel will change its status after time td1, which is 15µs to 60µs after the beginning ofthe time slot. If the bus master transmits a 0 (Write Zero Time Slot), the output transistor will change its
status with a delay of td0 after the 1-Wire line has returned to its idle level. The value of td0 may vary
between 200 and 300 ns (see Figure 10a). Depending on the load conditions, there may be additional
delay until the voltage at the PIO reaches a new logical level.
When communicating with both channels, the Interleave Control Bit IC controls when data is sampled
and when data arrives at the PIO pins. There is an asynchronous mode (IC = 0) and a synchronous mode
(IC = 1). For the asynchronous mode, both channels are accessed in an alternating way. For the synchro-
nous mode, both channels are accessed simultaneously. For single-channel operation the Interleave
Control Bit must be set to 0.
When reading in the asynchronous mode each channel is sampled alternately at the start of each Read
Time Slot, beginning with channel A. The logic level detected at the PIO is immediately transmitted to
the master during the same time slot. When reading in the synchronous mode, both channels will be
sampled at the same time. The data bit from channel A will be sent to the master immediately during thesame time slot while the data bit from channel B follows with the next time slot which does not sample
the PIOs. Both channels will be sampled again with the time slot that follows the transmission of the data
bit from PIO-B (Figure 10b).
When writing in the asynchronous mode, each channel will change its status independently of the other.The change of status occurs with the same timing relations as for communication with one channel.
However, every second write time slot addresses the same channel. The first time slot is directed to
channel A, the second to channel B, the next to channel A and so on. As a consequence, in asynchronous
mode both PIOs can never change their status at the same time. When writing in the synchronous mode,
both channels operate together. After the new values for both channels have arrived at the DS2406 thechange of status at both channels occurs with the same timing relations as for communication with one
channel. As with the asynchronous mode, every second write time slot contains data for the same
channel. The first time slot addresses channel A, the second channel B and so on. Depending on the data
values, in the synchronous mode both PIOs can change their status at the same time (Figure 10c). In any
of these cases, the information of channel A and channel B will appear alternating on the 1-Wire line,always starting with channel A. By varying the idle-time between time slots on the 1-Wire line one has
DS2406
The TOG bit of Channel Control Byte 1 specifies if one is always reading or writing (TOG = 0) or if oneis going to change from reading to writing or vice versa after every data byte that has been sent to or
received from the DS2406 (TOG = 1). When accessing one channel, one byte is equivalent to eight reads
from or writes to the selected PIO pin. When accessing two channels, one byte is equivalent to four reads
or writes from/to each channel.
The initial mode (reading or writing) for accessing the PIO channels is specified in the IM bit. For read-
ing, IM has to be set to 1, for writing IM needs to be 0. If the TOG bit is set to 0, the device will always
read or write as specified by the IM bit. If TOG is 1, the device will use the setting of IM for the first byte
to be transmitted and will alternate between reading and writing after every byte. Table 1 illustrates the
effect of TOG and IM for one-channel as well as for two-channel operation.
THE EFFECT OF TOGGLE MODE AND INITIAL MODE Table 1The ALR bit of Channel Control Byte 1 controls whether the activity latch of each channel gets reset.
Both activity latches are cleared simultaneously if the ALR bit is 1. They are not changed if the ALR bit
is 0. An activity latch is set with a negative or positive edge that occurs at its associated PIO channel.
Channel Control Byte 1 also controls the internal CRC generator to safeguard data transmission betweenthe bus master and the DS2406 for channel access. It does not affect reading from or writing to the
memory sections of the DS2406. The CRC control bits (bit 0 and bit 1) can be set to create and protect
data packets that have the size of 8 bytes or 32 bytes. If desired, the device can safeguard even single
bytes by a 16-bit CRC. This setting, however, limits the average PIO sampling rate to about one third of
its maximum possible value. The codes for the CRC control are shown in the table below.
The CRC provides a high level of safeguarding data. A detailed description of CRCs is found in
Application Note 27 and the “Book of DS19xx iButton Standards”. If the CRC is disabled, the CRC-
related sections in the flow chart are skipped.
DS2406
After the Channel Control bytes have been transmitted the bus master receives the Channel Info byte(Figure 9). This byte indicates the status of the channel flip-flops, the PIO pins, the activity latches as
well as the availability of channel B and external power supply. To be able to read from a PIO channel,
the output transistor needs to be non-conducting, which is equivalent to a 1 for the channel flip-flop.
Reading 0 for both the channel flip-flop and the sensed level indicates that the output transistor of the PIO
is pulling the node low. For the Channel Info byte PIO A and B are sampled at the same time, as in thesynchronous mode. If channel B is available, bit 6 of the Channel Info Byte reads 1. For 1-channel
versions of the DS2406, the PIO B sensed level, channel flip-flop value, and activity latch value should
be ignored. Without an external supply, the supply indication bit (bit 7) reads 0. As long as the voltage
applied to the VCC pin is high enough to operate the device this bit will read 1.
CHANNEL INFO BYTE Figure 9
ONE-CHANNEL READ/WRITE Figure 10aPIO
1-WIRE
READ (IC=0, Asynchronous Mode)
WRITE (IC=0, Asynchronous Mode)PIO
1-WIRE
PIO SAMPLING
TWO-CHANNEL READ Figure 10bPIO-A
PIO SAMPLING
1-WIRE
PIO-B5798642
