DS2404B-DS2404S Fast Delivery |IC PHOENIX CO.,LIMITED

DS2404S ,EconoRAM Time ChipPIN DESCRIPTION§ 256-bit scratchpad with strict read/writeV – 2.8 to 5.5 VoltsCCprotocols ensures ..
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DS2405Z ,Addressable SwitchFEATURES PIN ASSIGNMENT TSOC PACKAGE§ Open drain PIO pin is controlled byTO-92match ..
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DS2404B-DS2404S
EconoRAM Time Chip
FEATURES 4096 bits of nonvolatile dual-port memory
including real time clock/calendar in binaryformat, programmable interval timer, and
programmable power-on cycle counter 1-WireTM interface for MicroLAN
communication at 16.3k bits per second 3-wire host interface for high-speed datacommunications at 2M bits per second Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts arealike Memory partitioned into 16 pages of 256-bits
for packetizing data 256-bit scratchpad with strict read/write
protocols ensures integrity of data transfer§ Programmable alarms can be set to generate
interrupts for interval timer, real time clock,
and/or cycle counter 16-pin DIP, SOIC and SSOP packages Operating temperature range from -40°C to+85°C Operating voltage range from 2.8 to 5.5
Volts
ORDERING INFORMATION
DS2404 16-pin DIP
DS2404S 16-pin SOIC
DS2404B 16-pin SSOP
PIN ASSIGNMENT
PIN DESCRIPTION
VCC – 2.8 to 5.5 Volts
IRQ – Interrupt Output
RST – 3-Wire Reset Input
DQ – 3-Wire Input/Output
I/O – 1-Wire Input/OutputCLK – 3-Wire Clock Input
NC – No Connection
GND – Ground
VBATB – Battery Backup InputVBATO – Battery Operate Input
1 Hz – 1 Hz Output
X1 ,X2 – Crystal Connections
DESCRIPTION
The DS2404 EconoRAM Time Chip offers a simple solution for storing and retrieving vital data and timeinformation with minimal hardware. The DS2404 contains a unique lasered ROM, real-time
clock/calendar, interval timer, cycle counter, programmable interrupts and 4096-bits of SRAM. Two
separate ports are provided for communication, 1-Wire and 3-wire. Using the 1-Wire port, only one pin is
required for communication, and the lasered ROM can be read even when the DS2404 is without power.
The 3-wire port provides high speed communication using the traditional Dallas Semiconductor 3-wire
interface. With either interface, a strict protocol for accessing the DS2404 ensures data integrity. Utilizingbackup energy sources, the data is nonvolatile and allows for stand-alone operation.
EconoRAM Time Chip
DS2404
DETAILED PIN DESCRIPTION
OVERVIEW
The DS2404 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bitSRAM, and 4) timekeeping registers. The timekeeping section utilizes an on-chip oscillator that is
connected to an external 32.768 kHz crystal. The SRAM and timekeeping registers reside in one
contiguous address space referred to hereafter as memory. All data is read and written least significant bit
first.
Two communication ports are provided, a 1-Wire port and a 3-wire port. A port selector determines
which of the two ports is being used. The communication ports and the ROM are parasite-powered via
I/O, RST, or VCC . This allows the ROM to be read in the absence of power. The ROM data is accessible
only through the 1-Wire port. The scratchpad and memory are accessible via either port.
If the 3-wire port is used, the master provides one of four memory function commands: 1) read memory,
2) read scratchpad, 3) write scratchpad, or 4) copy scratchpad. The only way to write memory is to first
write the scratchpad and then copy the scratchpad data to memory. (See Figure 6.)
If the 1-Wire port is used, the memory functions will not be available until the ROM function protocol
has been established. This protocol is described in the ROM functions flow chart (Figure 9). The master
must first provide one of five ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM,4) skip ROM or 5) search interrupt. After a ROM function sequence has been successfully executed, the
DS2404
The “Power Control” section provides for two basic power configurations, battery operate mode and VCC
operate mode. The battery operate mode utilizes one supply connected to VBATO . The VCC operate mode
may utilize two supplies; the primary supply connects to VCC and a backup supply connects to VBATB .
DS2404 BLOCK DIAGRAM Figure 1
COMMUNICATION PORTS
Two communication ports are provided, a 1-Wire and a 3-wire port. The advantages of using the 1-Wire
port are as follows: 1) provides access to the 64-bit lasered ROM, 2) consists of a single communication
signal (I/O), and 3) multiple devices may be connected to the 1-Wire bus. The 1-Wire bus has a
maximum data rate of 16.3k bits/second and requires one 5kW external pullup.
The 3-wire port consists of three signals, RST, CLK, and DQ. RSTis an enable input, DQ is bidirectional
serial data, and the CLK input is used to clock in or out the serial data. The advantages of using the 3-
wire port are 1) high data transfer rate (2 MHz), 2) simple timing, and 3) no external pullup required.
Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first
DS2404
More information on how to arbitrate port access is found in section “Device Operation Modes” later in
this document.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the I/O, RST, or VCC pins are high. When using the 1-Wire port in battery operate mode,
RSTand VCC provide no power since they are low. However, I/O will provide sufficient power as long as
the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1)
by parasiting off these pins, battery power is conserved and 2) the ROM may be read in absence of
normal power. For instance, in battery-operate mode, if the battery fails, the ROM may still be readnormally.
In battery-backed mode, if VCC fails, the port switches in the battery but inhibits communication. The
ROM may still be read normally over the 1-Wire port if RST is low.
64-BIT LASERED ROM
Each DS2404 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code (DS2404 code is 04h). The next 48 bits are a unique serial number. The last eight bits are a CRC ofthe first 56 bits. (See Figure 2.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-
Wire Cyclic Redundancy Check is available in Application Note 27, “Understanding and Using CyclicRedundancy Checks with Dallas Semiconductor iButton Products”.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number
is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.
64-BIT LASERED ROM Figure 2
CRCSERIAL NUMBERDS2404 FAMILY CODE
MSBLSB
1-WIRE CRC CODE Figure 3
DS2404
MEMORY MAP Figure 4
DS2404
MEMORY
The memory map in Figure 4 shows a page (32 bytes) called the scratchpad and 17 pages called memory.Pages 0 through 15 each contain 32 bytes which make up the 4096-bit SRAM. Page 16 has only 30 bytes
which contain the timekeeping registers.
The scratchpad is an additional page of memory that acts as a buffer when writing to memory. Data isfirst written to the scratchpad where it can be read back. After the data has been verified, a copy
scratchpad command will transfer the data to memory. This process ensures data integrity when
modifying the memory.
TIMEKEEPING
A 32.768 kHz crystal oscillator is used as the time base for the timekeeping functions. The oscillator can
be turned on or off by an enable bit in the control register. The oscillator must be on for the real time
clock, interval timer, cycle counter and 1 Hz output to function.
The timekeeping functions are double buffered. This feature allows the master to read time or countwithout the data changing while it is being read. To accomplish this, a snapshot of the counter data is
transferred to holding registers which the user accesses. This occurs after the eighth bit of the Read
Memory Function command.
Real-Time Clock
The real-time clock is a 5-byte binary counter. It is incremented 256 times per second. The least
significant byte is a count of fractional seconds. The upper four bytes are a count of seconds. The real-
time clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the
number of seconds since a reference point which is determined by the user. For example, 12:00A.M.,January 1, 1970 could be a reference point.
Interval Timer
The interval timer is a 5-byte binary counter. When enabled, it is incremented 256 times per second. Theleast significant byte is a count of fractional seconds. The interval timer can accumulate 136 years of
seconds before rolling over. The interval timer has two modes of operation which are selected by the
MANAUTO/ bit in the control register. In the auto mode, the interval timer will begin counting after the
I/O line has been high for a period of time determined by the DSEL bit in the control register. Similarly,
the interval timer will stop counting after the I/O line has been low for a period of time determined by the
DSEL bit. In the manual mode, time accumulation is controlled by the STARTSTOP/bit in the control
register.
NOTE: For auto mode operation, the high level on the I/O pin must be greater than or equal to 70% of
VCC or VBATO .
Cycle Counter
The cycle counter is a 4-byte binary counter. It increments after the falling edge of the I/O line if the
appropriate I/O line timing has been met. This timing is selected by the DSEL bit in the control register.
(See “Status/ Control” section).
NOTE: For cycle counter operation, the high level on the I/O pin must be greater than or equal to 70% ofVCC or VBATO .
DS2404
Alarm Registers
The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the samemanner. When the value of a given counter equals the value in its associated alarm register, the
appropriate flag bit is set in the status register. If the corresponding interrupt enable bit(s) in the status
register is set, an interrupt is generated. If a counter and its associated alarm register are write protected
when an alarm occurs, access to the device becomes limited. (See “Status/Control”, “Interrupts”, and the“Programmable Expiration” sections.)
STATUS/CONTROL REGISTERS
The status and control registers are the first two bytes of page 16 (see “Memory Map”, Figure 4).
Status Register65432100200hReal-time clock alarm flagInterval timer alarm flagCycle counter alarm flag
When a given alarm occurs, the corresponding alarm flag is set to a logic 1. The alarm flag(s) is clearedby reading the status register.Real-time interrupt enableInterval timer interrupt enableCycle counter interrupt enable
Writing any of the interrupt enable bits to a logic 0 will allow an interrupt condition to be generated when
its corresponding alarm flag is set (see “Interrupts” section).
Control Register65432100201hWrite protect real-time clock/alarm registersWrite protect interval timer/alarm registersWrite protect cycle counter/alarm registers
DS2404
Setting a write protect bit to a logic 1 will permanently write protect the corresponding counter and alarm
registers, all write protect bits, and additional bits in the control register. The write protect bits can not be
written in a normal manner (see “Write Protect/Programmable Expiration” section).Read Only
If a programmable expiration occurs and the read only bit is set to a logic 1, then the DS2404 becomes
read only. If a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit
lasered ROM can be accessed (see “Write Protect/Programmable Expiration” section).Oscillator enable
This bit controls the crystal oscillator. When set to a logic 1, the oscillator will start operation. When theoscillator bit is a logic 0, the oscillator will stop.Automatic/Manual Mode
When this bit is set to a logic 1, the interval timer is in automatic mode. In this mode, the interval timer is
enabled by the I/O line. When this bit is set to a logic 0, the interval timer is in manual mode. In this
mode the interval timer is enabled by the STOP/START bit.Stop/Start (in Manual Mode)
If the interval timer is in manual mode, the interval timer will start counting when this bit is set to a logic
0 and will stop counting when set to a logic 1. If the interval timer is in automatic mode, this bit has no
effect.Delay Select Bit
This bit selects the delay that it takes for the cycle counter and the interval timer (in auto mode) to see atransition on the I/O line. When this bit is set to a logic 1, the delay time is 123 + 2 ms. This delay allows
communication on the I/O line without starting or stopping the interval timer and without incrementing
the cycle counter. When this bit is set to a logic 0, the delay time is 3.5 ±0.5 ms.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
memory. Two examples follow the flowchart. Three address registers are provided as shown in Figure 5.
The first two registers represent a 16-bit target address (TA1, TA2). The third register is the ending
offset/data status byte (E/S).
The target address points to a unique byte location in memory. The first five bits of the target address
(T4:T0) represent the byte offset within a page. This byte offset points to one of 32 possible byte
locations within a given page. For instance, 00000b points to the first byte of a page where as 11111b
would point to the last byte of a page.
DS2404
The third register (E/S) is a read only register. The first five bits (E4: E0) of this register are called the
ending offset. The ending offset is a byte offset within a page. Bit 5 (PF) is the partial byte flag. Bit 6
(OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.
ADDRESS REGISTERS Figure 56543210
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user must first provide the 2–byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at
the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the host stops writingdata. The maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum
offset, the overflow flag (OF) will be set and the remaining data will be ignored. If the user writes an
incomplete byte and an overflow has not occurred, the partial byte flag (PF) will be set.
Read Scratchpad Command [AAh]
This command may be used to verify scratchpad data and target address. After issuing the read scratchpad
command, the user may begin reading. The first two bytes will be the target address. The next byte will
be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset
(T4: T0). The user may read data until the end of the scratchpad after which the data read will be all logic1’s.
Copy Scratchpad [55h]
This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, the user must provide a 3-byte authorization pattern. This pattern must exactly match the datacontained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA
(Authorization Accepted) flag will be set and the copy will begin. At this point, the part will go into a TX
mode, transmitting a logic 1 to indicate the copy is in progress. A logic 0 will be transmitted after the data
has been copied. Any attempt to reset the part will be ignored while the copy is in progress. Copy
typically takes 30 ms.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset through the ending offset, will be copied to memory, starting at the target address.
Anywhere from 1 to 32 bytes may be copied to memory with this command. Whole bytes are copied evenif only partially written. The AA flag will be cleared only by executing a write scratchpad command.
DS2404
MEMORY FUNCTION FLOW CHART Figure 6
DS2404
Read Memory [F0h]
The read memory command may be used to read the entire memory. After issuing the command, the usermust provide the 2-byte target address. After the two bytes, the user reads data beginning from the target
address and may continue until the end of memory, at which point logic 1’s will be read. It is important to
realize that the target address registers will contain the address provided. The ending offset/data status
byte is unaffected.
The hardware of the DS2404 provides a means to accomplish error-free writing to the memory section.
To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets of the size of one memory page each. Such a packet
would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that
eliminate having to read a page multiple times to determine if the received data is correct or not. (See theBook of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-
Wire environment.)
MEMORY FUNCTION EXAMPLES
Example 1: Write one page of data to page 15
Read page 15 (3-wire port)
TA2
NOTE: The ROM function commands do not apply to the 3-wire port. After RSTis at a high level, the
device expects to receive a memory function command.
DS2404
Example 2: Write two data bytes to memory locations 0026h and 0027h (the seventh and eighth byte of
page 1). Read entire memory (1-Wire port).
TA2 AUTHORIZATION CODE
WRITE PROTECT/PROGRAMMABLE EXPIRATION
The write protect bits (WPR, WPI, WPC) provide a means of write protecting the timekeeping data and
limiting access to the DS2404 when an alarm occurs (programmable expiration).
The write protect bits may not be written by performing a single copy scratchpad command. Instead, to
write these bits, the copy scratchpad command must be performed three times. Please note that the AA bit
will be set, as expected, after the first copy command is successfully executed. Therefore, theauthorization pattern for the second and third copy command should have this bit set. The read
scratchpad command may be used to verify the authorization pattern.
DS2404
The write protect bits, once set, permanently write protects their corresponding counter and alarm
registers, all write protect bits, and certain control register bits as shown in Figure 7. The time/count
registers will continue to count if the oscillator is enabled. If the user wishes to set more than one write
protect bit, the user must set them at the same time. Once a write protect bit is set it cannot be undone,
and the remaining write protect bits, if not set, cannot be set.
The programmable expiration takes place when one or more write protect bits have been set and a
corresponding alarm occurs. If the RO (read only) bit is set, only the read scratchpad and read memory
function commands are available. If the RO bit is a logic “0”, no memory function commands are
available. The ROM functions are always available.
WRITE PROTECT CHART Figure 7
* Becomes write “1” only, i.e., once written to a logic “1”, may not be written back to a logic “0”.
** Forced to a logic “0”.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In most instances the
DS2404 behaves as a slave. The exception is when the DS2404 generates an interrupt due to a
timekeeping alarm. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2404 (I/O pin 5) is open drain with an internal circuitequivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor
of approximately 5kW.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120 ms, one or more of the devices on the bus may be reset.
DS2404
HARDWARE CONFIGURATION Figure 8
TRANSACTION SEQUENCE
The protocol for accessing the DS2404 via the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2404 is on the bus and is ready to
operate. For more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the five ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 9):
Read ROM [33h]
This command allows the bus master to read the DS2404’s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can only be used if there is a single DS2404 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will usually result in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2404 on a multidrop bus. Only the DS2404 that exactly matches the 64-bit ROM sequence
will respond to the following memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the
bus.

Partno	Mfg	Dc	Qty	Available	Descript
DS2404B	DALLAS	N/a	1	avai	EconoRAM Time Chip
DS2404S		N/a	8	avai	EconoRAM Time Chip