DS2401+T ,Silicon Serial NumberDS2401Silicon Serial Numberwww.dalsemi.com
DS2401AX1-03B-00 ,Silicon Serial NumberDS2401Silicon Serial Number
DS2401P ,Silicon Serial NumberFEATURES PIN ASSIGNMENT TSOC PACKAGE§ Upgrade and drop-in replacement forTO-92DS2400DALLAS- ..
DS2401P/T&R ,Silicon Serial NumberFEATURES PIN ASSIGNMENT Upgrade and drop-in replacement for DS2400TO-92TSOC PACKAGE— Extended 2.8 ..
DS2401P+ ,Silicon Serial NumberPIN DESCRIPTION16.3kbits/sTO-92/SOT-223 TSOC TO-92 Tape & Reel version with leads bentPin 1 Ground ..
DS2401P+T , Silicon Serial Number Unique, Factory-Lasered and Tested 64-Bit
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2401+T-DS2401P-DS2401X1-DS2401Z
Silicon Serial Number
FEATURES Upgrade and drop-in replacement for
DS2400- Extended 2.8 to 6.0 voltage rangeMultiple DS2401s can reside on a
common 1-Wire bus Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester);
guaranteed no two parts alike Built-in multidrop controller ensures
compatibility with other MicroLAN
products§ 8-bit family code specifies DS2401
communications requirements to reader Presence Pulse acknowledges when the
reader first applies voltage Low-cost TO-92, SOT-223 and TSOCsurface mount packages Reduces control, address, data, and power to
a single pin Zero standby power required Directly connects to a single port pin of amicroprocessor and communicates at up to
16.3 kbits/s TO-92 tape & reel version with leads bent to
100 mil spacing (default) or with straight
leads (DS2401T-SL)§ Applications
- PCB Identification
- Network Node IDEquipment Registration Operates over industrial temperature range of-40°C to +85°C
PIN ASSIGNMENT TSOC PACKAGE
PIN DESCRIPTION
TO-92/SOT-223TSOCPin 1GroundGround
Pin 2Data (DQ)Data (DQ)
Pin 3No ConnectNo Connect
Pin 4GroundNo ConnectPin 5-6-No Connect
ORDERING INFORMATIONDS2401 TO-92 Package
DS2401Z SOT-223 Surface Mount Package
DS2401T Tape & Reel of DS2401
DS2401T-SL Like DS2401T but straight leadsDS2401Y Tape & Reel of DS2401Z
DS2401P TSOC Surface Mount Package
DS2401V Tape & Reel of DS2401P
DS2401X1 Chip Scale Pkg., Tape & Reel
DS2401
DESCRIPTIONThe DS2401 enhanced Silicon Serial Number is a low-cost, electronic registration number that providesan absolutely unique identity which can be determined with a minimal electronic interface, typically a
single port pin of a microcontroller. The DS2401 consists of a factory-lasered, 64-bit ROM that includes a
unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (01h). Data is transferred serially
via the 1-Wire protocol which requires only a single data lead and a ground return. Power for reading andwriting the device is derived from the data line itself with no need for an external power source. The
DS2401 is an upgrade to the DS2400. The DS2401 is fully reverse-compatible with the DS2400 but
provides the additional multi-drop capability that enables many devices to reside on a single data line.
The familiar TO-92, SOT-223 or TSOC package provides a compact enclosure that allows standard
assembly equipment to handle the device easily.
OPERATIONThe DS2401’s internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit family
code and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus transactions
in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulsesfrom the bus master. All data is read and written least significant bit first.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances,the DS2401 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). For a more detailed protocol description, refer to Chapter 4 of the
Book of DS19xx iButton Standards.
Hardware ConfigurationThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an
open drain connection or 3-state outputs. The DS2401 is an open drain part with an internal circuitequivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional
pin is not available, separate output and input pins can be tied together. The bus master requires a pullup
resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3.
The value of the pullup resistor should be approximately 5 kW for short line lengths. A multidrop bus
consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbits per second.
The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120 ms, one or more of the devices on the bus may be reset.
DS2401 MEMORY MAP Figure 1MSB LSBMSB LSBMSB LSB
DS2401
DS2401 EQUIVALENT CIRCUIT Figure 2
BUS MASTER CIRCUIT Figure 3
A) Open Drain
DS2401
TRANSACTION SEQUENCEThe sequence for accessing the DS2401 via the 1-Wire port is as follows: Initialization ROM Function Command Read Data
INITIALIZATIONAll transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by theslave(s).
The Presence Pulse lets the bus master know that the DS2401 is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDSOnce the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure
4):
Read ROM [33h] or [0Fh]This command allows the bus master to read the DS2401’s 8-bit family code, unique 48-bit serialnumber, and 8-bit CRC. This command can only be used if there is a single DS2401 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The DS2401 Read ROM function will occur with a
command byte of either 33h or 0Fh in order to ensure compatibility with the DS2400, which will only
respond to a 0Fh command word with its 64-bit ROM data.
Match ROM [55h] / Skip ROM [CCh]The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a Skip
ROM command. (See the Book of DS19xx iButton Standards). Since the DS2401 contains only the 64-bitROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause no
further activity on the 1-Wire bus if executed. The DS2401 does not interfere with other 1-Wire parts on a
multidrop bus that do respond to a Match ROM or Skip ROM (for example, a DS2401 and DS1994 on
the same bus).
Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search processis the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual
DS2401
1-WIRE SIGNALINGThe DS2401 requires a strict protocol to ensure data integrity. The protocol consists of four types ofsignaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2401 is shown in Figure 5.A reset pulse followed by a Presence Pulse indicates the DS2401 is ready to send or receive data given
the correct ROM command.
The bus master transmits (TX ) a reset pulse (tRSTL , minimum 480 ms). The bus master then releases the
line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the 5 kW pullup
resistor. After detecting the rising edge on the data pin, the DS2401 waits (tPDH, 15-60 ms) and then
transmits the Presence Pulse (tPDL , 60-240 ms).
READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2401 to the master
by triggering a delay circuit in the DS2401. During write time slots, the delay circuit determines when theDS2401 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2401 will hold the data line low overriding the “1” generated by the master.
If the data bit is a 1, the DS2401 will leave the read data time slot unchanged.
DS2401
ROM FUNCTIONS FLOW CHART Figure 4
