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DS2227-100-DS2227-120
Flexible NV SRAM Stik
FEATURESFlexibly organized as 128k x 32, 256k x 16,
or 512k x 8 bitsData retention >10 years in the absence ofVCCNonvolatile circuitry transparent to and
independent from host systemAutomatic write protection circuitry
safeguards against data lossSeparate chip enables allow access by byte,
word, or long wordFast access times: 70 ns, 100 ns, or 120 nsUnlimited write cyclesRead cycle time equals write cycle timeEmploys popular JEDEC standard 72-position
SIMM connection schemeLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
PIN ASSIGNMENT
DESCRIPTIONThe DS2227 Flexible NV SRAM Stik is a self-contained 4,194,304-bit nonvolatile static RAM which can
be flexibly organized as 128k x 32 bits, 256k x 16 bits, or 512k x 8 bits. The nonvolatile memory contains
all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of
power for more than 10 years. The DS2227 employs the popular JEDEC standard 72-position SIMM
connection scheme requiring no additional circuitry.
OPERATION
DS2227
Flexible NV SRAM Stik72-Pin SIP STIK
DS2227
select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV
SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read
enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data
lines from two banks together. Chip enables, read enables, and write enables from these banks are alsotied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket
DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular,
inclined, or parallel mount, depending on the height available. See the DS907x SipStikTM connectors
available from Dallas Semiconductor.
READ MODEThe DS2227 executes a read cycle whenever WE(Write Enable) is inactive (high) and CE(Chip Enable)
and OE(Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 - A16)
defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within
tACC (access time) after the last address input signal is stable, providing that CE and OE access times are
also satisfied. If OE and CE times are not satisfied, then data access must be measured from the later
occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather thanaddress access.
WRITE MODEThe DS2227 is in the write mode whenever both WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs to tODW from its falling edge.
DATA RETENTION MODEThe DS2227 provides fully functional capability for VCC greater than 4.5 volts and guarantees write
protection for VCC less than 4.25 volts. Data is maintained in the absence of VCC without any additional
support circuitry. The DS2227 constantly monitors VCC. Should the supply voltage decay, the NVSRAM automatically write-protects itself, all inputs become “don’t care” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects a lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects the external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.5 volts.
The DS2227 checks lithium status to warn of potential data loss. Each time that VCC power is restored to
the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than
2.0 volts, the second memory access to the device is inhibited. Battery status can, therefore, be
determined by a three-step process. First, a read cycle is performed to any location in memory, in order tosave the contents of that location. A subsequent write cycle can then be executed to the same memory
location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less
than 2.0V and data is in danger of being corrupted.
The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The
DS2227
PIN DESCRIPTION Table 1
NOTE: Leave all pins marked as NC unconnected.
DS2227
SCHEMATIC (1 CELL) Figure 1
DS2227
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.3V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-40° to +85°C
* This is a stress rating only and functional operation of the device at these or any other conditions abovethose indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5V ±10%)
CAPACITANCE(TA = 25°C)
DS2227
AC ELECTRICAL CHARACTERISTICS
