DS21Q58L ,E1 Quad TransceiverAPPLICATIONS Receive Side DSLAMs Interleaving PCM Bus Operation Up to 16.384MHz Routers Conf ..
DS21Q58L+ ,E1 Quad TransceiverAPPLICATIONS Receive Side DSLAMs Interleaving PCM Bus Operation Up to 16.384MHz Routers Conf ..
DS21Q58LN ,E1 Quad TransceiverFEATURES Four Complete E1 (CEPT) PCM-30/ISDN-PRI The DS21Q58 E1 quad transceiver contains all th ..
DS21Q58LN+ ,E1 Quad TransceiverFEATURES Four Complete E1 (CEPT) PCM-30/ISDN-PRI The DS21Q58 E1 quad transceiver contains all th ..
DS21Q59 ,E1 Quad TransceiverAPPLICATIONS Interleaving PCM Bus Operation Up to DSLAMs 16.384MHz Routers Configurable Paral ..
DS21Q59L ,E1 Quad TransceiverFEATURES Four Complete E1 (CEPT) PCM-30/ISDN-PRI The DS21Q59 E1 quad transceiver contains all th ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q58L-DS21Q58LN
E1 Quad Transceiver
GENERAL DESCRIPTION The DS21Q58 E1 quad transceiver contains all the
necessary functions for connecting to four E1 lines.
The DS21Q58 is a direct replacement for the
DS21Q50, with the addition of signaling access and
improved interrupt handling. It is composed of a line
interface unit (LIU), framer, and a TDM backplane
interface, and is controlled through an 8-bit parallel
port configured for Intel or Motorola bus operations or
serial port operation.
APPLICATIONS DSLAMs
Routers
IMA and WAN Equipment
PIN CONFIGURATION
FEATURES Four Complete E1 (CEPT) PCM-30/ISDN-PRI Transceivers Pin Compatible with the DS21Q50 and DS21Q59 Short-Haul Line Interfaces 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Frames to FAS, CAS, and CRC4 Formats CAS/CCS Signaling Support 4MHz/8MHz/16MHz Clock Synthesizer Flexible System Clock with Automatic Source Switching on Loss-of-Clock Source Two-Frame Elastic-Store Slip Buffer on the Receive Side Interleaving PCM Bus Operation Up to 16.384MHz Configurable Parallel and Serial Port Operation Detects and Generates Remote and AIS Alarms Fully Independent Transmit and Receive Functionality Four Separate Loopback Functions PRBS Generation/Detection/Error Counting 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and E Bits Eight Additional User-Configurable Output Pins
��100-Pin (14mm x 14mm) LQFP Package
ORDERING INFORMATION
DS21Q58 Go to
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
DS21Q58 E1 Quad Transceiver
TABLE OF CONTENTS
1. ACRONYMS.......................................................................................................................6
2. DETAILED DESCRIPTION.................................................................................................6
3. BLOCK DIAGRAM.............................................................................................................7
4. PIN DESCRIPTION.............................................................................................................8 4.1 PIN FUNCTION DESCRIPTIONS......................................................................................................12
5. FUNCTIONAL DESCRIPTION.........................................................................................13
6. HOST INTERFACE PORT................................................................................................14 6.1 PARALLEL PORT OPERATION.......................................................................................................14
6.2 SERIAL PORT OPERATION............................................................................................................14
7. REGISTER MAP...............................................................................................................16
8. CONTROL, ID, AND TEST REGISTERS.........................................................................17 8.1 POWER-UP SEQUENCE................................................................................................................18
8.2 FRAMER LOOPBACK....................................................................................................................21
8.3 AUTOMATIC ALARM GENERATION.................................................................................................22
8.4 REMOTE LOOPBACK....................................................................................................................22
8.5 LOCAL LOOPBACK.......................................................................................................................23
9. STATUS AND INFORMATION REGISTERS...................................................................27 9.1 INTERRUPT HANDLING.................................................................................................................28
9.2 CRC4 SYNC COUNTER................................................................................................................29
10. ERROR COUNT REGISTERS..........................................................................................34 10.1 BPV OR CV COUNTER.............................................................................................................34
10.2 CRC4 ERROR COUNTER..........................................................................................................34
10.3 E-BIT/PRBS BIT-ERROR COUNTER..........................................................................................35
10.4 FAS ERROR COUNTER.............................................................................................................35
11. SIGNALING OPERATION................................................................................................36 11.1 RECEIVE SIGNALING.................................................................................................................36
11.2 TRANSMIT SIGNALING...............................................................................................................36
11.3 CAS OPERATION.....................................................................................................................36
12. DS0 MONITORING FUNCTION.......................................................................................37
13. PRBS GENERATION AND DETECTION.........................................................................39
14. SYSTEM CLOCK INTERFACE........................................................................................40
15. TRANSMIT CLOCK SOURCE..........................................................................................41
16. IDLE CODE INSERTION..................................................................................................41
17. PER-CHANNEL LOOPBACK..........................................................................................42
18. ELASTIC STORE OPERATION.......................................................................................42
19. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43
DS21Q58 E1 Quad Transceiver
21. LINE INTERFACE UNIT...................................................................................................47 21.1 RECEIVE CLOCK AND DATA RECOVERY.....................................................................................47
21.1.1 Termination...........................................................................................................................................47
21.2 RECEIVE MONITOR MODE.........................................................................................................48
21.3 TRANSMIT WAVESHAPING AND LINE DRIVING.............................................................................49
21.4 JITTER ATTENUATORS..............................................................................................................51
21.4.1 Clock and Data Jitter Attenuators.........................................................................................................51
21.4.2 Undedicated Clock Jitter Attenuator.....................................................................................................52
22. CODE MARK INVERSION (CMI).....................................................................................53
23. INTERLEAVED PCM BUS OPERATION.........................................................................55
24. FUNCTIONAL TIMING DIAGRAMS.................................................................................57 24.1 RECEIVE..................................................................................................................................57
24.2 TRANSMIT................................................................................................................................59
25. OPERATING PARAMETERS...........................................................................................62
26. AC TIMING PARAMETERS AND DIAGRAMS................................................................63 26.1 MULTIPLEXED BUS AC CHARACTERISTICS.................................................................................63
26.2 NONMULTIPLEXED BUS AC CHARACTERISTICS..........................................................................66
26.3 SERIAL PORT...........................................................................................................................68
26.4 RECEIVE AC CHARACTERISTICS...............................................................................................69
26.5 TRANSMIT AC CHARACTERISTICS.............................................................................................71
26.6 SPECIAL MODES AC CHARACTERISTICS....................................................................................72
27. PACKAGE INFORMATION..............................................................................................73
28. REVISION HISTORY........................................................................................................74
DS21Q58 E1 Quad Transceiver
LIST OF FIGURES Figure 3-1. Block Diagram.......................................................................................................................7
Figure 6-1. Serial Port Operation Mode 1...............................................................................................14
Figure 6-2. Serial Port Operation Mode 2...............................................................................................15
Figure 6-3. Serial Port Operation Mode 3...............................................................................................15
Figure 6-4. Serial Port Operation Mode 4...............................................................................................15
Figure 21-1 Typical Monitor Port Application..........................................................................................48
Figure 21-2. External Analog Connections (Basic Configuration)...........................................................49
Figure 21-3. External Analog Connections (Protected Interface)............................................................50
Figure 21-4. Transmit Waveform Template............................................................................................51
Figure 21-5. Jitter Tolerance...................................................................................................................52
Figure 21-6. Jitter Attenuation................................................................................................................52
Figure 22-1. CMI Coding........................................................................................................................53
Figure 22-2. Example of CMI Code Violation..........................................................................................54
Figure 23-1. IBO Configuration Using Two DS21Q58 Transceivers (Eight E1 Lines)..............................56
Figure 24-1. Receive Frame and Multiframe Timing...............................................................................57
Figure 24-2. Receive Boundary Timing (With Elastic Store Disabled).....................................................57
Figure 24-3. Receive Boundary Timing (With Elastic Store Enabled).....................................................57
Figure 24-4. Receive Interleave Bus Operation......................................................................................58
Figure 24-5. Transmit Frame and Multiframe Timing..............................................................................59
Figure 24-6. Transmit Boundary Timing..................................................................................................59
Figure 24-7. Transmit Interleave Bus Operation.....................................................................................59
Figure 24-8. Framer Synchronization Flowchart.....................................................................................60
Figure 24-9. Transmit Data Flow............................................................................................................61
Figure 26-1. Intel Bus Read AC Timing (PBTS = 0)................................................................................64
Figure 26-2. Intel Bus Write Timing (PBTS = 0)......................................................................................64
Figure 26-3. Motorola Bus AC Timing (PBTS = 1)..................................................................................65
Figure 26-4. Intel Bus Read Timing (PBTS = 0)......................................................................................66
Figure 26-5. Intel Bus Write Timing (PBTS = 0)......................................................................................67
Figure 26-6. Motorola Bus Read Timing (PBTS = 1)...............................................................................67
Figure 26-7. Motorola Bus Write Timing (PBTS = 1)...............................................................................67
Figure 26-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0)............................................................................68
Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled).........................................................69
Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled)........................................................70
Figure 26-11. Transmit AC Timing (IBO Disabled)..................................................................................71
Figure 26-12. Transmit AC Timing (IBO Enabled)..................................................................................72
DS21Q58 E1 Quad Transceiver
LIST OF TABLES Table 4-1. Pin Description (Sorted by Function)......................................................................................8
Table 4-2. Pin Assignments (Sorted by Number)....................................................................................10
Table 4-3. System (Backplane) Interface Pins........................................................................................12
Table 4-4. Alternate Jitter Attenuator......................................................................................................12
Table 4-5. Clock Synthesizer..................................................................................................................12
Table 4-6. Parallel Port Control Pins.......................................................................................................12
Table 4-7. Serial Port Control Pins.........................................................................................................13
Table 4-8. Line Interface Pins.................................................................................................................13
Table 4-9. Supply Pins...........................................................................................................................13
Table 6-1. Bus Mode Select...................................................................................................................14
Table 7-1. Register Map (Sorted by Address).........................................................................................16
Table 8-1. Sync/Resync Criteria.............................................................................................................19
Table 8-2. G.703 Function......................................................................................................................24
Table 8-3. Output Modes........................................................................................................................25
Table 9-1. Alarm Criteria........................................................................................................................29
Table 13-1. Transmit PRBS Mode Select...............................................................................................39
Table 13-2. Receive PRBS Mode Select................................................................................................39
Table 14-1. Synthesizer Output Select...................................................................................................40
Table 14-2. System Clock Selection.......................................................................................................40
Table 20-1. OUTA and OUTB Function Select.......................................................................................46
Table 21-1 Receive Monitor Mode Gain.................................................................................................48
Table 21-2. Line Build-Out Select in LICR..............................................................................................49
Table 21-3. Transformer Specifications..................................................................................................49
Table 23-1. IBO System Clock Select.....................................................................................................55
Table 23-2. IBO Device Assignment.......................................................................................................55
Table 26-1. AC CharacteristicsMultiplexed Parallel Port.....................................................................63
Table 26-2. AC CharacteristicsNonmultiplexed Parallel Port...............................................................66
Table 26-3. AC CharacteristicsSerial Port (BTS1 = 1, BTS0 = 0)........................................................68
Table 26-4. AC CharacteristicsReceive...............................................................................................69
Table 26-5. AC CharacteristicsTransmit..............................................................................................71
Table 26-6. AC CharacteristicsSpecial Modes....................................................................................72
DS21Q58 E1 Quad Transceiver
1. ACRONYMS The following abbreviations are used throughout this data sheet:
2. DETAILED DESCRIPTION The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface
generates the necessary waveshapes for driving the network, depending on the type of media used. E1 waveform
generation includes G.703 waveshapes for both 75� coax and 120� twisted cables. The receive interface recovers
clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator only
requires a 2.048MHz MCLK and can be placed in either the transmit or receive data paths. An additional feature of the LIU is a code mark inversion (CMI) coder/decoder for interfacing to optical networks. On the transmit side, the backplane interface section provides clock/data and frame-sync signals to the framer. The
framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the HDB3 (zero code suppression) and alternate mark inversion (AMI) line coding. The
receive-side framer decodes AMI and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
The backplane interface provides a versatile method of sending and receiving data from the host system. The receive elastic store provides a method for interfacing to asynchronous systems. The elastic store also manages
slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow multiple E1 lines to share a high-speed backplane. The parallel port provides access for control and configuration of all the DS21Q58s features. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. The device fully meets all the latest E1 specifications, including ITU-T G.703, G.704,
G.706, G.823, G.732 and I.431 ETS 300 011, ETS 300 233, and ETS 300 166 as well as CTR12 and CTR4.
The DS21Q58 is optimized for high-density termination of E1 lines. Two significant features are included for this type of application: the IBO and a system clock synthesizer feature. The IBO allows up to eight E1 data streams to
be multiplexed onto a single high-speed PCM bus without additional external logic. The system clock synthesizer allows any of the E1 lines to be selected as the master source of the clock for the system and for all the
transmitters. This is also accomplished without the need of external logic. Each of the four transceivers has a clock and data jitter attenuator that can be assigned to either the transmit or receive path. In addition, there is a single,
undedicated clock jitter attenuator that can be hardware configured as needed by the user. Each transceiver also contains a PRBS pattern generator and detector. Figure 23-1 shows a simplified typical application that terminates
eight E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The 16.384MHz system clock is derived and phase-locked to one of the eight E1 lines. On the receive side of each port,
DS21Q58 E1 Quad Transceiver
3. BLOCK DIAGRAM
Figure 3-1. Block Diagram
DS21Q58 E1 Quad Transceiver
4. PIN DESCRIPTION
Table 4-1. Pin Description (Sorted by Function)
DS21Q58 E1 Quad Transceiver
Note: EQVSS lines are wired to RVSS lines. DS21Q58 E1 Quad Transceiver
Table 4-2. Pin Assignments (Sorted by Number)
DS21Q58 E1 Quad Transceiver
Note: EQVSS lines are wired to RVSS. DS21Q58 E1 Quad Transceiver
4.1 Pin Function Descriptions
Table 4-3. System (Backplane) Interface Pins
Table 4-4. Alternate Jitter Attenuator
Table 4-5. Clock Synthesizer
Table 4-6. Parallel Port Control Pins
DS21Q58 E1 Quad Transceiver
Table 4-7. Serial Port Control Pins
Table 4-8. Line Interface Pins
Table 4-9. Supply Pins
5. FUNCTIONAL DESCRIPTION The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the DS21Q58s RRING and RTIP pins.
The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive framer, where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21Q58
contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0dB to -12dB. The receive framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including carrier loss, loss of
synchronization, AIS, and remote alarm. If needed, the receive elastic store can be enabled to absorb the phase
and frequency differences between the recovered E1 data stream and an asynchronous backplane clock, which is provided at the SYSCLK input. The clock applied at the SYSCLK input can be either a
2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The transmit framer is independent of the receive framer in both the clock requirements and characteristics. The transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125�s frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot
1 is identical to channel 2, and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8. Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term locked is used to refer
to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., an 8.192MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
DS21Q58 E1 Quad Transceiver
6. HOST INTERFACE PORT The DS21Q58 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an
external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table 6-1 for a description of the bus configurations. Motorola bus signals are listed in
parentheses (). See the timing diagrams in the AC Electrical Characteristics in Section 26 for more details.
Table 6-1. Bus Mode Select
6.1 Parallel Port Operation When using the parallel interface on the DS21Q58 (BTS1 = 0) the user has the option for either multiplexed bus
operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q58 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
Section 26 for more details.
6.2 Serial Port Operation Setting the BTS1 pin = 1 and BTS0 pin = 0 enables the serial bus interface on the DS21Q58. Port read/write timing
is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 26 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 6-1, Figure 6-2,
Figure 6-3, and Figure 6-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next five bits identify the register address. The next bit is reserved and must be set to 0 for proper operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode
causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS input low. When input-clock edge select (ICES) is low, input data is
latched on the rising edge of SCLK; when ICES is high, input data is latched on the falling edge of SCLK. When output-clock edge select (OCES) is low, data is output on the falling edge of SCLK; when OCES is high, data is
output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated
if the CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Figure 6-1. Serial Port Operation Mode 1
DS21Q58 E1 Quad Transceiver
Figure 6-2. Serial Port Operation Mode 2
Figure 6-3. Serial Port Operation Mode 3
Figure 6-4. Serial Port Operation Mode 4
DS21Q58 E1 Quad Transceiver
7. REGISTER MAP
Table 7-1. Register Map (Sorted by Address)
DS21Q58 E1 Quad Transceiver
Note 1: The device ID register and the system clock-interface control register exist in Transceiver 1 only (TS0, TS1 = 0).
Note 2: Only the factory uses the test register; this register must be cleared (set to all zeros) on power-up initialization to ensure proper operation.
8. CONTROL, ID, AND TEST REGISTERS The DS21Q58 operation is configured through a set of nine control registers. Typically, the control registers are
only accessed when the system is first powered up. Once the device has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There is one receive control register (RCR), one transmit control register (TCR), and seven common control registers (CCR1 to CCR7). Each of these
registers is described in this section. Address 0Fh has a device identification register (IDR). The four MSBs of this read-only register are fixed to 1 0 0 1, indicating that a DS21Q58 E1 quad transceiver is present. The lower 4 bits of the IDR are used to identify the
revision of the device. This register exists in Transceiver 1 only (TS0, TS1 = 0).
The factory in testing the DS21Q58 uses the test register at addresses 1E. On power-up, the test register should
be set to 00h for the DS21Q58 to properly operate.
Register Name:
IDR Register Description:
Device Identification Register Register Address:
0F Hex Bit # 7 6 5 4 3 2 1 0
Name
DS21Q58 E1 Quad Transceiver
8.1 Power-Up Sequence On power-up and after the supplies are stable, the DS21Q58 should be configured for operation by writing to all the
internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (It takes the device about 40ms to recover from the LIRST bit being toggled.) After the SYSCLK input is stable, the
ESR bits (CCR4.5 and CCR4.6) should be toggled from 0 to 1 (this step can be skipped if the elastic store is
disabled).
Register Name:
RCR Register Description:
Receive Control Register Register Address:
10 Hex Bit # 7 6 5 4 3 2 1 0
Name RSMF
DS21Q58 E1 Quad Transceiver
Table 8-1. Sync/Resync Criteria Register Name:
TCR Register Description:
Transmit Control Register Register Address:
11 Hex Bit # 7 6 5 4 3 2 1 0
Name IFSS
Note: See Figure 24-9 for more details about how the transmit control register affects DS21Q58 operation. DS21Q58 E1 Quad Transceiver
Register Name:
CCR1 Register Description:
Common Control Register 1 Register Address:
12 Hex Bit # 7 6 5 4 3 2 1 0
Name FLB
DS21Q58 E1 Quad Transceiver
8.2 Framer Loopback When CCR1.7 is set to 1, the DS21Q58 enters a framer loopback (FLB) mode (Figure 3-1). This loopback is useful
in testing and debugging applications. In FLB mode, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TTIP and TRING. 2) The RCLK output is replaced with the TCLK input.
Register Name:
CCR2 Register Description:
Common Control Register 2 Register Address:
13 Hex Bit # 7 6 5 4 3 2 1 0 Name ECUS
DS21Q58 E1 Quad Transceiver
8.3 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). If one (or more) of these conditions is present, the framer forces an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the receiver is monitored to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-
receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If one (or more) of these conditions is present, the device transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications, and a constant remote alarm is transmitted if the
DS21Q58 cannot find CRC4 multiframe synchronization within 400ms as per G.706. Register Name:
CCR3 Register Description:
Common Control Register Register Address:
14 Hex Bit # 7 6 5 4 3 2 1 0
Name
8.4 Remote Loopback When CCR4.7 is set to 1, the DS21Q58 is forced into remote loopback (RLB) mode. In this loopback, data input through the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins. Data continues to pass
through the DS21Q58s receive framer as it would normally and the data from the transmit formatter is ignored (Figure 3-1).
DS21Q58 E1 Quad Transceiver
8.5 Local Loopback When CCR4.6 is set to 1, the DS21Q58 is forced into local loopback (LLB) mode. In this loopback, data continues
to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted. Data in this loopback passes through the jitter attenuator (Figure 3-1). Register Name:
CCR4 Register Description:
Common Control Register 4 Register Address:
15 Hex Bit # 7 6 5 4 3 2 1 0
Name
DS21Q58 E1 Quad Transceiver
Register Name:
CCR5 Register Description:
Common Control Register 5 Register Address:
16 Hex Bit # 7 6 5 4 3 2 1 0
Name
Table 8-2. G.703 Function DS21Q58 E1 Quad Transceiver
Register Name:
CCR6 Register Description:
Common Control Register 6 Register Address:
2F Hex Bit # 7 6 5 4 3 2 1 0
Name OTM1
Table 8-3. Output Modes DS21Q58 E1 Quad Transceiver
Register Name:
CCR7 Register Description:
Common Control Register 7 Register Address:
1F Hex Bit: 7 6 5 4 3 2 1 0
Name: N.M. = Not meaningful
DS21Q58 E1 Quad Transceiver
9. STATUS AND INFORMATION REGISTERS The DS21Q58 has a set of four registers that contain information about a framers real-time status. The registers
include status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers is set to 1.
All the bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are not latched, which means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, the bit remains set until
the user reads that bit. The bit is cleared when it is read and is not set again until the event has occurred again (or, in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set if the alarm is still present). The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the register
informs the framer which bits the user wishes to read and have cleared. The user writes a byte to one of these registers with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to
obtain the latest information on. When a 1 is written to a bit location, the read register updates with the latest information. When a 0 is written to a bit position, the read register does not update and the previous value is held. write to the status and information registers is immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written, and this value should be written back into
the same register to ensure the bit clears. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access through the parallel port. This write-read-write
scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q58 with higher-order software languages. The SSR register operates differently than the other three. It is a read-only register and reports the status of the
synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt through the INT output pin. Each of the alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through
interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2).
The interrupts caused by alarms in SR1 (RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, and RCMF). The alarm-
caused interrupts force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 9-1). The INT pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.
The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high () when the user reads the event bit that caused the interrupt to occur. Furthermore, some event-based interrupts occur continuously
as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF, RCMF). Other event-based interrupts force
the INT pin low only once when the event is first detected (LOTC, PRSBD, RDMA, RSA1, RSA0), that is, the PRBSD interrupt fires once when the receiver detects the PRBS pattern. If the receiver continues to receive the
PRBS pattern, no more interrupts are fired. If the receiver then detects that PRBS is no longer being sent, it resets and, when it receives the PRBS pattern again, another interrupt is fired.
DS21Q58 E1 Quad Transceiver
9.1 Interrupt Handling The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of
the unused addresses such as 0Ch, 0Dh, or 0Eh in any port.
Bit # 7 6 5 4 3 2 1 0 Name
Register Name:
RIR Register Description:
Receive Information Register Register Address:
08 Hex Bit # 7 6 5 4 3 2 1 0
Name
DS21Q58 E1 Quad Transceiver
Register Name: SSR
Register Description: Synchronizer Status Register Register Address: 09 Hex Bit # 7 6 5 4 3 2 1 0
Name
9.2 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared
when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync
counter rolls over.
Table 9-1. Alarm Criteria
DS21Q58 E1 Quad Transceiver
Register Name: SR1
Register Description: Status Register 1 Register Address: 0A Hex Bit # 7 6 5 4 3 2 1 0
Name
DS21Q58 E1 Quad Transceiver
Register Name: IMR1
Register Description: Interrupt Mask Register 1 Register Address: 18 Hex Bit # 7 6 5 4 3 2 1 0
Name
DS21Q58 E1 Quad Transceiver
Register Name: SR2
Register Description: Status Register 2 Register Address: 0B Hex Bit # 7 6 5 4 3 2 1 0
Name RMF
DS21Q58 E1 Quad Transceiver
Register Name: IMR2
Register Description: Interrupt Mask Register 2 Register Address: 19 Hex Bit # 7 6 5 4 3 2 1 0
Name RMF
DS21Q58 E1 Quad Transceiver
10. ERROR COUNT REGISTERS
Each DS21Q58 transceiver contains a set of four counters that record bipolar (BPVs) or code violations (CVs),
errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E-bit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four
counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.7 = 1) as determined by the timer in status register 2 (SR2.4). Hence, these registers contain performance data from
either the previous second or the previous 62.5ms. The user can use the interrupt from the one-second timer to determine when to read these registers. The user has a full second (or 62.5ms) to read the counters before the
data is lost. The counters saturate at their respective maximum counts and do not roll over.
10.1 BPV or CV Counter
Violation count register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BPVs or CVs. If CCR2.6 = 0, the VCR counts BPVs. BPVs are defined as consecutive
marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver through CCR1.2, then HDB3 codewords are not counted as BPVs. If CCR2.6 = 1, the VCR counts CVs as defined in ITU O.161. CVs are
defined as consecutive BPVs of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times
and is not disabled by loss-of-sync conditions. The counter saturates at 65,535 and does not roll over. The bit-error rate on an E1 line would have to be greater than 10-2 before the VCR would saturate. Register Name: VCR1, VCR2
Register Description: Bipolar Violation Count Registers Register Address: 00 Hex, 01 Hex Bit # 7 6 5 4 3 2 1 0 Name
10.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 count in a
one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and
CRCCR2 have an alternate function.
Register Name: CRCCR1, CRCCR2 Register Description: CRC4 Count Registers
Register Address: 02 Hex, 03 Hex
Bit # 7 6 5 4 3 2 1 0 Name
DS21Q58 E1 Quad Transceiver
10.3 E-Bit/PRBS Bit-Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit
counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since
the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level.
Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This
pattern can be framed, unframed, or in any time slot. See Section 13 for more details.
Register Name: EBCR1, EBCR2
Register Description: E-Bit Count Registers
Register Address: 04 Hex, 05 Hex Bit # 7 6 5 4 3 2 1 0 Name
10.4 FAS Error Counter
FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors
are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot
saturate.
Register Name: FASCR1, FASCR2 Register Description: FAS Error Count Registers
Register Address: 06 Hex, 07 Hex
Bit # 7 6 5 4 3 2 1 0 Name
DS21Q58 E1 Quad Transceiver
11. SIGNALING OPERATION
Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these
registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter. The user can read what was written to the transmit signaling buffer by setting CCR6.5 = 1, then reading
SA1SA16. In most applications, however, CCR6.5 should be set = 0.
11.1 Receive Signaling
Signaling data is sampled from time slot 16 in the receive data stream and copied into the receive signaling buffers. The host can access the signaling data by reading SA1 through SA16. The signaling information in these registers
is always updated on multiframe boundaries. The SR2.7 bit in status register 2 can be used to alert the host that new signaling data is present in the receive signaling buffers. The host has 2ms to read the signaling buffers before
they are updated.
11.2 Transmit Signaling
Insertion of signaling data from the transmit signaling buffers is enabled by setting CCR6.3 = 1. Signaling data is
loaded into the transmit signaling buffers by writing the signaling data to SA1SA16. On multiframe boundaries, the contents of the transmit signaling buffer is loaded into a shift register for placement in the appropriate bit position in
the outgoing data stream. The user can use the transmit multiframe interrupt in status register 2 (SR2.5) to know when to update the signaling bits. The host has 2ms to update the signaling data. The user only needs to update
the signaling data that has changed since the last update.
11.3 CAS Operation
For CAS mode, the user must provide the CAS alignment pattern (four 0s in the upper nibble of TS16). Typically
this is done by setting the upper four bits of SA1 = 0. The lower four bits are alarm bits. The user only needs to update the appropriate channel associated signaling data in SA2SA16 on multiframe boundaries. Register Name: SA1 to SA16
Register Description: Signaling Registers
Register Address: 30h to 3Fh SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16
DS21Q58 E1 Quad Transceiver
12. DS0 MONITORING FUNCTION
Each DS21Q58 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the
receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0 to RCM4 bits in
the CCR4 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits appear in the transmit DS0 monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits appear in the
receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0
channel 15 in the receive direction needed to be monitored, then the following values would be programmed into CCR4 and CCR5: TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0
Register Name: CCR3 (Repeated here from Section 6 for convenience.)
Register Description: Common Control Register 3 Register Address: 14 Hex Bit # 7 6 5 4 3 2 1 0
Name
Register Name: TDS0M Register Description: Transmit DS0 Monitor Register
Register Address: 22 Hex
Bit # 7 6 5 4 3 2 1 0
Name
