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DS21Q55DK
Quad T1/E1/J1 Transceiver Design Kit Daughter Card
GENERAL DESCRIPTION The DS21Q55DK is an easy-to-use evaluation board
for the DS21Q55 quad T1/E1/J1 transceiver. The DS21Q55DK is intended to be used as a daughter
card with the DK101 motherboard or the DK2000 motherboard. The DS21Q55DK comes complete with
a DS21Q55 quad SCT, transformers, termination resistors, configuration switches, line-protection
circuitry, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and
Dallas’ ChipView software give point-and-click access to configuration and status registers from a
Windows�-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status. An on-board FPGA contains mux logic to connect framer
ports to one another or to the DK2000 in a variety of configurations.
Each DS21Q55DK is shipped with a free DK101 motherboard. For complex applications, the DK2000
high-performance demo kit motherboard can be purchased separately.
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
FEATURES ��Demonstrates Key Functions of DS21Q55 Quad T1/E1/J1 Transceiver
��Includes DS21Q55 Quad LIU, Transformers,
BNC, and RJ45 Network Connectors and Termination Passives
��Compatible with DK101 and DK2000 Demo Kit Motherboards
��DK101/DK2000 and ChipView Software Provide
Point-and-Click Access to the DS21Q55 Register Set
��All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
��Memory-Mapped FPGA Provides Flexible Clock/Data/Sync Connections Among Framer
Ports and DK2000 Motherboard
��LEDs for Loss-of-Signal and Interrupt Status
��Easy-to-Read Silk-Screen Labels Identify the Signals Associated with All Connectors, Jumpers and LEDs
��Network Interface Protection for Overvoltage and
Overcurrent Events
DESIGN KIT CONTENTS DS21Q55DK Design Kit Daughter Card DK101 Low-Cost Motherboard
CD-ROM ChipView Software
DS21Q55DK Data Sheet DK101 Data Sheet
DS21Q55 Data Sheet DS21Q55 Errata Sheet
DS21Q55DK
Quad T1/E1/J1 Transceiver Design Kit
Daughter Card
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
COMPONENT LIST
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
BOARD FLOORPLAN
ERRATA Connector J1 has silk-screen mislabeled such that the text TMS and TCK should be swapped. Worded
differently, TCK belongs to pin 7 and TMS belongs to pin 9. Switches SW1 to SW4 are missing silk screen to indicate which side is grounded. Sliding the switch toward the BNC grounds the BNC shell (E1 mode). For T1 mode the switch should be slid away from the BNC.
BASIC OPERATION This design kit relies upon several supporting files, which are available for downloading on our website at /telecom. See the DS21Q55DK QuickView data sheet for these files.
Hardware Configuration
Using the DK101 Processor Board: Connect the daughter card to the DK101 processor board. Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is unused. Additionally, the TIM 5V supply headers are unused.) All processor board DIP-switch settings should be in the ON position with exception of the flash-programming
switch, which should be OFF. From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs �
ChipView � ChipView.
Using the DK2000 Processor Board: Connect the daughter card to the DK2000 processor board. Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected to connector J2. From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs �
ChipView � ChipView.
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
General Upon power-up, the RLOS LEDs (green) will not be lit, the INT LED (red) will not be lit, but the FPGA status LED (green) will be lit. When operating in E1 mode, slide SW1SW4 such that the BNC shell is grounded (to the left, as shown in the
board floorplan). When operating in T1 mode, ensure that SW1SW4 are slid to the right as shown in the board floorplan.
Miscellaneous Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA, which is on the DS21Q55 daughter card. The definition file for this FPGA is named DS21Q55DC_FPGA.def. The definitions are located on page 6. A
drop-down menu on the top of the screen allows for switching between definition files. All files referenced above are available for download as described in the section marked BASIC OPERATION
QUICK SETUP (DEMO MODE) The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Demo Mode. The program will request a configuration file, select among the displayed files
(DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg). The Demo Mode screen will appear. Upon external loopback, the LOS and OOF indicators will extinguish. Note: Demo Mode interacts with the device driver, which is resident in the DK101/DK2000 firmware. The current implementation of this driver is for one device. As such, the demo mode will only interact with Port 1.
With minor changes, the device driver is extendible to N devices.
QUICK SETUP (REGISTER VIEW) The PC will load ChipView offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View. The program will request a definition file. Select DS21Q55DC_FPGA.def; through the links section this will
also load DS21Q55DC.def. The Register View Screen will appear, showing the register names, acronyms, and values for the DS21Q55 Predefined register settings for several functions are available as initialization files. INI files are loaded by selecting the menu File�Reg Ini File�Load Ini File Load the INI file DS21Q55_T1_BERT_ESF.ini After loading the INI file, the following may be observed: The RLOS LEDs (green) light upon external loopback. All four ports of the DS2Q155 begin transmitting a Daly pattern. When external loopback is applied, the
BERT bit count registers BBC13 and BEC13 may be updated by clearing and setting BC1.LC and clicking the Read All button.
DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
ADDRESS MAP DK101 Daughter Card address space begins at 0x81000000.
DK2000 Daughter Card address space begins at: 0x30000000 for slot 0
0x40000000 for slot 1 0x50000000 for slot 2
0x60000000 for slot 3
All offsets given below are relative to the beginning of the daughter card address space (shown above).
Table 1. Daughter Card Address Map Registers in the FPGA may be easily modified using the ChipView host-based user-interface software along with
the definition file named DS21Q55DC_FPGA.def.
