DS21Q50LN ,Quad E1 TransceiverFEATURES The DS21Q50 E1 quad transceiver contains all the Four Complete E1 (CEPT) PCM-30/ISDN-PRI ..
DS21Q55 ,Quad T1/E1/J1 TransceiverAPPLICATIONS: Complete T1 (DS1)/ISDN–PRI/J1 transceiver § Routers functionality § Channel Service U ..
DS21Q552 ,Quad T1 Transceiver (5V/3.3V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q554 ,Quad E1 Transceiver (5V/3.3V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q554 ,Quad E1 Transceiver (5V/3.3V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q554B+ ,Quad T1/E1 Transceiver (3.3V, 5.0V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q50L-DS21Q50LN
Quad E1 Transceiver
GENERAL DESCRIPTION The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines.
The on-board clock/data recovery circuitry coverts
the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1
22AWG (0.6mm) twisted-pair cables from 0km to
over 2km in length. The device can generate the
necessary G.703 waveshapes for both 75� coax and
120� twisted-pair cables. The on-board jitter attenuators (selectable to either 32 bits or 128 bits)
can be placed in either the transmit or receive data
paths. The framers locate the frame and multiframe boundaries and monitor the data streams for alarms.
The device contains a set of internal registers, from
which the user can access and control the operation of the unit by the parallel control port or serial port.
The device fully meets all the latest E1 specifications
including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431 ETS 300 011, ETS 300 233, and ETS 300
166 as well as CTR12 and CTR4.
APPLICATIONS DSLAMs
Routers
IMA and WAN Equipment
PIN CONFIGURATION
FEATURES ��Four Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceivers Long-Haul and Short-Haul Line Interfaces 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Frames to FAS, CAS, CCS, and CRC4 Formats 4MHz/8MHz/16MHz Clock Synthesizer Flexible System Clock with Automatic Source
Switching on Loss-of-Clock Source Two-Frame Elastic-Store Slip Buffer on the
Receive Side Interleaving PCM Bus Operation Up to
16.384MHz Configurable Parallel and Serial Port Operation Detects and Generates Remote and AIS Alarms Fully Independent Transmit and Receive
Functionality Four Separate Loopback Functions PRBS Generation/Detection/Error Counting 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits Eight Additional User-Configurable Output Pins
��100-Pin, 14mm x 14mmLQFP Package
ORDERING INFORMATION
DS21Q50
DS21Q50
TABLE OF CONTENTS
1. INTRODUCTION...............................................................................................................................6
2. PIN DESCRIPTION............................................................................................................................9 2.1 PIN FUNCTION DESCRIPTION.........................................................................................................15
2.1.1 System (Backplane) Interface Pins.......................................................................................................15 2.1.2 Alternate Jitter Attenuator....................................................................................................................16
2.1.3 Clock Synthesizer..................................................................................................................................16
2.1.4 Parallel Port Control Pins....................................................................................................................16 2.1.5 Serial Port Control Pins.......................................................................................................................17
2.1.6 Line Interface Pins................................................................................................................................18
2.1.7 Supply Pins...........................................................................................................................................18
3. HOST INTERFACE PORT..............................................................................................................20 3.1 PARALLEL PORT OPERATION........................................................................................................20
3.2 SERIAL PORT OPERATION.............................................................................................................20 3.3 REGISTER MAP.............................................................................................................................23
4. CONTROL, ID, AND TEST REGISTERS.....................................................................................24 4.1 POWER-UP SEQUENCE..................................................................................................................25
4.2 FRAMER LOOPBACK.....................................................................................................................28
4.3 AUTOMATIC ALARM GENERATION...............................................................................................29
4.4 REMOTE LOOPBACK.....................................................................................................................30 4.5 LOCAL LOOPBACK........................................................................................................................30
5. STATUS AND INFORMATION REGISTERS.............................................................................32 5.1 CRC4 SYNC COUNTER.................................................................................................................34
6. ERROR COUNT REGISTERS........................................................................................................39 6.1 BPV OR CODE VIOLATION COUNTER...........................................................................................39
6.2 CRC4 ERROR COUNTER...............................................................................................................40
6.3 E-BIT/PRBS BIT ERROR COUNTER..............................................................................................40
6.4 FAS ERROR COUNTER..................................................................................................................41
7. DS0 MONITORING FUNCTION...................................................................................................42
8. PRBS GENERATION AND DETECTION....................................................................................45
9. SYSTEM CLOCK INTERFACE.....................................................................................................46
10. TRANSMIT CLOCK SOURCE......................................................................................................47
11. IDLE CODE INSERTION................................................................................................................48
12. PER-CHANNEL LOOPBACK........................................................................................................49
13. ELASTIC STORE OPERATION....................................................................................................49
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION.....................................50
15. USER-CONFIGURABLE OUTPUTS.............................................................................................53
16. LINE INTERFACE UNIT................................................................................................................56 16.1 RECEIVE CLOCK AND DATA RECOVERY.......................................................................................56
16.2 TERMINATION...............................................................................................................................57 16.3 RECEIVE MONITOR MODE............................................................................................................57
DS21Q50
17. CMI (CODE MARK INVERSION).................................................................................................64
18. INTERLEAVED PCM BUS OPERATION....................................................................................66
19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68 19.1 RECEIVE TIMING DIAGRAMS........................................................................................................68 19.2 TRANSMIT TIMING DIAGRAMS......................................................................................................70
20. OPERATING PARAMETERS........................................................................................................74
21. AC TIMING PARAMETERS AND DIAGRAMS.........................................................................75 21.1 MULTIPLEXED BUS AC CHARACTERISTICS..................................................................................75 21.2 NONMULTIPLEXED BUS AC CHARACTERISTICS...........................................................................78
21.3 SERIAL PORT................................................................................................................................81
21.4 RECEIVE AC CHARACTERISTICS...................................................................................................82
21.5 TRANSMIT AC CHARACTERISTICS................................................................................................84
21.6 SPECIAL MODES AC CHARACTERISTICS.......................................................................................86
22. PACKAGE INFORMATION...........................................................................................................87
DS21Q50
LIST OF FIGURES Figure 1-1. Block Diagram............................................................................................................................8
Figure 3-1. Serial Port Operation Mode 1...................................................................................................21
Figure 3-2. Serial Port Operation Mode 2...................................................................................................21
Figure 3-3. Serial Port Operation Mode 3...................................................................................................22
Figure 3-4. Serial Port Operation Mode 4...................................................................................................22
Figure 16-1. Typical Monitor Port Application...........................................................................................57
Figure 16-2. External Analog Connections (Basic Configuration).............................................................60
Figure 16-3. External Analog Connections (Protected Interface)...............................................................60
Figure 16-4. Transmit Waveform Template................................................................................................61
Figure 16-5. Jitter Tolerance........................................................................................................................63
Figure 16-6. Jitter Attenuation.....................................................................................................................63
Figure 17-1. CMI Coding............................................................................................................................64
Figure 17-2. CMI Code Violation Example................................................................................................65
Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines)............................67
Figure 19-1. Receive Frame and Multiframe Timing..................................................................................68
Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)......................................................68
Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled).......................................................69
Figure 19-4. Receive Interleave Bus Operation..........................................................................................69
Figure 19-5. Transmit Frame and Multiframe Timing................................................................................70
Figure 19-6. Transmit Boundary Timing.....................................................................................................70
Figure 19-7. Transmit Interleave Bus Operation.........................................................................................71
Figure 19-8. Framer Synchronization Flowchart.........................................................................................72
Figure 19-9. Transmit Data Flow................................................................................................................73
Figure 21-1. Intel Bus Read AC Timing (PBTS = 0)..................................................................................76
Figure 21-2. Intel Bus Write Timing (PBTS = 0)........................................................................................76
Figure 21-3. Motorola Bus AC Timing (PBTS = 1)....................................................................................77
Figure 21-4. Intel Bus Read Timing (PBTS = 0).........................................................................................79
Figure 21-5. Intel Bus Write Timing (PBTS = 0)........................................................................................79
Figure 21-6. Motorola Bus Read Timing (PBTS = 1).................................................................................80
Figure 21-7. Motorola Bus Write Timing (PBTS = 1)................................................................................80
Figure 21-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0)..............................................................................81
Figure 21-9. Receive AC Timing (Receive Elastic Store Disabled)...........................................................82
Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled)..........................................................83
Figure 21-11. Transmit AC Timing (IBO Disabled)...................................................................................85
Figure 21-12. Transmit AC Timing (IBO Enabled)....................................................................................85
Figure 21-13. NRZ Input AC Timing..........................................................................................................86
DS21Q50
LIST OF TABLES Table 2-1. Pin Assignments (by Function)....................................................................................................9
Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12
Table 3-1. Bus Mode Select.........................................................................................................................20
Table 3-2. Register Map..............................................................................................................................23
Table 4-1. Sync/Resync Criteria..................................................................................................................26
Table 5-1. Alarm Criteria............................................................................................................................34
Table 8-1. Transmit PRBS Mode Select......................................................................................................45
Table 8-2. Receive PRBS Mode Select.......................................................................................................45
Table 9-1. Master Port Selection.................................................................................................................47
Table 9-2. Synthesizer Output Select..........................................................................................................47
Table 15-1. OUTA and OUTB Function Select..........................................................................................55
Table 16-1. Receive Monitor Mode Gain....................................................................................................57
Table 16-2. Monitor Mode Settings.............................................................................................................58
Table 16-3. Line Build-Out Select in LICR................................................................................................59
Table 16-4. Transformer Specifications......................................................................................................59
Table 18-1. IBO Device Assignment...........................................................................................................66
Table 18-2. IBO System Clock Select.........................................................................................................67
DS21Q50
1. INTRODUCTION The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included
for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The
IBO allows up to eight E1 data streams to be multiplexed onto a single high-speed PCM bus without
additional external logic. The system clock synthesizer feature allows any of the E1 lines to be selected as the master source of clock for the system and for all the transmitters. This is also accomplished without
the need of external logic. Each of the four transceivers has a clock and data jitter attenuator that can be
assigned to either the transmit or receive path. In addition there is a single, undedicated clock jitter
attenuator that can be hardware configured as the user needs. Each transceiver also contains a PRBS
pattern generator and detector. Figure 18-1 shows a simplified typical application that terminates eight E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The
16.384MHz system clock is derived and phased-locked to one of the eight E1 lines. On the receive side of
each port, an elastic store provides logical management of any slip conditions because of the
asynchronous relationship of the eight E1 lines. In this application, all eight transmitters are timed to the
selected E1 line.
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS21Q50 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive framer
locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms
including, carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input. The clock applied
at the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The
transmit framer is independent from the receive in both the clock requirements and characteristics. The
transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
DS21Q50
Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125µs frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first.
These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is
identical to channel 1; time slot 1 is identical to channel 2; and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8. Bit number 1, MSB, is transmitted first. Bit number 8, the LSB,
is transmitted last. The term locked is used to refer to two clock signals that are phase-locked or
frequency-locked or derived from a common clock (i.e., a 8.192MHz clock can be locked to a 2.048MHz
clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations
are used:
DS21Q50
Figure 1-1. Block Diagram
DS21Q50
2. PIN DESCRIPTION
Table 2-1. Pin Assignments (by Function)
DS21Q50
DS21Q50
Note: EQVSS lines are tied to RVSS lines in the 100-pin LQFP package. DS21Q50
Table 2-2. Pin Assignment (by LQFP Pin Number)
DS21Q50
DS21Q50
Note: EQVSS lines are tied to RVSS lines in the 100-pin LQFP package. DS21Q50
2.1 Pin Function Description
2.1.1 System (Backplane) Interface Pins Signal Name:
TCLK Signal Description:
Transmit Clock Signal Type:
Input A 2.048MHz primary clock. Used to clock data through the transmit formatter. Signal Name:
TSER Signal Description:
Transmit Serial Data Signal Type:
Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when IBO disabled. Sampled on the falling edge
of SYSCLK when the IBO function is enabled. Signal Name:
TSYNC Signal Description:
Transmit Sync Signal Type:
Input/Output As an input, pulse at this pin establishes either frame or multiframe boundaries for the transmitter. As an output,
can be programmed to output either a frame or multiframe pulse. Signal Name:
RSER Signal Description:
Receive Serial Data Signal Type:
Output Received NRZ serial data. Updated on rising edges of RCLK when the receive elastic store is disabled. Updated on
the rising edges of SYSCLK when the receive elastic store is enabled.
Signal Name:
RSYNC Signal Description:
Receive Sync Signal Type:
Input/Output An extracted pulse, one RCLK wide, is output at this pin, which identifies either frame or CAS/CRC4 multiframe
boundaries. If the receive elastic store is enabled, then this pin can be enabled to be an input at which a frame boundary pulse synchronous with SYSCLK is applied.
Signal Name:
SYSCLK Signal Description:
System Clock Signal Type:
Input 2.048MHz clock that is used to clock data out of the receive elastic store. When the IBO is enabled this can be a 4.096MHz, 8.192MHz, or 16.384MHz clock.
Signal Name:
OUTA Signal Description:
User Selectable Output A Signal Type:
Output A multifunction pin that can be programmed by the host to output various alarms, clocks or data, or used to control
external circuitry. Signal Name:
OUTB Signal Description:
User Selectable Output B Signal Type:
Output A multifunction pin that can be programmed by the host to output various alarms, clocks, or data, or used to control
external circuitry.
DS21Q50
2.1.2 Alternate Jitter Attenuator Signal Name:
AJACKI Signal Description:
Alternate Jitter Attenuator Clock Input Signal Type:
Input Clock input to alternate jitter attenuator. Signal Name:
AJACKO Signal Description:
Alternate Jitter Attenuator Clock Output Signal Type:
Output Clock output of alternate jitter attenuator.
2.1.3 Clock Synthesizer Signal Name:
4/8/16MCK Signal Description:
4.096MHz/8.192MHz/16.384MHz Clock Output Signal Type:
Output A 4.096MHz, 8.192MHz, or 16.384MHz clock output that is referenced to one of the four recovered line clocks (RCLKs) or to an external 2.048MHz reference.
Signal Name:
REFCLK Signal Description:
Reference Clock Signal Type:
Input/Output Can be configured as an output to source a 2.048MHz reference clock or as an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
2.1.4 Parallel Port Control Pins Signal Name: INT Signal Description:
Interrupt Signal Type:
Output Flags host controller during conditions and change of conditions defined in status registers 1 and 2 and the HDLC
status register. Active-low, open-drain output.
Signal Name:
BTS0 Signal Description:
Bus Type Select Bit 0 Signal Type:
Input Used with BTS1 to select between muxed, nonmuxed, serial bus operation, and output high-Z mode. Signal Name:
BTS1 Signal Description:
Bus Type Select Bit 0 Signal Type:
Input Used with BTS0 to select between muxed, nonmuxed, serial bus operation, and output high-Z mode.
Signal Name:
TS0 Signal Description:
Transceiver Select Bit 0 Signal Type:
Input Used with TS1 to select one of four transceivers.
Signal Name:
TS1 Signal Description:
Transceiver Select Bit 0
DS21Q50
Signal Name: PBTS
Signal Description: Parallel Bus Type Select Signal Type: Input
Used to select between Motorola and Intel parallel bus types.
Signal Name: AD0 to AD7/SDO
Signal Description: Data Bus or Address/Data Bus [D0 to D6]
Data Bus or Address/Data Bus [D7]/Serial Port Output Signal Type: Input/Output
In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed address/data bus.
Signal Name: A0 to A4 Signal Description: Address Bus Signal Type: Input
In nonmultiplexed bus operation, this serves as the address bus. In multiplexed bus operation, these pins are not used and should be wired low.
Signal Name: RD(DS)/SCLK Signal Description: Read InputData Strobe/Serial Port Clock
Signal Type: Input
RD and DS are active-low signals. DS active HIGH when in multiplexed mode. See bus-timing diagrams.
Signal Name: CS Signal Description: Chip Select
Signal Type: Input Must be low to read or write to the device. CS is an active low signal.
Signal Name: ALE (AS)/A5 Signal Description: Address Latch Enable (Address Strobe) or A6 Signal Type: Input
In nonmultiplexed bus operation, this serves as the upper address bit. In multiplexed bus operation, this serves to demultiplex the bus on a positive-going edge.
Signal Name: WR (R/W)/SDI Signal Description: Write Input (Read/Write)/Serial Port Data Input Signal Type: Input
WR is an active-low signal.
2.1.5 Serial Port Control Pins
Signal Name: SDO Signal Description: Serial Port Output Signal Type: Output
Data at this output can be updated on the rising or falling edge of SCLK.
Signal Name: SDI
Signal Description: Serial Port Data Input Signal Type: Input Data at this input can be sampled on the rising or falling edge of SCLK.
DS21Q50
Signal Name: ICES
Signal Description: Input Clock Edge Select
Signal Type: Input Used to select which SCLK clock edge samples data at SDI. Signal Name: OCES Signal Description: Output Clock Edge Select
Signal Type: Input Used to select which SCLK clock edge updates data at SDO.
Signal Name: SCLK Signal Description: Serial Port Clock Signal Type: Input
Used to clock data into and out of the serial port.
2.1.6 Line Interface Pins Signal Name: MCLK
Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation.
Signal Name: RTIP and RRING
Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the E1 line. See Section
16 for details.
Signal Name: TTIP and TRING
Signal Description: Transmit Tip and Ring Signal Type: Output
Analog line driver outputs. These pins connect through a 1:2 step-up transformer to the E1 line. See Section 16 for details.
2.1.7 Supply Pins Signal Name: DVDD
Signal Description: Digital Positive Supply Signal Type: Supply
3.3V ±5%. Should be tied to the RVDD and TVDD pins. Signal Name: RVDD
Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply
Signal Type: Supply 3.3V ±5%. Should be tied to the RVDD and DVDD pins.
DS21Q50
Signal Name: DVSS
Signal Description: Digital Signal Ground
Signal Type: Supply 0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground
Signal Type: Supply 0V. Should be tied to DVSS and TVSS.
Signal Name: EQVSS Signal Description: Receiver Equalizer Analog Signal Ground Signal Type: Supply
0V. Should be tied to DVSS and TVSS. Not accessible in the 100-pin LQFP package.
Signal Name: TVSS
Signal Description: Transmit Analog Signal Ground Signal Type: Supply
0V. Should be tied to DVSS and RVSS.
DS21Q50
3. HOST INTERFACE PORT
The DS21Q50 is controlled either through a nonmultiplexed bus, a multiplexed bus, or serial interface
bus by an external microcontroller or microprocessor. The device can operate with either Intel or
Motorola bus timing configurations. See Table 3-1 for a description of the bus configurations. All
Motorola bus signals are listed in parentheses (). See Functional Timing Diagrams in Section 19 for more details.
Table 3-1. Bus Mode Select
3.1 Parallel Port Operation
When using the parallel interface on the DS21Q50 (BTS1 = 0) the user has the option for either
multiplexed bus operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q50 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is
wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus signals
are listed in parentheses (). See the timing diagrams in AC Timing Parameters and Diagrams in
Section 21 for more details.
3.2 Serial Port Operation Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port
read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or
writes by the host. See Section 21 for the AC timing of the serial port. All serial port accesses are LSB
first. See Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 for more details. Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next five bits identify the register address. The next bit is reserved
and must be set to 0 for proper operation. The last bit (MSB) of the address/command byte enables the
burst mode when set to 1. The burst mode causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS input low. When input clock-edge select (ICES) is low,
input data is latched on the rising edge of SCLK. When ICES is high, input data is latched on the falling
edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of
SCLK. When OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is three-stated when CS is high.
DS21Q50
Figure 3-1. Serial Port Operation Mode 1
Figure 3-2. Serial Port Operation Mode 2
DS21Q50
Figure 3-3. Serial Port Operation Mode 3 Figure 3-4. Serial Port Operation Mode 4
DS21Q50
3.3 Register Map
Table 3-2. Register Map
DS21Q50 Note 1: The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0).
Note 2: Only the factory uses the test registers; these registers must be cleared (set to all zeros) on power-up initialization to
ensure proper operation.
4. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21Q50 is configured through a set of seven control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the device has been
initialized, the control registers only need to be accessed when there is a change in the system
configuration. There is one receive control register (RCR), one transmit control register (TCR), and five common control registers (CCR1 to CCR5). Each of these registers is described in this section.
There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed
to 1, indicating that an E1 quad transceiver is present. The next three MSBs are reserved for future use. The lower 4 bits of the device ID register are used to identify the revision of the device. This register
exists in Transceiver 1 only (TS0, TS1 = 0).
The test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On
power-up, the test registers should be set to 00h in order for the DS21Q50 to operate properly.
Register Name: IDR Register Description: Device Identification Register
Register Address: 0F Hex Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
4.1 Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by
writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of
the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to
1 to reset the line interface circuitry (it takes the device about 40ms to recover from the LIRST bit being toggled). Finally, after the SYSCLK input is stable, the ESR bits (CCR4.5 and CCR4.6) should be
toggled from a 0 to 1 (this step can be skipped if the elastic store is disabled).
Register Name: RCR
Register Description: Receive Control Register Register Address: 10 Hex
Bit 7 6 5 4 3 2 1 0
Name RSMF
DS21Q50
Table 4-1. Sync/Resync Criteria
Register Name: TCR Register Description: Transmit Control Register
Register Address: 11 Hex Bit 7 6 5 4 3 2 1 0
Name IFSS
DS21Q50
Register Name: CCR1
Register Description: Common Control Register 1
Register Address: 12 Hex
Bit 7 6 5 4 3 2 1 0
Name FLB
DS21Q50
4.2 Framer Loopback
When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode (Figure 1-1). This
loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter
back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TTIP and TRING.
2) The RCLK output is replaced with the TCLK input.
Register Name: CCR2 Register Description: Common Control Register 2 Register Address: 13 Hex Bit 7 6 5 4 3 2 1 0
Name RCUS
DS21Q50
4.3 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS
generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the
following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or
loss-of-receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer forces an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive to determine if
any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones)
reception, or loss-of-receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions
is present, the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications
and a constant remote alarm is transmitted if the DS21Q50 cannot find CRC4 multiframe synchronization
within 400ms as per G.706. Register Name: CCR3 Register Description: Common Control Register
Register Address: 14 Hex Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
4.4 Remote Loopback
When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data
input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues
to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit
formatter is ignored (Figure 1-1).
4.5 Local Loopback
When CCR4.6 is set to 1, the DS21Q50 is forced into local loopback (LLB). In this loopback, data
continues to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data
being transmitted. Data in this loopback passes through the jitter attenuator (Figure 1-1).
Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 15 Hex Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
Register Name: CCR5
Register Description: Common Control Register 5
Register Address: 16 Hex
Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
5. STATUS AND INFORMATION REGISTERS
A set of four registersstatus register 1 (SR1), status register 2 (SR2), receive information register (RIR),
and synchronizer status register (SSR)contains information about the DS21Q50 framers real-time
status
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers sets to 1. The bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are
not latched. This means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, it
remains set until the user reads that bit. The bit is cleared when it is read and it is not set again until the
event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set
if the alarm is still present).
The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the
register informs the framer which bits the user wishes to read and have cleared. The user writes a byte to
one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he
or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read
register is updated with the latest information. When a 0 is written to a bit position, the read register is not updated and the previous value is held. A write to the status and information registers is immediately
followed by a read of the same register. The read result should be logically ANDed with the mask byte
that was just written and this value should be written back into the same register to ensure that bit clears.
This second write step is necessary because the alarms and events in the status registers occur
asynchronously in respect to their access through the parallel port. The write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other
bits in the register. This operation is key in controlling the DS21Q50 with higher order software
languages.
The SSR register operates differently than the other three. It is a read-only register and reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write.
The SR1and SR2 registers can initiate a hardware interrupt through the INT output pin. Each of the
alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through the
interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2).
The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC,
TAF, LOTC, and RCMF). The alarm-caused interrupts force the INT pin low whenever the alarm
changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 5-1). The
INT pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that
caused the interrupt to occur even if the alarm is still present.
The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high ()
when the user reads the event bit that caused the interrupt to occur. Furthermore, some event-based
interrupts occur continuously as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF,
RCMF). Other event-based interrupts force the INT pin low only once when the event is first detected
(LOTC, PRSBD, RDMA, RSA1, RSA0), i.e., the PRBSD interrupt fires once when the receiver detects the PRBS pattern. If the receiver continues to receive the PRBS pattern, no more interrupts fire. If the
receiver then detects that PRBS is no longer being sent, the receiver resets and when it receives the PRBS
DS21Q50
Register Name: RIR
Register Description: Receive Information Register
Register Address: 08 Hex
Bit 7 6 5 4 3 2 1 0
Name RGM1
LEVEL INDICATION
DS21Q50
Register Name: SSR
Register Description: Synchronizer Status Register
Register Address: 09 Hex
Bit 7 6 5 4 3 2 1 0
Name
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. Disabling the
CRC4 mode (CCR1.0 = 0) can also clear the counter. This counter determines the time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the
CRC4 level cannot be obtained within 400ms, the search should be abandoned and proper action taken.
The CRC4 sync counter rolls over.
Table 5-1. Alarm Criteria
DS21Q50
Register Name: SR1
Register Description: Status Register 1
Register Address: 0A Hex
Bit 7 6 5 4 3 2 1 0
Name RSA1
DS21Q50
Register Name: IMR1
Register Description: Interrupt Mask Register 1
Register Address: 18 Hex
Bit 7 6 5 4 3 2 1 0
Name RSA1
DS21Q50
Register Name: SR2
Register Description: Status Register 2
Register Address: 0B Hex
Bit 7 6 5 4 3 2 1 0
Name RMF
DS21Q50
Register Name: IMR2
Register Description: Interrupt Mask Register 2
Register Address: 19 Hex
Bit 7 6 5 4 3 2 1 0
Name RMF
DS21Q50
6. ERROR COUNT REGISTERS
A set of four counters in each transceiver of the DS21Q50 record bipolar (BPV) or code violations (CV),
errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E-
bit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of
these four counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.7 = 1), as determined by the timer in status register 2 (SR2.4). Hence, these registers
contain performance data from either the previous second or the previous 62.5ms. The user can use the
interrupt from the one-second timer to determine when to read these registers. The user has a full second
(or 62.5ms) to read the counters before the data is lost. The counters saturate at their respective maximum
counts and do not roll over.
6.1 BPV or Code Violation Counter
Violation count register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either BPVs or CVs. If CCR2.6 = 0, the VCR counts BPVs. BPVs are
defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver
through CCR1.2, HDB3 codewords are not counted as BPVs. If CCR2.6 = 1, the VCR counts CVs, as defined in ITU O.161. CVs are defined as consecutive bipolar violations of the same polarity. In most
applications, the framer should be programmed to count BPVs when receiving AMI code and to count
CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss-of-sync
conditions. The counter saturates at 65,535 and does not roll over. The bit error rate on an E1 line would
have to be greater than 10-2 before the VCR would saturate.
Register Name: VCR1, VCR2 Register Description: Bipolar Violation Count Registers
Register Address: 00 Hex, 01 Hex
Bit 7 6 5 4 3 2 1 0
Name
Name
DS21Q50
6.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word
of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the
maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is
disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and CRCCR2 have alternate functions.
Register Name: CRCCR1, CRCCR2
Register Description: CRC4 Count Registers Register Address: 02 Hex, 03 Hex
Bit 7 6 5 4 3 2 1 0
Name
Name
6.3 E-Bit/PRBS Bit Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a
16-bit counter that records far-end block errors (FEBE), as reported in the first bit of frames 13 and 15 on
E1 lines running with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues
to count if loss-of-multiframe sync occurs at the CAS level. Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function
is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the
PRBS pattern. This pattern can be framed, unframed, or in any time slot. See Section 8 for more details.
Register Name: EBCR1, EBCR2
Register Description: E-Bit Count Registers Register Address: 04 Hex, 05 Hex Bit 7 6 5 4 3 2 1 0
Name
Name
DS21Q50
6.4 FAS Error Counter
FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of
a 16-bit counter that records word errors in the frame alignment signal (FAS) in time slot 0. This counter
is disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS-word error count in a one-second period is 4000, this counter cannot saturate.
Register Name: FASCR1, FASCR2
Register Description: FAS Error Count Registers Register Address: 06 Hex, 07 Hex
Bit 7 6 5 4 3 2 1 0
Name
Name
DS21Q50
7. DS0 MONITORING FUNCTION
Each DS21Q50 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0
channel in the receive direction at the same time. In the transmit direction, the user determines which
channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the
receive direction, the RCM0RCM4 bits in the CCR4 register need to be properly set. The DS0 channel pointed to by the TCM0TCM4 bits appear in the transmit DS0 monitor (TDS0M) register; the DS0
channel pointed to by the RCM0RCM4 bits appear in the receive DS0 (RDS0M) register. The TCM4
TCM0 and RCM4RCM0 bits should be programmed with the decimal decode of the appropriate E1
channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive
direction need to be monitored, the following values are programmed into CCR4 and CCR5:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0
Register Name: CCR3 (Repeated here from Section 3 for convenience.)
Register Description: Common Control Register 3 Register Address: 14 Hex
Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
Register Name: TDS0M
Register Description: Transmit Ds0 Monitor Register
Register Address: 22 Hex
Bit 7 6 5 4 3 2 1 0
Name
Register Name: CCR4 (Repeated here from Section 3 for convenience.) Register Description: Common Control Register 4
Register Address: 15 Hex Bit 7 6 5 4 3 2 1 0
Name
DS21Q50
Register Name: RDS0M
Register Description: Receive Ds0 Monitor Register
Register Address: 2A Hex
Bit 7 6 5 4 3 2 1 0
Name
