DS21Q44T ,Enhanced QUAD E1 FRAMERapplicationsORDERING INFORMATION Integral HDLC controller with 64-byte buffers 0 0DS21Q44T (0 C to ..
DS21Q44T ,Enhanced QUAD E1 FRAMERFEATURES FUNCTIONAL DIAGRAM Four E1 (CEPT or PCM-30) /ISDN-PRIframing transceiversRece ive Elastic ..
DS21Q48 ,5V E1/T1/J1 Line InterfacePIN DESCRIPTION 10 3 HARDWARE MODE ....... 23 3.1 REGISTER MAP ........23 3.2 PARALLEL PORT OPERATI ..
DS21Q48A3N ,5V E1/T1/J1 Line InterfaceFEATURES Complete E1, T1, or J1 Line Interface Unit TOP VIEW 44(LIU) Supports Both Long- and ..
DS21Q50 ,Quad E1 TransceiverFEATURES The DS21Q50 E1 quad transceiver contains all the Four Complete E1 (CEPT) PCM-30/ISDN-PRI ..
DS21Q50L ,Quad E1 TransceiverAPPLICATIONS CRC4 Codeword Errors, FAS Word Errors, and DSLAMs E Bits Routers Eight Additional U ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q44T
Enhanced QUAD E1 FRAMER
FEATURESFour E1 (CEPT or PCM-30) /ISDN-PRI
framing transceiversAll four framers are fully independent;
transmit and receive sections of each framerare fully independentFrames to FAS, CAS, CCS, and CRC4 formatsEach of the four framers contain dual two–
frame elastic store slip buffers that can
connect to asynchronous backplanes up to8.192 MHz8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)Easy access to Si and Sa bitsExtracts and inserts CAS signalingLarge counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bitsProgrammable output clocks for FractionalE1, per channel loopback, H0 and H12
applicationsIntegral HDLC controller with 64-byte buffers
configurable for Sa bits or DS0 operationDetects and generates AIS, remote alarm,and remote multiframe alarmsPin compatible with DS21Q42 Enhanced
Quad T1 Framer3.3V supply with 5V tolerant I/O; low power
CMOSAvailable in 128–pin TQFP packageIEEE 1149.1 support
FUNCTIONAL DIAGRAM
ACTUAL SIZE
ORDERING INFORMATIONDS21Q44T(00 C to 700 C)
DS21Q44TN(-400 C to +850 C)
DESCRIPTIONThe DS21Q44 E1 is an enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Eachframer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
DS21Q44
Enhanced QUAD E1 FRAMER
DS21Q44
1. INTRODUCTIONThe DS21Q44 is a superset version of the popular DS21Q43 Quad E1 framer offering the new features
listed below. All of the original features of the DS21Q43 have been retained and software created for the
original device is transferable to the DS21Q44.
New FeaturesAdditional hardware signaling capability including:– receive signaling reinsertion to a backplane multiframe syncavailability of signaling in a separate PCM data streamsignaling freezinginterrupt generated on change of signaling dataPer–channel code insertion in both transmit and receive pathsFull HDLC controller with 64–byte buffers in both transmit and receive paths. Configurable for Sa
bits or DS0 accessRCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state8.192 MHz clock synthesizerAbility to monitor one DS0 channel in both the transmit and receive pathsOption to extend carrier loss criteria to a 1 ms period as per ETS 300 233Automatic RAI generation to ETS 300 011 specificationsIEEE 1149.1 support
Functional DescriptionThe receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. Ifneeded, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.
Reader’s Note:This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us frame,
there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These
32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical
to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of
eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS Frame Alignment SignalCRC4Cyclical Redundancy Check
CAS Channel Associated SignalingCCS Common Channel Signaling
MF MultiframeSa Additional bits
Si International bitsE-bit CRC4 Error Bits
DS21Q44
DS21Q44 ENHANCED QUAD E1 FRAMER Figure 1-1
DS21Q44
TABLE OF CONTENTS
1. INTRODUCTION ..............................................................................................................................2
2. DS21Q44 PIN DESCRIPTION .........................................................................................................7
3. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................13
4. DS21Q44 REGISTER MAP.............................................................................................................20
5. PARALLEL PORT...........................................................................................................................24
6. CONTROL, ID AND TEST REGISTERS.....................................................................................24
7. STATUS AND INFORMATION REGISTERS.............................................................................34
8. ERROR COUNT REGISTERS.......................................................................................................40
9. DS0 MONITORING FUNCTION...................................................................................................43
10. SIGNALING OPERATION ............................................................................................................4510.1PROCESSOR BASED SIGNALING........................................................................................45
10.2HARDWARE BASED SIGNALING........................................................................................48
11. PER–CHANNEL CODE GENERATION AND LOOPBACK ...................................................4911.1TRANSMIT SIDE CODE GENERATION...............................................................................49
11.1.1Simple Idle Code Insertion and Per-Channel Loopback...................................................49
11.1.2Per-Channel Code Insertion..............................................................................................50
11.2RECEIVE SIDE CODE GENERATION..................................................................................51
12. CLOCK BLOCKING REGISTERS...............................................................................................52
13. ELASTIC STORES OPERATION ................................................................................................5313.1RECEIVE SIDE.........................................................................................................................54
13.2TRANSMIT SIDE.....................................................................................................................54
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION....................................5414.1HARDWARE SCHEME...........................................................................................................5414.2INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME.....................................55
14.3INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME...............................57
DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0.................................................................5915.1GENERAL OVERVIEW...........................................................................................................59
15.2HDLC STATUS REGISTERS..................................................................................................60
15.3BASIC OPERATION DETAILS...............................................................................................6115.4HDLC REGISTER DESCRIPTION..........................................................................................62
16. INTERLEAVED PCM BUS OPERATION...................................................................................69
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT..........................7217.1DESCRIPTION..........................................................................................................................72
17.2TAP CONTROLLER STATE MACHINE................................................................................73
17.3INSTRUCTION REGISTER AND INSTRUCTIONS.............................................................75
17.4TEST REGISTERS....................................................................................................................77
18. TIMING DIAGRAMS......................................................................................................................82
19. OPERATING PARAMETERS ......................................................................................................92
20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................105
DS21Q44
DOCUMENT REVISION HISTORY
Revision Notes12-22-98 Initial Release
DS21Q44
2. DS21Q44 PIN DESCRIPTION
Pin Description Sorted by Pin Number Table 2-1
DS21Q44
DS21Q44
DS21Q44
Note:1. Brackets [ ] indicate pin function when the DS21Q44 is configured for emulation of the DS21Q43,
(FMS = 1).
Pin Description Sorted by Pin Function, FMS = 0 Table 2-2
DS21Q44
DS21Q44
DS21Q44
3. DS21Q44 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINSSignal Name:
TCLKSignal Description:
Transmit ClockSignal Type:
InputA 2.048 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSERSignal Description:
Transmit Serial DataSignal Type:
InputTransmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store isdisabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLKSignal Description:
Transmit Channel ClockSignal Type:
OutputA 256 KHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation).
Signal Name:
TCHBLKSignal Description:
Transmit Channel BlockSignal Type:
OutputA user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLKwhen the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 Kbps (H0), 768
Kbps, 1920 bps (H12) or ISDN–PRI . Also useful for locating individual channels in drop–and–insert
applications, for external per–channel loopback, and for per–channel conditioning. See Section 12 for
DS21Q44
Signal Name:
TSYSCLKSignal Description:
Transmit System ClockSignal Type:
Input1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz.
Signal Name:
TLCLKSignal Description:
Transmit Link ClockSignal Type:
Output4 KHz to 20 KHz demand clock for the TLINK input. See Section 14 for details.
Signal Name:
TLINKSignal Description:
Transmit Link DataSignal Type:
InputIf enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination
of the Sa bit positions (Sa4 to Sa8). See Section 14 for details.
Signal Name:
TSYNCSignal Description:
Transmit SyncSignal Type:
Input /OutputA pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This pin can
also be programmed to output either a frame or multiframe pulse. Always synchronous with TCLK.
Signal Name:
TSSYNCSignal Description:
Transmit System SyncSignal Type:
InputOnly used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use thetransmit side elastic store. Always synchronous with TSYSCLK.
Signal Name:
TSIGSignal Description:
Transmit Signaling InputSignal Type:
InputWhen enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when
FMS = 0.
Signal Name:
TPOSSignal Description:
Transmit Positive Data OutputSignal Type:
OutputUpdated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR1.7) control bit.
Signal Name:
TNEGSignal Description:
Transmit Negative Data OutputSignal Type:
Output
DS21Q44
RECEIVE SIDE PINS
Signal Name:RLINKSignal Description:Receive Link DataSignal Type:Output
Updated with full recovered E1 data stream on the rising edge of RCLK.
Signal Name:RLCLKSignal Description:Receive Link ClockSignal Type:Output
A 4 KHz to 20 KHz clock for the RLINK output. Used for sampling Sa bits.
Signal Name:RCLKSignal Description:Receive Clock InputSignal Type:Input
2.048 MHz clock that is used to clock data through the receive side framer.
Signal Name:RCHCLK
Signal Description:Receive Channel Clock
Signal Type:Output A 256 KHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation).
Signal Name:RCHBLKSignal Description:Receive Channel BlockSignal Type:Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLKwhen the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name:RSERSignal Description:Receive Serial DataSignal Type:Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:RSYNCSignal Description:Receive Sync
Signal Type:Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRCmultiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
DS21Q44
Signal Name:RFSYNCSignal Description:Receive Frame Sync
Signal Type:Output
An extracted 8 KHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
Signal Name:RMSYNCSignal Description:Receive Multiframe Sync
Signal Type:Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. Ifthe receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q43 emulation).
Signal Name:RSYSCLKSignal Description:Receive System ClockSignal Type:Input1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied low
in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.
Signal Name:RSIGSignal Description:Receive Signaling OutputSignal Type:Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.This function is available when FMS = 0.
Signal Name:RLOS/LOTC
Signal Description:Receive Loss of Sync / Loss of Transmit Clock
Signal Type:OutputA dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q43
emulation).
Signal Name:CLKSISignal Description:8 MHz Clock ReferenceSignal Type:Input
A 2.048 MHz reference clock used in the generation of 8MCLK. This function is available when
FMS = 0.
Signal Name:8MCLKSignal Description:8 MHz Clock
Signal Type:Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function isavailable when FMS = 0.
DS21Q44
Signal Name:RPOSSignal Description:Receive Positive Data Input
Signal Type:Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS andRNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name:RNEG
Signal Description:Receive Negative Data Input
Signal Type:InputSampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
PARALLEL CONTROL PORT PINS
Signal Name:INT*Signal Description:InterruptSignal Type:OutputFlags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the FDL Status Register. Active low, open drain output.
Signal Name:FMSSignal Description:Framer Mode SelectSignal Type:Input
Set low to select DS21Q44 feature set. Set high to select DS21Q43 emulation.
Signal Name:MUXSignal Description:Bus OperationSignal Type:Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:D0 TO D7 / AD0 TO AD7Signal Description:Data Bus or Address/Data BusSignal Type:Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX
= 1), serves as a 8–bit multiplexed address / data bus.
Signal Name:A0 TO A5, A7Signal Description:Address Bus
Signal Type:Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation(MUX = 1), these pins are not used and should be tied low.
Signal Name:ALE (AS) / A6
Signal Description:Address Latch Enable (Address Strobe) or A6
Signal Type:InputIn non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
DS21Q44
Signal Name:BTSSignal Description:Bus Type Select
Signal Type:Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls thefunction of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name:RD* (DS*)
Signal Description:Read Input (Data Strobe)
Signal Type:InputRD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 19 .
Signal Name:FS0 AND FS1
Signal Description:Framer SelectsSignal Type:InputSelects which of the four framers to be accessed.
Signal Name:CS*
Signal Description:Chip SelectSignal Type:InputMust be low to read or write to the device. CS* is an active low signal.
Signal Name:WR* (R/W*)
Signal Description:Write Input (Read/Write)Signal Type:InputWR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name:TEST
Signal Description:3–State ControlSignal Type:InputSet high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
Signal Name:JTRST*Signal Description:IEEE 1149.1 Test ResetSignal Type:InputThis signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this pin should be held low. This function isavailable when FMS = 0.
Signal Name:JTMS
Signal Description:IEEE 1149.1 Test Mode Select
Signal Type:InputThis pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
DS21Q44
Signal Name:JTCLKSignal Description:IEEE 1149.1 Test Clock Signal
Signal Type:Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If notused, this pin should be tied to VSS. This function is available when FMS = 0.
Signal Name:JTDI
Signal Description:IEEE 1149.1 Test Data Input
Signal Type:InputTest instructions and data are clocked into this pin on the rising edge of JTCLK. If not used, this pin
should be pulled high. This function is available when FMS = 0.
Signal Name:JTDO
Signal Description:IEEE 1149.1 Test Data Output
Signal Type:OutputTest instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0.
SUPPLY PINS
Signal Name:VDD
Signal Description:Positive SupplySignal Type:Supply2.97 to 3.63 volts.
Signal Name:VSS
Signal Description:Signal GroundSignal Type:Supply0.0 volts.
DS21Q44
4. DS21Q44 REGISTER MAP
Register Map Sorted by Address Table 4-1
DS21Q44
DS21Q44
DS21Q44
DS21Q44
Notes:
1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to allzeros) on power– up initialization to insure proper operation.
2. Register banks CxH, DxH, ExH, and FxH are not accessible.
5. PARALLEL PORT
The DS21Q44 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21Q44 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorolatiming will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 19 for more details.
6. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS21Q44 is configured via a set of ten control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21Q44 has been initialized, the control registers will only need to be accessed when there is achange in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).
Each of the ten registers are described in this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that the DS21Q44 is present. The T1 pin–for–pin compatible version of the
DS21Q44 is the DS21Q42 and it also has an ID register at address 0Fh and the user can read the MSB to
DS21Q44
Power–Up Sequence
The DS21Q44 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach on each framer within the DS21Q44.
1. Clear framer’s register space by writing 00H to the addresses 00H through 0BFH.
2. Program required registers to achieve desired operating mode.
Note:
When emulating the DS21Q43 feature set (FMS = 1), the full address space (00H through 0BFH) must beinitialized. DS21Q43 emulation require address pin A7 to be used.
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
T1E1IDR.7T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chipID3IDR.3Chip Revision Bit 3. MSB of a decimal code that represents the
chip revision.
ID2IDR.1Chip Revision Bit 2.
ID1IDR.2Chip Revision Bit 1.
ID0IDR.0Chip Revision Bit 0. LSB of a decimal code that represents thechip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RSMFRCR1.7RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries1 = RSYNC outputs CRC4 multiframe boundaries
RSMRCR1.6RSYNC Mode Select.
0 = frame mode (see the timing in Section 18)
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
RSIORCR1.5RSYNC I/O Select. (note: this bit must be set to zero when
RCR2.1=0).
0 = RSYNC is an output (depends on RCR1.6)1 = RSYNC is an input (only valid if elastic store enabled)RCR1.4Not Assigned. Should be set to zero when written.RCR1.3Not Assigned. Should be set to zero when written.
FRCRCR1.2Frame Resync Criteria.
0 = resync if FAS received in error 3 consecutive times1 = resync if FAS or bit 2 of non–FAS is received in error 3
consecutive times
SYNCERCR1.1Sync Enable.
0 = auto resync enabled
1 = auto resync disabledRESYNCRCR1.0Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
SYNC/RESYNC CRITERIA Table 6–1
DS21Q44
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
Sa8SRCR2.7Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit
position; set to zero to force RLCLK low during Sa8 bitposition. See Section 18 for timing details.
Sa7SRCR2.6Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit
position; set to zero to force RLCLK low during Sa7 bit
position. See Section 18 for timing details.
Sa6SRCR2.5Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bitposition; set to zero to force RLCLK low during Sa6 bit
position. See Section 18 for timing details.
Sa5SRCR2.4Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit
position; set to zero to force RLCLK low during Sa5 bit
position. See Section 18 for timing details.Sa4SRCR2.3Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit
position; set to zero to force RLCLK low during Sa4 bit
position. See Section 18 for timing details.
RBCSRCR2.2Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz1 = if RSYSCLK is 2.048 MHz
RESERCR2.1Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabledRCR2.0Not Assigned. Should be set to zero when written.
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
ODFTCR1.7Output Data Format.0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG=0
TFPTTCR1.6Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
T16STCR1.5Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin
1 = source timeslot 16 from TS0 to TS15 registers
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
TUA1TCR1.4Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEGTSiSTCR1.3Transmit International Bit Select.0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1TCR1.2Transmit Signaling All Ones.0 = normal operation
1 = force timeslot 16 in every frame to all ones
TSMCR1.1TSYNC Mode Select.
0 = frame mode (see the timing in Section 18)
1 = CAS and CRC4 multiframe mode (see the timing in Section18)
TSIOTCR1.0TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
Notes:
See Figure 18–15 for more details about how the Transmit Control Registers affect the operation of the
DS21Q44.
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
Sa8STCR2.7Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK
pin; set to zero to not source the Sa8 bit. See Section 18 for
timing details.
Sa7STCR2.6Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINKpin; set to zero to not source the Sa7 bit. See Section 18 for
timing details.
Sa6STCR2.5Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK
pin; set to zero to not source the Sa6 bit. See Section 18 for
timing details.Sa5STCR2.4Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK
pin; set to zero to not source the Sa5 bit. See Section 18 for
timing details.
Sa4STCR2.3Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK
pin; set to zero to not source the Sa4 bit. See Section 18 fortiming details.
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
ODMTCR2.2Output Data Mode.
0 = pulses at TPOSO and TNEGO are one full TCLKO period
wide1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
AEBETCR2.1Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit directionTCR2.0Function of RLOS/LOTC Pin.0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
FLBCCR1.7Framer Loopback.
0=loopback disabled
1=loopback enabled
THDB3CCR1.6Transmit HDB3 Enable.0=HDB3 disabled
1=HDB3 enabled
TG802CCR1.5Transmit G.802 Enable. See Section 18 for details.
0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26TCRC4CCR1.4Transmit CRC4 Enable.0=CRC4 disabled
1=CRC4 enabled
RSMCCR1.3Receive Signaling Mode Select.
0=CAS signaling mode1=CCS signaling mode
RHDB3CCR1.2Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
RG802CCR1.1Receive G.802 Enable. See Section 18 for details.0=do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
RCRC4CCR1.0Receive CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
DS21Q44
FRAMER LOOPBACK
When CCR1.7 is set to a one, the framer will enter a Framer LoopBack (FLB) mode. See Figure 1–1 for
more details. This loopback is useful in testing and debugging applications. In FLB, the framer will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOS and TNEG.2. Data input via RPOS and RNEG will be ignored.
3. The RCLK output will be replaced with the TCLK input.
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
ECUSCCR2.7Error Counter Update Select. See Section 8 for details.
0=update error counters once a second
1=update error counters every 62.5 ms (500 frames)
VCRFSCCR2.6VCR Function Select. See Section 8 for details.0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
AAISCCR2.5Automatic AIS Generation.
0=disabled
1=enabledARACCR2.4Automatic Remote Alarm Generation.0=disabled
1=enabled
RSERCCCR2.3RSER Control.
0=allow RSER to output data as received under all conditions1=force RSER to one under loss of frame alignment conditions
LOTCMCCCR2.2Loss of Transmit Clock Mux Control. Determines whether
the transmit side formatter should switch to the ever present
RCLK if the TCLK should fail to transition (see Figure 1–1).
0=do not switch to RCLK if TCLK stops1=switch to RCLK if TCLK stops
RFFCCR2.1Receive Force Freeze. Freezes receive side signaling at RSIG
(and RSER if CCR3.3=1); will override Receive Freeze Enable
(RFE). See Section 10 or details.
0=do not force a freeze event1=force a freeze event
RFECCR2.0Receive Freeze Enable. See Section 10 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSIG (and RSER
if CCR3.3=1).
DS21Q44
AUTOMATIC ALARM GENERATION
The DS21Q44 can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS
generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the
following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
framer will transmit an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to
determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm
(all one’s) reception, loss of receive carrier or if CRC4 multiframe synchronization (if enabled) cannot be
found within 128 ms of FAS synchronization. If any one (or more) of the above conditions is present,then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a
constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization
within 400 ms as per G.706.
It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TESECCR3.7Transmit Side Elastic Store Enable.0=elastic store is bypassed
1=elastic store is enabled
TCBFSCCR3.6Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin1=TCBRs define which signaling bits are to be inserted
TIRFSCCR3.5Transmit Idle Registers (TIR) Function Select. See Section
11 for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER(i.e., Per Channel Loopback function)CCR3.4Not Assigned. Should be set to zero when written.
RSRECCR3.3Receive Side Signaling Re–Insertion Enable. See Section 10
for details.
0=do not re–insert signaling bits into the data stream presentedat the RSER pin
1=re–insert the signaling bits into data stream presented at the
RSER pin
THSECCR3.2Transmit Side Hardware Signaling Insertion Enable. See
Section 10 for details.0=do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
presented at the TSER pin
TBCSCCR3.1Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz1=if TSYSCLK is 2.048 MHz
RCLACCR3.0Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive zeros (125 us)
1=RCL declared upon 2048 consecutive zeros (1 ms)
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RLBCCR4.7Remote Loopback.
0 = loopback disabled1 = loopback enabledCCR4.6Not Assigned. Should be set to zero when written.CCR4.5Not Assigned. Should be set to zero when written.
TCM4CCR4.4Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in theTDS0M register. See Section 9 or details.
TCM3CCR4.3Transmit Channel Monitor Bit 3.
TCM2CCR4.2Transmit Channel Monitor Bit 2.
TCM1CCR4.1Transmit Channel Monitor Bit 1.
TCM0CCR4.0Transmit Channel Monitor Bit 0. LSB of the channel decode.
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR5.7Not Assigned. Should be set to zero when writtenRESALGNCCR5.6Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if
the pointer separation is already greater or equal to half a frame.
If pointer separation is less then half a frame, the command willbe executed and data will be disrupted. Should be toggled after
RSYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent align. See Section 13 for details.
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
TESALGNCCR5.5Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be takenif the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13for details.
RCM4CCR5.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
RCM3CCR5.3Receive Channel Monitor Bit 3.RCM2CCR5.2Receive Channel Monitor Bit 2.RCM1CCR5.1Receive Channel Monitor Bit 1.
RCM0CCR5.0Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR6.7Not Assigned. Should be set to zero when writtenCCR6.6Not Assigned. Should be set to zero when writtenCCR6.5Not Assigned. Should be set to zero when written–CCR6.4Not Assigned. Should be set to zero when writtenCCR6.3Not Assigned. Should be set to zero when written
TCLKSRCCCR6.2Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RESRCCR6.1Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
TESRCCR6.0Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
DS21Q44
7. STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 15 but
they operate the same as the other status registers in the DS21Q44 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will becleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The bytewritten to the register will inform the framer which bits the user wishes to read and have cleared. The user
will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a
zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written
to a bit location, the read register will be updated with the latest information. When a zero is written to a
bit position, the read register will not be updated and the previous value will be held. A write to the statusand information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor toindividually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q44 with higher–order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read ofthis register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), andHDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 15.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act
differently than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA,
RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interruptswill force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 7-1). The INT* pin will be allowed to return high (if no other
interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is
still present, the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
DS21Q44
ISR: INTERRUPT STATUS REGISTER (Any address from 0C0 Hex to 0FF Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
F3HDLCISR.7FRAMER 3 HDLC CONTROLLER INTERRUPT
REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
F3SRISR.6FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.F2HDLCISR.5FRAMER 2 HDLC CONTROLLER INTERRUPTREQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F2SRISR.4FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
F1HDLCISR.3FRAMER 1 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.1 = Interrupt request pending.
F1SRISR.2FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F0HDLCISR.1FRAMER 0 HDLC CONTROLLER INTERRUPT
REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
F0SRISR.0FRAMER 0 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.1 = Interrupt request pending.
DS21Q44
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TESFRIR.7Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.TESERIR.6Transmit Side Elastic Store Empty. Set when the transmit
side elastic store buffer empties and a frame is repeated.
LORCRIR.5Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2μs (3μs ± 1μs).RESFRIR.4Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
RESERIR.3Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRCRCRIR.2CRC Resync Criteria Met. Set when 915/1000 code words arereceived in error.
FASRCRIR.1FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CASRCRIR.0CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
CSC5SSR.7CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.CSC4SSR.6CRC4 Sync Counter Bit 4.CSC3SSR.5CRC4 Sync Counter Bit 3.
CSC2SSR.4CRC4 Sync Counter Bit 2.
CSC0SSR.3CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next
to LSB is not accessible.FASSASSR.2FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CASSASSR.1CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4SASSR.0CRC4 MF Sync Active. Set while the synchronizer issearching for the CRC4 MF alignment word.
DS21Q44
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests
that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should beabandoned and proper action taken. The CRC4 Sync Counter will rollover.
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1SR1.7Receive Signaling All Ones / Signaling Change. Set when
over a full MF, the content of timeslot 16 contains less than
three zeros. This alarm is not disabled in the CCS signaling
mode. A change in the contents of RS1 through RS16 from one
multiframe to the next will cause RSA1 and RSA0 to be set.RDMASR1.6Receive Distant MF Alarm. Set when bit–6 of timeslot 16 in
frame 0 has been set for two consecutive multiframes. This
alarm is not disabled in the CCS signaling mode.
RSA0SR1.5Receive Signaling All Zeros / Signaling Change. Set when
over a full MF, timeslot 16 contains all zeros. A change in thecontents of RS1 through RS16 from one multiframe to the next
will cause RSA1 and RSA0 to be set.
RSLIPSR1.4Receive Side Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
RUA1SR1.3Receive Unframed All Ones. Set when an unframed all onescode is received at RPOS and RNEG.
RRASR1.2Receive Remote Alarm. Set when a remote alarm is received
at RPOS and RNEG.
RCLSR1.1Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1)
consecutive zeros have been detected at RPOS and RNEG.RLOSSR1.0Receive Loss of Sync. Set when the device is not synchronized
to the receive E1 stream.
DS21Q44
ALARM CRITERIA Table 7-1
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
RAFSR2.6Receive Align Frame. Set every 250 s at the beginning ofalign frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
TMFSR2.5Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert thehost that signaling data needs to be updated.
SECSR2.4One Second Timer. Set on increments of one second based on
RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms
instead of once a second.
TAFSR2.3Transmit Align Frame. Set every 250 s at the beginning ofalign frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
LOTCSR2.2Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 s). Will force the
LOTC pin high if enabled via TCR2.0.
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
RCMFSR2.1Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.TSLIPSR2.0Transmit Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1IMR1.7Receive Signaling All Ones / Signaling Change.
0=interrupt masked
1=interrupt enabled
RDMAIMR1.6Receive Distant MF Alarm.0=interrupt masked
1=interrupt enabled
RSA0IMR1.5Receive Signaling All Zeros / Signaling Change.
0=interrupt masked
1=interrupt enabledRSLIPIMR1.4Receive Elastic Store Slip Occurrence.0=interrupt masked
1=interrupt enabled
RUA1IMR1.3Receive Unframed All Ones.
0=interrupt masked1=interrupt enabled
RRAIMR1.2Receive Remote Alarm.
0=interrupt masked
1=interrupt enabled
RCLIMR1.1Receive Carrier Loss.0=interrupt masked
1=interrupt enabled
RLOSIMR1.0Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
DS21Q44
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive CAS Multiframe.
0=interrupt masked1=interrupt enabled
RAFIMR2.6Receive Align Frame.
0=interrupt masked
1=interrupt enabled
TMFIMR2.5Transmit Multiframe.0=interrupt masked
1=interrupt enabled
SECIMR2.4One Second Timer.
0=interrupt masked
1=interrupt enabledTAFIMR2.3Transmit Align Frame.0=interrupt masked
1=interrupt enabled
LOTCIMR2.2Loss Of Transmit Clock.
0=interrupt masked1=interrupt enabled
RCMFIMR2.1Receive CRC4 Multiframe.
0=interrupt masked
1=interrupt enabled
TSLIPIMR2.0Transmit Side Elastic Store Slip Occurrence.0=interrupt masked
1=interrupt enabled
8. ERROR COUNT REGISTERS
There are a set of four counters in each framer that record bipolar or code violations, errors in the CRC4
SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these fourcounters are automatically updated on either one second boundaries (CCR2.7=0) or every 62.5 ms
(CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt
from the one second timer to determine when to read these registers. The user has a full second (or 62.5
ms) to read the counters before the data is lost. All four counters will saturate at their respectivemaximum counts and they will not rollover.
BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16–bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the samepolarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
DS21Q44
Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
the framer should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on a E1 line would have to begreater than 10** –2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)(LSB)VCR1VCR2
SYMBOLPOSITIONNAME AND DESCRIPTIONV15VCR1.7MSB of the 16–bit code violation countV0VCR2.0LSB of the 10–bit code violation count
CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since themaximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is
disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of
multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)(LSB)CRCCR1CRCCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC9CRCCR1.1MSB of the 10–Bit CRC4 error count
CRC0CRCCR2.0LSB of the 10–Bit CRC4 error count
Note:
1. The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error
counter.
E–Bit Counter
E–bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word ofa 10–bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter
DS21Q44
EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)(LSB)EBCR1EBCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
EB9EBCR1.1MSB of the 10–Bit E–Bit Error CountEB0EBCR2.0LSB of the 10–Bit E–Bit Error Count
Note:
The upper six bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex)
(MSB)(LSB)FASCR1FASCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
FAS11FASCR1.7MSB of the 12–Bit FAS Error CountFAS0FASCR2.2LSB of the 12–Bit FAS Error Count
Notes:
1. The lower two bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error
counter.2. The lower two bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.
DS21Q44
9. DS0 MONITORING FUNCTION
Each framer in the DS21Q44 has the ability to monitor one DS0 64Kbps channel in the transmit direction
and one DS0 channel in the receive direction at the same time. In the transmit direction the user will
determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4
register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel. Channels 1 through 32 map to register values 0 through
31. For example, if DS0 channel 6 (timeslot 5) in the transmit direction and DS0 channel 15 (timeslot 14)
in the receive direction needed to be monitored, then the following values would be programmed intoCCR4 and CCR5:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
[Repeated here from section 6 for convenience]
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RLBCCR4.7Remote Loopback.
0 = loopback disabled
1 = loopback enabledCCR4.6Not Assigned. Should be set to zero when written.–CCR4.5Not Assigned. Should be set to zero when written.
TCM4CCR4.4Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 9 or details.TCM3CCR4.3Transmit Channel Monitor Bit 3.TCM2CCR4.2Transmit Channel Monitor Bit 2.
TCM1CCR4.1Transmit Channel Monitor Bit 1.
TCM0CCR4.0
Transmit Channel Monitor Bit 0. LSB of the channel decode.
DS21Q44
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTDS0M.7Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).B2TDS0M.6Transmit DS0 Channel Bit 2.B3TDS0M.5Transmit DS0 Channel Bit 3.TDS0M.4Transmit DS0 Channel Bit 4.TDS0M.3Transmit DS0 Channel Bit 5.TDS0M.2Transmit DS0 Channel Bit 6.B7TDS0M.1Transmit DS0 Channel Bit 7.B8TDS0M.0Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
[Repeated here from section 6 for convenience]
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR5.7Not Assigned. Should be set to zero when written
RESALGNCCR5.6Receive Elastic Store Align. Setting this bit from a zero to aone may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if
the pointer separation is already greater or equal to half a frame.
If pointer separation is less then half a frame, the command will
be executed and data will be disrupted. Should be toggled afterRSYSCLK has been applied and is stable. Must be cleared and
set again for a subsequent align. See Section 13 for details.
TESALGNCCR5.5Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be takenif the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13for details.
RCM4CCR5.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
DS21Q44
SYMBOLPOSITIONNAME AND DESCRIPTION
RCM3CCR5.3Receive Channel Monitor Bit 3.
RCM2CCR5.2Receive Channel Monitor Bit 2.
RCM1CCR5.1Receive Channel Monitor Bit 1.RCM0CCR5.0Receive Channel Monitor Bit 0. LSB of the channel decode.
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRDS0M.7Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit
to be received).RDS0M.6Receive DS0 Channel Bit 2.RDS0M.5Receive DS0 Channel Bit 3.B4RDS0M.4Receive DS0 Channel Bit 4.B5RDS0M.3Receive DS0 Channel Bit 5.RDS0M.2Receive DS0 Channel Bit 6.RDS0M.1Receive DS0 Channel Bit 7.RDS0M.0Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bitto be received).
10. SIGNALING OPERATION
Each framer in the DS21Q44 contains provisions for both processor based (i.e., software based) signaling
bit access and for hardware based access. Both the processor based access and the hardware based access
can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and thehardware based signaling is covered in Section 10.2.
10.1 PROCESSOR BASED SIGNALING
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channelassociated with a particular signaling bit. The voice channel numbers have been assigned as described in
the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is
used in the rest of the data sheet. For example, voice channel 1 is associated with timeslot 1 (Channel 2)
and voice Channel 30 is associated with timeslot 31 (Channel 32). There is a set of 16 registers for the
receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registersare detailed below.
DS21Q44
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB)(LSB)RS1 (30)RS2 (31)RS3 (32)RS3 (33)RS5 (34)RS6 (35)RS7 (36)RS8 (37)RS9 (38)RS10 (39)RS11 (3A)RS12 (3B)RS13 (3C)RS14 (3D)RS15 (3E)RS16 (3F)
SYMBOLPOSITIONNAME AND DESCRIPTIONRS1.0/1/3Spare Bits.RS1.2Remote Alarm Bit (integrated and reported in SR1.6).
A(1)RS2.7Signaling Bit A for Channel 1D(30)RS16.0Signaling Bit D for Channel 30.
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize theReceive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have beenloaded with data. The user has 2 ms to retrieve the data before it is lost. The signaling data reported in
RS1 to RS16 is also available at the RSIG and RSER pins.
Three status bits in Status Register 1 (SR1) monitor the contents of registers RS1 through RS16. Status
monitored includes all zeros detection, all ones detection and a change in register contents. The ReceiveSignaling All Zeros status bit (SR1.5) is set when over a full multi-frame, RS1 through RS16 contain all
zeros. The Receive Signaling All Ones status bit (SR1.7) is set when over a full multi-frame, RS1 through
RS16 contain less than three zeros. A change in the contents of RS1 through RS16 from one multiframe
to the next will cause RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time.
The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting either
the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75 ms to
DS21Q44
TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex)
(MSB)(LSB)TS1 (40)TS2 (41)TS3 (42)TS4 (43)TS5 (44)TS6 (45)TS7 (46)TS8 (47)TS9 (48)TS10 49)TS11(4A)TS12 (4B)TS13 (4C)TS14 (4D)TS15 (4E)TS16 (4F)
SYMBOLPOSITIONNAME AND DESCRIPTIONTS1.0/1/3Spare Bits.TS1.2Remote Alarm Bit (integrated and reported in SR1.6).
A(1)TS2.7Signaling Bit A for Channel 1D(30)TS16.0Signaling Bit D for Channel 30.
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the framer
will load the values present in the Transmit Signaling Register into an outgoing signaling shift registerthat is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5)
to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to update
the TSR’s before the old data will be retransmitted. ITU specifications recommend that the ABCD
signaling not be set to all zeros because they will emulate a CAS multiframe alignment word.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a one. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to one. In CCS signalingmode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data
before the old data will be retransmitted.
Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) todeter-mine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the
corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pin (the
DS21Q44
10.2 HARDWARE BASED SIGNALING
Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, thenthe backplane clock (RSYSCLK) must be 2.048 MHz. The ABCD signaling bits are output on RSIG in
the lower nibble of each channel. The RSIG data is updated once a multiframe (2 ms) unless a freeze is in
effect. See the timing diagrams in Section 18 for some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked bysetting the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data be re–aligned at the RSER output according to this applied
multiframe boundary. in this mode, the elastic store must be enabled the backplane clock must be 2.048
MHz.
The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,carrier loss, or slip has occurred.
The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the
RSIG pin (and at the RSER pin if RSRE=1 via CCR3.3). When freezing is enabled (RFE=1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.When the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms
to 5 ms before being allowed to be updated with new signaling data.
Transmit Side
Via the THSE control bit (CCR3.2), the DS21Q44 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
hardware signaling insertion capabilities of each framer are available whether the transmit side elasticstore is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock (TSYSCLK)
must be 2.048 MHz.
When hardware signaling insertion is enabled on a framer (THSE=1), then the user must enable the
Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6=1). This is needed sothat the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to
timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper
information. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from
TSER (or TSIG if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from
the Transmit Signaling (TS) registers. See definition below.
DS21Q44
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)(LSB)TCBR1 (22)TCBR2 (23)TCBR3 (24)TCBR4 (25)
Note:
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
CONTROL BITSREGISTER VALUESTHSE=1 (CCR3.2)TS1=0Bh (MF alignment word, remote alarm etc.)
TCBFS=1 (CCR3.6)TCBR1=03h (source timeslot 16, frame 1 data)
T16S=1(TCR1.5)TCBR2=01h (source voice Channel 5 signaling data from TS6)
TCBR3=04h (source voice Channel 10 signaling data from TS11)TCBR4=00h
11. PER–CHANNEL CODE GENERATION AND LOOPBACK
Each framer in the DS21Q44 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section11.1. The receive direction is from the E1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 was a
feature contained in the original DS21Q43 while the second method which is covered in Section 11.1.2 is
a new feature of the DS21Q44.
11.1.1 Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
DS21Q44
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs mustbe synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC. There are no restrictions on which channels can be looped back or on how many channels can
be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
(MSB)(LSB)TIR1 (26)TIR2 (27)TIR3 (28)TIR4 (29)
SYMBOLSPOSITIONSNAME AND DESCRIPTION
CH1 - 32TIR1.0 - 4.7Transmit Idle Code Insertion Control Bits.0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
Notes:
If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–ChannelLoopback; see Figure 1–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TIDR7TIDR.7MSB of the Idle Code (this bit is transmitted first)TIDR0TIDR.0LSB of the Idle Code (this bit is transmitted last)
11.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit ChannelRegisters (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
DS21Q44
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)(LSB)TC1 (60)
SYMBOLPOSITIONNAME AND DESCRIPTIONTC1.7MSB of the Code (this bit is transmitted first)C0TC1.0LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address=A0 to A3 Hex)
(MSB)(LSB)TCC1 (A0)TCC2 (A1)TCC3 (A2)TCC4 (A3)
SYMBOLPOSITIONNAME AND DESCRIPTION
CH1 - 32TCC1.0 - 4.7Transmit Code Insertion Control Bits
0 = do not insert data from the TC register into the transmit data
stream
1 = insert data from the TC register into the transmit datastream
11.2 RECEIVE SIDE CODE GENERATION
On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the codeplaced in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be
placed into each of the 32 E1 channels.
RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address=80 to 9F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)(LSB)RC1 (80)
SYMBOLPOSITIONNAME AND DESCRIPTIONC7RC1.7MSB of the Code (this bit is sent first to the backplane)RC1.0LSB of the Code (this bit is sent last to the backplane)
DS21Q44
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)(LSB)RCC1 (A4)RCC2 (A5)RCC3 (A6)RCC4 (A7)
SYMBOLPOSITIONNAME AND DESCRIPTION
CH1 - 32RCC1.0 - 4.7Receive Code Insertion Control Bits0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data stream
12. CLOCK BLOCKING REGISTERSThe Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK andTCHBLK pin will be held high during the entire corresponding channel time. See the timing in Section
18 for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to
use the TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted via the
TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pins
(the corresponding bit in the TCBR=0). See the timing in Section 18 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address=2B to 2E Hex)
(MSB)(LSB)RCBR1 (2B)RCBR2 (2C)RCBR3 (2D)RCBR4 (2E)
SYMBOLSPOSITIONSNAME AND DESCRIPTION
CH1 - 32RCBR1.0 - 4.7Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channeltime
1 = force the RCHBLK pin high during this channel time
DS21Q44
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING
REGISTERS (Address=22 to 25 Hex)
(MSB)(LSB)TCBR1 (22)TCBR2 (23)TCBR3 (24)TCBR4 (25)
SYMBOLSPOSITIONSNAME AND DESCRIPTIONCH1 - 32TCBR1.0 - 4.7Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
Note:
If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG
if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from the TransmitSignaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)(LSB)TCBR1 (22)TCBR2 (23)TCBR3 (24)TCBR4 (25)
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
13. ELASTIC STORES OPERATION
Each framer in the DS21Q44 contains dual two–frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 datastream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or
2.048 MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled ordisabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (CCR6.0
& CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is lost during
the reset. The second method, the Elastic Store Align ( CCR5.5 & CCR5.6) forces the elastic store depth
to a minimum depth of half a frame only if the current pointer separation is already less then half a frame.
