DS21Q43AT ,Quad E1 Framerapplications§ Detects and generates AIS, remote alarm, and QUADE1remote multiframe alarmsFRAMER§ Pi ..
DS21Q43AT ,Quad E1 FramerFEATURES FUNCTIONAL DIAGRAM§ Four E1 (CEPT or PCM-30) /ISDN-PRIframing transceivers§ All four frame ..
DS21Q43AT ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
DS21Q43AT ,Quad E1 Framerfeatures have been added to the framers in theDS21Q43A over the DS2143.ADDED FEATURE SECTIONNon-mul ..
DS21Q43AT+ ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
DS21Q44T ,Enhanced QUAD E1 FRAMERapplicationsORDERING INFORMATION Integral HDLC controller with 64-byte buffers 0 0DS21Q44T (0 C to ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q43AT
Quad E1 Framer
FEATURESFour E1 (CEPT or PCM-30) /ISDN-PRI
framing transceiversAll four framers are fully independent;
transmit and receive sections of each framerare fully independentFrames to FAS, CAS, CCS, and CRC4
formats8-bit parallel control port that can be
connected to either multiplexed or non-multiplexed busesEach of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz§ Easy access to Si and Sa bitsExtracts and inserts CAS signalingLarge counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits§ Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applicationsDetects and generates AIS, remote alarm, and
remote multiframe alarms§ Pin-compatible with DS21Q41B Quad T1
Framer5V supply; low power CMOSAvailable in 128-pin TQFPIndustrial (-40°C to +85°C) grade versionavailable (DS21Q43ATN)
FUNCTIONAL DIAGRAM
ACTUAL SIZE
DESCRIPTIONThe DS21Q43A combines four of the popular DS2143 E1 Controllers onto a single monolithic die. The
“A” designation denotes that some new features are available in the Quad version which were not
available in the single E1 device. The added features in the DS21Q43A are listed in Section 1. TheDS21Q43A offers a substantial space savings to applications that require more than one E1 framer on a
card. The Quad version is only slightly bigger than the single E1 device. All four framers in the
DS21Q43A are totally independent; they do not share a common framing synchronizer. Also, the transmit
and receive sides of each framer are totally independent. The dual two-frame elastic stores contained in
each of the four framers can be independently enabled and disabled as required. The DS21Q43A meets
DS21Q43A
1.0 INTRODUCTIONThe DS21Q43A Quad E1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer
#3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each
of the four framers within the DS21Q43A maintains the same register structure that appeared in the
DS2143. The two framer-select inputs (FS0 and FS1) are used to determine which framer within the
DS21Q43A is being accessed. In this manner, software written for the DS2143 can also be used in theDS21Q43A with only slight modifications. Several new features have been added to the framers in the
DS21Q43A over the DS2143.
DS21Q43A
DS21Q43A BLOCK DIAGRAM Figure 1-1
READER’S NOTEThis data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 system which are numbered 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 isthe LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS Frame Alignment CRC4 Cyclical Redundancy Check
CAS Channel Associated CCS Common Channel Signaling
Signaling
MF Multiframe SaAdditional bits
DS21Q43A
PIN-OUT CONFIGURATION Figure 1-2
DS21Q43A
TRANSMIT PIN LIST Table 1-1
DS21Q43A
RECEIVE PIN LIST Table 1-2
DS21Q43A
DS21Q43A
CONTROL PORT/TEST/SUPPLY PIN LIST Table 1-3
DS21Q43A
DS21Q43A PIN DESCRIPTION Table 1-4
Transmit Clock [TCLK]. 2.048 MHz primary clock. Used to clock data through the transmit side
formatter. Necessary for proper operation of the parallel control port.
Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK whenthe transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmitside elastic store is enabled.
Transmit Channel Clock [TCHCLK]. 256 kHz clock which pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with
TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion ofchannel data. See Section 11 for timing details.
Transmit Bipolar Data [TPOS and TNEG]. Updated on rising edge of TCLK. Can be programmed tooutput NRZ data on TPOS via the TCR1.7 control bit.
Transmit Channel Block [TCHBLK]. A user programmable output that can be forced high or low
during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is
disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used
such as Fractional E1, 384 kpbs service (H0), 1920 kpbs (H12), or ISDN-PRI. Also useful for locatingindividual channels in drop-and-insert applications and for per-channel loopback. See Section 11 for
timing details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmitside elastic store function is enabled. Should be tied low in applications that do not use the transmit sideelastic store.
Transmit Link Clock [TLCLK]. 4 kHz to 20 kHz demand clock for the TLINK input. Controlled by
TCR2. See Section 11 for timing details.
Transmit Link Data [TLINK]. If enabled via TCR2, this pin will be sampled on the falling edge ofTCLK to insert data into the Sa bit positions. See Section 11 for timing details.
Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for theDS21Q43A. Via TCR1.1, the DS21Q43A can be programmed to output either a frame or multiframepulse at this pin. See Section 11 for timing details.
Transmit Frame Sync [TFSYNC]. 8 kHz pulse. Only used when the transmit side elastic store is
enabled. A pulse at this pin will establish frame boundaries for the DS21Q43A. Should be tied low in
applications that do not use the transmit side elastic store. See Section 11 for timing details.
Receive Link Data [RLINK]. Updated with full received E1 data stream on the rising edge of RCLK.See Section 11 for timing details.
Receive Link Clock [RLCLK]. 4 kHz to 20 kHz demand clock for the RLINK output. Controlled byRCR2. See Section 11 for timing details. Necessary for proper operation of the parallel control port.
DS21Q43A
Receive Channel Clock [RCHCLK]. 256 kHz clock which pulses high during the LSB of each channel.Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data. See
Section 11 for timing details.
Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low duringany of the 32 E1 channels. Synchronous with RCLK when the transmit side elastic store is disabled.
Synchronous with RSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks
to a serial UART or LAPD controller in applications where not all E1 channels are used such asFractional E1, 384 kpbs service (H0), 1920 kpbs (H12), or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications and for per-channel loopback. See Section 11 for timing details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when thereceive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive sideelastic store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies eitherframe (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If the receive side elastic store is enabled via
RCR2.1, then this pin can be enabled to be an input at which a frame boundary pulse is applied. SeeSection 11 for timing details.
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse, one RCLK wide, is output at this pin whichidentifies frame boundaries. See Section 11 for timing details.
Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this pin which identifies either CAS or CRC4
multiframe boundaries. If the receive side elastic store is disabled, then this output should be ignored. See
Section 11 for timing details.
Receive Bipolar Data Inputs [RPOS and RNEG]. Sampled on falling edge of RCLK. Tie together toreceive NRZ data and disable bipolar violation monitoring circuitry.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic storefunction is enabled. Should be tied low in applications that do not use the elastic store. Allowing this pinto float can cause the device to 3-state its outputs.
Receive Loss of Sync/Loss of Transmit Clock [RLOS/LOTC]. A dual function output. If CCR1.6=0,then this pin will toggle high when the synchronizer is searching for the E1 frame or multiframe. If
TCR2.0=1, then this pin will toggle high the TCLK pin has not been toggled for 5 ms.
Receive Alarm Interrupt [INT]. Flags host controller during conditions defined in the Status Registersof the four framers. User can poll the Interrupt Status Register (ISR) to determine which status register in
which framer is active (if any). Active low, open drain output.
3-State Control [TEST]. Set high to 3-state all output and I/O pins (including the parallel control port).Set low for normal operation. Useful in board-level testing.
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
DS21Q43A
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the WR (R/W) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input [
Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.
Chip Selects [CS]. Must be low to read or write to any of the four framers.
A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [WR] (Read/Write [R/W]).
Positive Supply [VDD]. 5.0 volts ± 0.5 volts.
Signal Ground [VSS]. 0.0 volts.
DS21Q43A FRAMER DECODE Table 1-5
DS21Q43A
DS21Q43A REGISTER MAP Table 1-6
DS21Q43A
DS21Q43A
NOTES:1. The Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all
0s) on power-up initialization to insure proper operation.
2. Any register address between 60h and 7Fh or between E0h and FFh will allow the status of the
interrupts to appear on the bus.
3. Register addresses 09h through 0Fh are reserved for future use.
2.0 PARALLEL PORTThe DS21Q43A is controlled via either a non-multiplexed (MUX=0) or multiplexed (MUX=1) bus by an
external microcontroller or microprocessor. The DS21Q43A can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams inthe AC Electrical Characteristics for more details.
3.0 CONTROL AND TEST REGISTERSThe operation of the DS21Q43A is configured via a set of seven registers. Typically, the control registers
are only accessed when the system is powered up. Once the DS21Q43A has been initialized, the control
registers will only need to be accessed when there is a change in the system configuration. There are two
Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and
three Common Control Registers (CCR1, CCR2 and CCR3). Each of the seven registers is described inthis section.
DS21Q43A
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRSMFRCR1.7
programmed in the multiframe mode (RCR1.6=1).0=RSYNC outputs CAS multiframe boundaries.
1=RSYNC outputs CRC4 multiframe boundaries.
RSMRCR1.6
RSYNC Mode Select.0=frame mode (see the timing in Section 11).1=multiframe mode (see the timing in Section 11).
RSIORCR1.5
RSYNC I/O Select.0=RSYNC is an output (depends on RCR1.6).
1=RSYNC is an input (only valid if elastic store enabled).(note: this bit must be set to 0 when RCR2.1=0).RCR1.4
Not Assigned. Should be set to 0 when written.RCR1.3
Not Assigned. Should be set to 0 when written.FRCRCR1.2
Frame Resync Criteria.0=resync if FAS received in error 3 consecutive times.
1=resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times.
SYNCERCR1.1
Sync Enable.0=auto resync enabled.
1=auto resync disabled.
RESYNCRCR1.0
Must be cleared and set again for a subsequent resync.
DS21Q43A
SYNC/RESYNC CRITERIA Table 3-1
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONSa8SRCR2.7set to 0 to not report the Sa8 bit.
Sa7SRCR2.6
set to 0 to not report the Sa7 bit.
Sa6SRCR2.5
set to 0 to not report the Sa6 bit.
Sa5SRCR2.4
set to 0 to not report the Sa5 bit.
Sa4SRCR2.3
set to 0 to not report the Sa4 bit.
RBCSRCR2.2
Receive Side Backplane Clock Select.0=if RSYSCLK is 1.544 MHz
1=if RSYSCLK is 2.048 MHz
RESERCR2.1
Receive Side Elastic Store Enable.0=elastic store is bypassed
1=elastic store is enabled
DS21Q43A
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONODFTCR1.7
Output Data Format.0=bipolar data at TPOS and TNEG1=NRZ data at TPOS; TNEG=0
TFPTTCR1.6
Transmit Timeslot 0 Pass Through.0=FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers1=FAS bits/Sa bits/Remote Alarm sourced from TSER
T16STCR1.5
Transmit Timeslot 16 Data Select.0=sample timeslot 16 at TSER pin
1=source timeslot 16 from TS0 to TS15 registers
TUA1TCR1.4
Transmit Unframed All 1s.0=transmit data normally
1=transmit an unframed all 1s code at TPOS and TNEG
TSiSTCR1.3
Transmit International Bit Select.0=sample Si bits at TSER pin
1=source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1TCR1.2
Transmit Signaling All 1s.0=normal operation
1=force timeslot 16 in every frame to all 1s
TSMTCR1.1
TSYNC Mode Select.0=frame mode (see the timing in Section 11)
1=CAS and CRC4 multiframe mode (see the timing in Section
11)
TSIOTCR1.0
TSYNC I/O Select.0=TSYNC is an input
1=TSYNC is an output
NOTE:1. See Figure 11-9 for more details about how the Transmit Control Registers affect the operation of the
DS21Q43A.
DS21Q43A
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONSa8STCR2.7
pin; set to 0 to not source the Sa8 bit.
Sa7STCR2.6
pin; set to 0 to not source the Sa7 bit.
Sa6STCR2.5pin; set to 0 to not source the Sa6 bit.
Sa5STCR2.4
pin; set to 0 to not source the Sa5 bit.
Sa4STCR2.3
pin; set to 0 to not source the Sa4 bit.
ODMTCR2.2
Output Data Mode.0=pulses at TPOS and TNEG are one full TCLK period wide1=pulses at TPOS and TNEG are 1/2 TCLK period wide
AEBETCR2.1
Automatic E-Bit Enable.0=E-bits not automatically set in the transmit direction
1=E-bits automatically set in the transmit direction.TCR2.0
Function of RLOS/LOTC Pin.0=Receive Loss of Sync (RLOS)
1=Loss of Transmit Clock (LOTC)
DS21Q43A
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONFLBCCR1.7
Framer Loopback.0=loopback disabled1=loopback enabled
THDB3CCR1.6
Transmit HDB3 Enable.0=HDB3 disabled
1=HDB3 enabled
TG802CCR1.5
Transmit G.802 Enable. See Section 11 for details.0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26
TCRC4CCR1.4
Transmit CRC4 Enable.0=CRC4 disabled
1=CRC4 enabled
RSMCCR1.3
Receive Signaling Mode Select.0=CAS signaling mode
1=CCS signaling mode
RHDB3CCR1.2
Receive HDB3 Enable.0=HDB3 disabled1=HDB3 enabled
RG802CCR1.1
Receive G.802 Enable. See Section 11 for details.0=do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
RCRC4CCR1.0
Receive CRC4 Enable.0=CRC4 disabled
1=CRC4 enabled
FRAMER LOOPBACKWhen CCR1.7 is set to a 1, the DS21Q43A will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q43A will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. data will be transmitted as normal at TPOS and TNEG
2. data at RPOS and RNEG will be ignored
3. the receive side signals become synchronous with TCLK instead of RCLK.
DS21Q43A
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONECUSCCR2.7
Error Counter Update Select.0=update error counters once a second1=update error counters every 62.5 ms (500 frames)
VCRFSCCR2.6
VCR Function Select.0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
AAISCCR2.5
Automatic AIS Generation.0=disabled
1=enabled
ARACCR2.4
Automatic Remote Alarm Generation.0=disabled
1=enabled
RSERCCCR2.3
RSER Control.0=allow RSER to output data as received under all conditions
1=force RSER to 1 under loss of frame alignment conditions
LOTCMCCCR2.2
transmit side formatter should switch to the ever-present RCLKif the TCLK should fail to transition (see Figure 1-1).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stopsCCR2.1
Not Assigned. Should be set to 0 when written.CCR2.0
Not Assigned. Should be set to 0 when written.
AUTOMATIC ALARM GENERATIONWhen either CCR2.4 or CCR2.5 is set to 1, the DS21Q43A monitors the receive side to determine if any
of the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) re-ception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then
the DS21Q43A will either force an AIS alarm (if CCR2.5=1) or a Remote Alarm (CCR2.4=1) to be
transmitted via the TPOS and TNEG pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1
at the same time.
DS21Q43A
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTESECCR3.7
Transmit Side Elastic Store Enable.0=elastic store is bypassed.1=elastic store is enabled.
TCBFSCCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select.0=TCBRs define the operation of the TCHBLK output pin.1=TCBRs define which signaling bits are to be inserted.
TIRFSCCR3.5
Transmit Idle Registers (TIR) Function Select.0=TIRs define in which channels to insert idle code.
1=TIRs define in which channels to insert data from RSER.
ESRCCR3.4
the elastic stores to a known depth. Should be toggled after
RSYSCLK and TSYSCLK have been applied and are stable.
Must be set and cleared again for a subsequent reset. Do notleave this bit set high.CCR3.3
Not Assigned. Should be set to 0 when written.CCR3.2
Not Assigned. Should be set to 0 when written.TBCSCCR3.1
Transmit Side Backplane Clock Select.0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHzCCR3.0
Not Assigned. Should be set to 0 when written.
POWER-UP SEQUENCEOn power-up, after the supplies are stable, the DS21Q43A should be configured for operation by writing
to all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESRbit should be toggled from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic store is not
being used).
4.0 STATUS AND INFORMATION REGISTERSThere is a set of four registers that contain information on the current real time status of the DS21Q43A,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and SynchronizerStatus Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
DS21Q43A
This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set until the
user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has
occurred again or if the alarm is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS21Q43A which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written toa bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access viathe parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q43A with higher-order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports thestatus of the synchronizer in real time. This register is not latched and it is not necessary to precede a read
of this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT pin. All
four of the framers share the INT output. Each of the alarms and events in the SR1 and SR2 can be either
masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask
Register 2 (IMR2) respectively. The user can determine which framer has active interrupts by polling theInterrupt Status Register (ISR).
ISR: INTERRUPT STATUS REGISTER (see Table 1-6, Note 2)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONF3SR2ISR.7
Status of Interrupt for SR2 in Framer 3. 1=interrupt active.F3SR1ISR.6
Status of Interrupt for SR1 in Framer 3. 1=interrupt active.F2SR2ISR.5
Status of Interrupt for SR2 in Framer 2. 1=interrupt active.F2SR1ISR.4
Status of Interrupt for SR1 in Framer 2. 1=interrupt active.F1SR2ISR.3
Status of Interrupt for SR2 in Framer 1. 1=interrupt active.F1SR1ISR.2
Status of Interrupt for SR1 in Framer 1. 1=interrupt active.F0SR2ISR.1
Status of Interrupt for SR2 in Framer 0. 1=interrupt active.
DS21Q43A
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TESFRIR.7
buffer fills and a frame is deleted.
TESERIR.6
buffer empties and a frame is repeated.
LORCRIR.5
transitioned for at least 2 ms (3 ms ± 1 ms).
RESFRIR.4
buffer fills and a frame is deleted.
RESERIR.3
buffer empties and a frame is repeated.
CRCRCRIR.2
received in error.
FASRCRIR.1
are received in error.
CASRCRIR.0alignment words are received in error.
DS21Q43A
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
CSC5SSR.7CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4SSR.6CRC4 Sync Counter Bit 4.
CSC3SSR.5CRC4 Sync Counter Bit 3.
CSC2SSR.4CRC4 Sync Counter Bit 2.
CSC0SSR.3
to LSB is not accessible.
FASSASSR.2alignment at the FAS level.
CASSASSR.1
for the CAS MF alignment word.
CRC4SASSR.0
for the CRC4 MF alignment word.
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the DS21Q43A has successfully obtained synchronization at the CRC4 level. The countercan also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the DS21Q43A has been searching for synchronization at the CRC4 level. Annex B of
ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the
search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.
DS21Q43A
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1SR1.7
16 contains less than three 0s over 16 consecutive frames. This
alarm is not disabled in the CCS signaling mode.
RDMASR1.6
frame 0 has been set for two consecutive multiframes. This
alarm is not disabled in the CCS signaling mode.
RSA0SR1.5
contains all 0s.
RSLIPSR1.4
either repeated or deleted a frame of data.
RUA1SR1.3
code is received at RPOS and RNEG.
RRASR1.2
RPOS and RNEG.
RCLSR1.1detected at RPOS and RNEG.
RLOSSR1.0
to the receive E1 stream.
ALARM CRITERIA Table 4-1
DS21Q43A
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7
signaling is enabled or not) on receive multiframe boundaries.Used to alert the host that signaling data is available.
RAFSR2.6Receive Align Frame. Set every 250
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
TMFSR2.5
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
SECSR2.4
RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms
instead of once a second.
TAFSR2.3Transmit Align Frame. Set every 250
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
LOTCSR2.2
transitioned for one channel time (or 3.9
LOTC pin high if enabled via TCR2.0. Based on RCLK.
RCMFSR2.1
boundaries; will continue to be set every 2 ms on an arbitraryboundary if CRC4 is disabled.
TSLIPSR2.0
either repeated or deleted a frame of data.
DS21Q43A
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RSA1IMR1.7Receive Signaling All 1s.
0=interrupt masked1=interrupt enabled
RDMAIMR1.6Receive Distant MF Alarm.
0=interrupt masked
1=interrupt enabled
RSA0IMR1.5Receive Signaling All 0s.
0=interrupt masked
1=interrupt enabled
RSLIPIMR1.4Receive Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
RUA1IMR1.3Receive Unframed All 1s.0=interrupt masked
1=interrupt enabled
RRAIMR1.2Receive Remote Alarm.
0=interrupt masked1=interrupt enabled
RCLIMR1.1Receive Carrier Loss.
0=interrupt masked
1=interrupt enabled
RLOSIMR1.0Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
DS21Q43A
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive CAS Multiframe.
0=interrupt masked1=interrupt enabled
RAFIMR2.6Receive Align Frame.
0=interrupt masked
1=interrupt enabled
TMFIMR2.5Transmit Multiframe.
0=interrupt masked
1=interrupt enabled
SECIMR2.41-Second Timer.0=interrupt masked
1=interrupt enabled
TAFIMR2.3Transmit Align Frame.0=interrupt masked
1=interrupt enabled
LOTCIMR2.2Loss Of Transmit Clock.
0=interrupt masked1=interrupt enabled
RCMFIMR2.1Receive CRC4 Multiframe.
0=interrupt masked
1=interrupt enabled
TSLIPIMR2.0Transmit Side Elastic Store Slip.
0=interrupt masked
1=interrupt enabled
5.0 ERROR COUNT REGISTERS
There are a set of four counters in the DS21Q43A that record bipolar or code violations, errors in the
CRC4 SMF code words, E-bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either 1-second boundaries (CCR2.7=0) or every 62.5 ms
(CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 100 ms. The user can use the interruptfrom the timer to determine when to read these registers. The user has a full second (or 62.5 ms) to read
the counters before the data is lost.
DS21Q43A
5.1 BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161.Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
the DS21Q43A should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be
greater than 10**-2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB) (LSB)VCR1VCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
V15VCR1.7MSB of the 16-bit bipolar or code violation count.VCR2.0LSB of the 16-bit bipolar or code violation count.
5.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB) (LSB)CRCCR1CRCCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC9CRCCR1.1MSB of the 10-bit CRC4 error count.
CRC0CRCCR2.0LSB of the 10-bit CRC4 error count.
NOTE:
DS21Q43A
5.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the 1st bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it willcontinue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB) (LSB)EBCR1EBCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
EB9EBCR1.1MSB of the 10-bit E-Bit count.
EB0EBCR2.0LSB of the 10-bit E-Bit count.
NOTE:
1. The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
5.4 FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter isdisabled during loss of frame synchronization conditions; it is not disabled during loss of synchronization
at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a 1-second
period is 4000, this counter cannot saturate.
FASCR1: FAS BIT COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS BIT COUNT REGISTER 2 (Address=04 Hex)
(MSB) (LSB)FASCR1FASCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
FAS11FASCR1.7MSB of the 12-bit FAS error count.
FAS0FASCR2.2LSB of the 12-bit FAS error count.
NOTES:
1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 errorcounter.
