DS21Q42 ,Enhanced Quad T1 FramerFEATURES FUNCTIONAL DIAGRAM Four T1 DS1/ISDN-PRI/J1 framingtransceiversRece ive Elastic All four ..
DS21Q43AT ,Quad E1 Framerapplications§ Detects and generates AIS, remote alarm, and QUADE1remote multiframe alarmsFRAMER§ Pi ..
DS21Q43AT ,Quad E1 FramerFEATURES FUNCTIONAL DIAGRAM§ Four E1 (CEPT or PCM-30) /ISDN-PRIframing transceivers§ All four frame ..
DS21Q43AT ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
DS21Q43AT ,Quad E1 Framerfeatures have been added to the framers in theDS21Q43A over the DS2143.ADDED FEATURE SECTIONNon-mul ..
DS21Q43AT+ ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q42
Enhanced Quad T1 Framer
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
FEATURESFour T1 DS1/ISDN-PRI/J1 framing
transceiversAll four framers are fully independentEach of the four framers contain dual two-
frame elastic-store slip buffers that can connect
to asynchronous backplanes up to 8.192MHz8-bit parallel control port that can be used
directly on either multiplexed or
nonmultiplexed buses (Intel or Motorola)Programmable output clocks for Fractional T1Fully independent transmit and receive
functionalityIntegral HDLC controller with 64-byte buffers
configurable for FDL or DS0 operationGenerates and detects in-band loop codes from
1 to 8 bits in length including CSU loop codesPin compatible with DS21Q44 E1 enhanced
quad E1 framer3.3V supply with 5V tolerant I/O; low-power
CMOSAvailable in 128-pin TQFP packageIEEE 1149.1 support
FUNCTIONAL DIAGRAMceiveramer
Elastic
Store
Transmit
Formatter
Elastic
Store
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3ontrol Port
ACTUAL SIZEUAD
FRAMER
ORDERING INFORMATIONDS21Q42T0°C to +70°C
DS21Q42TN-40°C to +85°C
DESCRIPTIONThe DS21Q42 is an enhanced version of the DS21Q41B quad T1 framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor-compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All
four framers in the DS21Q42 are totally independent; they do not share a common framing synchronizer.
The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
DS21Q42
Enhanced Quad T1 Framer
DS21Q42
1. INTRODUCTIONThe DS21Q42 is a superset version of the popular DS21Q41 quad T1 framer offering the new features
listed below. All of the original features of the DS21Q41 have been retained and software created for the
original device is transferable to the DS21Q42.
NEW FEATURESAdditional hardware signaling capability including:Receive signaling re-insertion to a backplane multiframe syncAvailability of signaling in a separate PCM data streamSignaling freezingInterrupt generated on change of signaling dataFull HDLC controller with 64-byte buffers in both transmit and receive paths. Configurable for FDL
or DS0 accessPer-channel code insertion in both transmit and receive pathsAbility to monitor one DS0 channel in both the transmit and receive pathsRCL, RLOS, RRA, and RAIS alarms now interrupt on change of stateDetects AIS-CI8.192 MHz clock synthesizerPer–channel loopbackAbility to calculate and check CRC6 according to the Japanese standardAbility to pass the F–Bit position through the elastic stores in the 2.048 MHz backplane modeIEEE 1149.1 support
FEATURESFour T1 DS1/ISDN–PRI/J1 framing transceiversAll four framers are fully independentFrames to D4, ESF, and SLC–96 R formatsEach of the four framers contain dual two–frame elastic store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz8–bit parallel control port that can be used directly on either multiplexed or non–multiplexed buses
(Intel or Motorola)Extracts and inserts robbed bit signalingDetects and generates yellow (RAI) and blue (AIS) alarmsProgrammable output clocks for Fractional T1Fully independent transmit and receive functionalityGenerates and detects in–band loop codes from 1 to 8 bits in length including CSU loop codesContains ANSI one’s density monitor and enforcerLarge path and line error counters including BPV, CV, CRC6, and framing bit errorsPin compatible with DS21Q44 E1 Enhanced Quad E1 Framer3.3V-supply with 5V tolerant I/O; low power CMOSAvailable in 128–pin TQFP package
DS21Q42
FUNCTIONAL DESCRIPTIONThe receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the
receive side elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK
input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock.
The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side of the DS21Q42 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission.
READER’S NOTE:This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us
frame, there are 24 8–bit channels plus a framing bit. It is assumed that the framing bit is sent first
followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is
the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data
sheet, the following abbreviations will be used:Superframe (12 frames per multiframe) Multiframe Structure
SLC–96Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
ESFExtended Superframe (24 frames per multiframe) Multiframe Structure
B8ZSBipolar with 8 Zero Substitution
CRCCyclical Redundancy CheckTerminal Framing Pattern in D4Signaling Framing Pattern in D4
FPSFraming Pattern in ESFMultiframe
BOCBit Oriented Code
HDLCHigh Level Data Link Control
FDLFacility Data Link
DS21Q42
Figure 1-1. DS21Q42 ENHANCED QUAD T1 FRAMER
DS21Q42
TABLE OF CONTENTS
1. INTRODUCTION ..............................................................................................................................2
2. DS21Q42 PIN DESCRIPTION .........................................................................................................8
3. DS21Q42 PIN FUNCTION DESCRIPTION .................................................................................15
4. DS21Q42 REGISTER MAP.............................................................................................................22
5. PARALLEL PORT...........................................................................................................................26
6. CONTROL, ID, AND TEST REGISTERS.....................................................................................26
7. STATUS AND INFORMATION REGISTERS.............................................................................37
8. ERROR COUNT REGISTERS........................................................................................................45
9. DS0 MONITORING FUNCTION...................................................................................................48
10. SIGNALING OPERATION ............................................................................................................5010.1. PROCESSOR-BASED SIGNALING......................................................................................50
10.2. HARDWARE-BASED SIGNALING......................................................................................52
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......................................5311.1. TRANSMIT SIDE CODE GENERATION .............................................................................53
11.1.1. Simple Idle Code Insertion and Per–Channel Loopback.................................................54
11.1.2. Per-Channel Code Insertion.............................................................................................55
11.2. RECEIVE SIDE CODE GENERATION.................................................................................55
11.2.1. Simple Code Insertion .....................................................................................................55
11.2.2. Per-Channel Code Insertion............................................................................................56
12. CLOCK BLOCKING REGISTERS...............................................................................................57
13. ELASTIC STORES OPERATION ............................................................................................... 5813.1. RECEIVE SIDE........................................................................................................................58
13.2. TRANSMIT SIDE ...................................................................................................................58
13.3. MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE ..............................59
