DS21Q41BT Fast Delivery |IC PHOENIX CO.,LIMITED

DS21Q41BT ,Quad T1 Framerapplications that require more than one T1 framer on a card. TheQuad version is only slightly bigge ..
DS21Q41BT ,Quad T1 FramerFEATURES FUNCTIONAL DIAGRAM§ Four T1 DS1/ISDN-PRI framing transceivers§ All four framers are fully ..
DS21Q42 ,Enhanced Quad T1 FramerFEATURES FUNCTIONAL DIAGRAM Four T1 DS1/ISDN-PRI/J1 framingtransceiversRece ive Elastic All four ..
DS21Q43AT ,Quad E1 Framerapplications§ Detects and generates AIS, remote alarm, and QUADE1remote multiframe alarmsFRAMER§ Pi ..
DS21Q43AT ,Quad E1 FramerFEATURES FUNCTIONAL DIAGRAM§ Four E1 (CEPT or PCM-30) /ISDN-PRIframing transceivers§ All four frame ..
DS21Q43AT ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS21Q41BT
Quad T1 Framer
FEATURESFour T1 DS1/ISDN-PRI framing transceiversAll four framers are fully independentFrames to D4, ESF, and SLC-96 formats8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed busesEach of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHzExtracts and inserts robbed bit signalingFramer and payload loopbacksLarge counters for BPVs, LCVs, EXZs,
CRC6, PCVs, F-bit errors and the number of
multiframes out of syncContains ANSI 1s density monitor and
enforcerCSU loop code generator and detectorProgrammable output clocks for Fractional
T1, ISDN-PRI, Actual Size and per channel
loopback applicationsOnboard FDL support circuitryPin-compatible with DS21Q43 Quad E1
Framer5V supply; low power CMOSAvailable in 128-pin TQFPIndustrial (-40°C to +85°C) grade version
available (DS21Q41BTN)
FUNCTIONAL DIAGRAM
ACTUAL SIZE
QUAD
FRAMER
DESCRIPTION
The DS21Q41B combines four of the popular DS2141A T1 Controllers onto a single monolithic die. The
“B” designation denotes that some new features are available in the Quad version that were not available
in the single T1 device. The added features in the DS21Q41B are listed in Section 1. The DS21Q41B
offers a substantial space savings to applications that require more than one T1 framer on a card. The
Quad version is only slightly bigger than the single T1 device. All four framers in the DS21Q41B are
totally independent; they do not share a common framing synchronizer. Also, the transmit and receive
sides of each framer are totally independent. The dual two-frame elastic stores contained in each of the
four framers can be independently enabled and disabled as required. The DS21Q41B meets all of the
DS21Q41B
Quad T1 Framer
www.dalsemi.com
RECEIVE
FRAMER
TRANSMIT
FORMATTER
ELASTIC
STORE
ELASTIC
STORE
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
DS21Q41B
1.0 INTRODUCTION
The DS21Q41B Quad T1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer
#3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each
of the four framers within the DS21Q41B maintain the same register structure that appeared in the
DS2141A. The two framer select inputs (FS0 and FS1) are used to determine which framer within the
DS21Q41B is being accessed. In this manner, software written for the DS2141A can also be used with
only slight modifications, in the DS21Q41B.
Several new features have been added to the framers in the DS21Q41B over the DS2141A. Below is short
list of the new features. More details can be found in Sections 2 through 12.
ADDED FEATURESECTION
Non-multiplexed parallel control port operation2
ANSI ones density monitor (transmit and receive sides) and enforcer (transmit side only)3 and 4
CSU loop code generator3
Elastic store reset and minimum delay mode3 and 10
Divide RSYNC output by two for D4 to ESF conversion applications3
TCLK keep alive3
Indications of transmit side elastic store slip direction4
Ability to decouple the receive and transmit elastic stores10
Counting of excessive 0s (EXZs)5
DS21Q41B
DS21Q41B BLOCK DIAGRAM Figure 1-1
DS21Q41B
TRANSMIT PIN LIST Table 1-1
PINSYMBOLTYPEDESCRIPTIONTCLK0ITransmit Clock for Framer 0TCLK1ITransmit Clock for Framer 1TCLK2ITransmit Clock for Framer 2
113TCLK3ITransmit Clock for Framer 3
126TSER0ITransmit Serial Data for Framer 0TSER1ITransmit Serial Data for Framer 1TSER2ITransmit Serial Data for Framer 2TSER3ITransmit Serial Data for Framer 3
128TCHCLK0OTransmit Channel Clock from Framer 0TCHCLK1OTransmit Channel Clock from Framer 1TCHCLK2OTransmit Channel Clock from Framer 2TCHCLK3OTransmit Channel Clock from Framer 3TCHBLK0OTransmit Channel Block from Framer 0TCHBLK1OTransmit Channel Block from Framer 1TCHBLK2OTransmit Channel Block from Framer 2TCHBLK3OTransmit Channel Block from Framer 3TLCLK0OTransmit Link Clock from Framer 0TLCLK1OTransmit Link Clock from Framer 1TLCLK2OTransmit Link Clock from Framer 2
114TLCLK3OTransmit Link Clock from Framer 3TLINK0ITransmit Link Data for Framer 0TLINK1ITransmit Link Data for Framer 1TLINK2ITransmit Link Data for Framer 2
116TLINK3ITransmit Link Data for Framer 3TPOS0OTransmit Bipolar Data from Framer 0TPOS1OTransmit Bipolar Data from Framer 1TPOS2OTransmit Bipolar Data from Framer 2TPOS3OTransmit Bipolar Data from Framer 3TNEG0OTransmit Bipolar Data from Framer 0TNEG1OTransmit Bipolar Data from Framer 1TNEG2OTransmit Bipolar Data from Framer 2TNEG3OTransmit Bipolar Data from Framer 3TSYNC0I/OTransmit Sync for Framer 0TSYNC1I/OTransmit Sync for Framer 1
DS21Q41B
127TFSYNC0ITransmit Sync for Elastic Store in Framer 0TFSYNC1ITransmit Sync for Elastic Store in Framer 1TFSYNC2ITransmit Sync for Elastic Store in Framer 2TFSYNC3ITransmit Sync for Elastic Store in Framer 3
125TSYSCLK0ITransmit System Clock for Elastic Store in Framer 0TSYSCLK1ITransmit System Clock for Elastic Store in Framer 1TSYSCLK2ITransmit System Clock for Elastic Store in Framer 2TSYSCLK3ITransmit System Clock for Elastic Store in Framer 3
RECEIVE PIN LIST Table 1-2
PINSYMBOLTYPEDESCRIPTIONRCLK0IReceive Clock for Framer 0RCLK1IReceive Clock for Framer 1RCLK2IReceive Clock for Framer 2
100RCLK3IReceive Clock for Framer 3RSER0OReceive Serial Data from Framer 0RSER1OReceive Serial Data from Framer 1RSER2OReceive Serial Data from Framer 2
107RSER3OReceive Serial Data from Framer 3RCHCLK0OReceive Channel Clock from Framer 0RCHCLK1OReceive Channel Clock from Framer 1RCHCLK2OReceive Channel Clock from Framer 2
103RCHCLK3OReceive Channel Clock from Framer 3RCHBLK0OReceive Channel Block from Framer 0RCHBLK1OReceive Channel Block from Framer 1RCHBLK2OReceive Channel Block from Framer 2
104RCHBLK3OReceive Channel Block from Framer 3RLCLK0OReceive Link Clock from Framer 0RLCLK1OReceive Link Clock from Framer 1RLCLK2OReceive Link Clock from Framer 2RLCLK3OReceive Link Clock from Framer 3RLINK0OReceive Link Data from Framer 0RLINK1OReceive Link Data from Framer 1RLINK2OReceive Link Data from Framer 2RLINK3OReceive Link Data from Framer 3RPOS0IReceive Bipolar Data for Framer 0
DS21Q41B
102RPOS3IReceive Bipolar Data for Framer 3RNEG0IReceive Bipolar Data for Framer 0RNEG1IReceive Bipolar Data for Framer 1RNEG2IReceive Bipolar Data for Framer 2
101RNEG3IReceive Bipolar Data for Framer 3RSYNC0I/OReceive Sync for Framer 0RSYNC1I/OReceive Sync for Framer 1RSYNC2I/OReceive Sync for Framer 2
106RSYNC3I/OReceive Sync for Framer 3RFSYNC0OReceive Frame Sync from Framer 0RFSYNC1OReceive Frame Sync from Framer 1RFSYNC2OReceive Frame Sync from Framer 2
109RFSYNC3OReceive Frame Sync from Framer 3RMSYNC0OReceive Multiframe Sync from Framer 0RMSYNC1OReceive Multiframe Sync from Framer 1RMSYNC2OReceive Multiframe Sync from Framer 2
108RMSYNC3OReceive Multiframe Sync from Framer 3RSYSCLK0IReceive System Clock for Elastic Store in Framer 0RSYSCLK1IReceive System Clock for Elastic Store in Framer 1RSYSCLK2IReceive System Clock for Elastic Store in Framer 2
105RSYSCLK3IReceive System Clock for Elastic Store in Framer 3RLOS/LOTC0OReceive Loss of Sync/Loss of Transmit Clock from Framer 0RLOS/LOTC1OReceive Loss of Sync/Loss of Transmit Clock from Framer 1RLOS/LOTC2OReceive Loss of Sync/Loss of Transmit Clock from Framer 2
112RLOS/LOTC3OReceive Loss of Sync/Loss of Transmit Clock from Framer 3
DS21Q41B
CONTROL PORT/TEST/SUPPLY PIN LIST Table 1-3
PINSYMBOLTYPEDESCRIPTIONTESTI3-State Control for all Output and I/O PinsCSIChip SelectFS0IFramer Select 0 for Parallel Control PortFS1IFramer Select 1 for Parallel Control PortBTSIBus Type Select for Parallel Control PortWR(R/W)IWrite Input (Read/Write)RD(DS)IRead Input (Data Strobe)A0IAddress Bus Bit 0; LSA1IAddress Bus Bit 1A2IAddress Bus Bit 2A3IAddress Bus Bit 3A4IAddress Bus Bit 4A5IAddress Bus Bit 5A6 or ALE (AS)IAddress Bus Bit 6; MSB or Address Latch Enable (Address
Strobe)INTOReceive Alarm Interrupt for all Four FramersMUXINon-Multiplexed or Multiplexed Bus Select
117D0 or AD0I/OData Bus Bit 0 or Address/Data Bus Bit 0; LSB
118D1 or AD1I/OData Bus Bit 1 or Address/Data Bus Bit 1
119D2 or AD2I/OData Bus Bit 2 or Address/Data Bus Bit 2
120D3 or AD3I/OData Bus Bit 3 or Address/Data Bus Bit 3
121D4 or AD4I/OData Bus Bit 4 or Address/Data Bus Bit 4
122D5 or AD5I/OData Bus Bit 5 or Address/Data Bus Bit 5
123D6 or AD6I/OData Bus Bit 6 or Address/Data Bus Bit 6
124D7 or AD7I/OData Bus Bit 7 or Address/Data Bus Bit 7; MSBVDD-Positive Supply VoltageVDD-Positive Supply VoltageVDD-Positive Supply Voltage
111VDD-Positive Supply VoltageVSS-Signal GroundVSS-Signal GroundVSS-Signal Ground
110VSS-Signal Ground
DS21Q41B
DS21Q41B PIN DESCRIPTION Table 1-4
Transmit Clock [TCLK]. 1.544 MHz primary clock. Used to clock data through the transmit side
formatter.
Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when
the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit
side elastic store is enabled.
Transmit Channel Clock [TCHCLK]. 192 kHz clock which pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with
TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section
12 for timing details.
Transmit Bipolar Data [TPOS and TNEG]. Updated on rising edge of TCLK. Can be programmed to
output NRZ data on TPOS via the TCR1.7 control bit.
Transmit Channel Block [TCHBLK]. A user programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with TCLK when the transmit side elastic store is
disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used
such as Fractional T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications and for per-channel loopback. See Section 12 for timing details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use the transmit side
elastic store.
Transmit Link Clock [TLCLK]. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See
Section 12 for timing details.
Transmit Link Data [TLINK]. If enabled via TCR1.2, this pin will be sampled during the F-bit time on
the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs bit position (D4)
or the Z-bit position (ZBTSI). See Section 12 for timing details.
Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the
DS21Q41B. Via TCR2.2, the DS21Q41B can be programmed to output either a frame or multiframe
pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to
output double-wide pulses at signaling frames. See Section 12 for timing details.
Transmit Frame Sync [TFSYNC]. 8 kHz pulse. Only used when the transmit side elastic store is
enabled. A pulse at this pin will establish frame boundaries for the DS21Q41B. Should be tied low in
applications that do not use the transmit side elastic store. See Section 12 for timing details.
Receive Link Data [RLINK]. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one
RCLK before the start of a frame. See Section 12 for timing details.
DS21Q41B
Receive Clock [RCLK]. 1.544 MHz primary clock. Used to clock data through the receive side of the
framer.
Receive Channel Clock [RCHCLK]. 192 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data,
locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section 12 for timing
details.
Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low during
any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional
T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications and for per-channel loopback. See Section 12 for timing details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If set to output frame boundaries, then via
RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the receive side
elastic store is enabled, then this pin can be enabled to be an input at which a frame boundary pulse is
applied. See Section 12 for timing details.
Receive Frame Sync (RFSYNC). An extracted 8 kHz pulse, one RCLK wide, is output at this pin which
identifies frame boundaries. See Section 12 for timing details.
Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output should be ignored. See Section 12 for timing details.
Receive Bipolar Data Inputs [RPOS and RNEG]. Sampled on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Allowing this pin
to float can cause the device to 3-state its outputs.
Receive Loss of Sync/Loss of Transmit Clock [RLOS/LOTC]. A dual function output. If CCR1.6=0,
then this pin will toggle high when the synchronizer is searching for the T1 frame and multiframe. If
CCR1.6=1, then this pin will toggle high if the TCLK pin has not been toggled for 5 μs.
Receive Alarm Interrupt [INT]. Flags host controller during conditions defined in the Status Registers
of the four framers. User can poll the Interrupt Status Register (ISR) to determine which status register in
which framer is active (if any). Active low, open drain output.
DS21Q41B
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD (DS), ALE(AS), and WR(R/W) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input [RD] (Data Strobe [DS]).
Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.
Chip Selects [CS]. Must be low to read or write to any of the four framers.
A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [WR] (Read/Write [R/W]).
Positive Supply [VDD]. 5.0 volts ±0.5 volts.
Signal Ground [VSS]. 0.0 volts.
DS21Q41B
DS21Q41B REGISTER MAP Table 1-5
ADDRESSR/WREGISTER NAMER/WStatus Register 1R/WStatus Register 2R/WReceive Information Register 1RLine Code Violation Count Register 1RLine Code Violation Count Register 2RPath Code Violation Count Register 1(1)RPath Code Violation Count Register 2RMultiframe Out of Sync Count Register 2RReceive FDL RegisterR/WReceive FDL Match Register 1R/WReceive FDL Match Register 2R/WReceive Control Register 1R/WReceive Control Register 2R/WReceive Mark Register 1R/WReceive Mark Register 2R/WReceive Mark Register 3R/WCommon Control Register 3R/WReceive Information Register 2R/WTransmit Channel Blocking Register 1R/WTransmit Channel Blocking Register 2R/WTransmit Channel Blocking Register 3R/WTransmit Control Register 1R/WTransmit Control Register 2R/WCommon Control Register 1R/WCommon Control Register 2R/WTransmit Transparency Register 1R/WTransmit Transparency Register 2R/WTransmit Transparency Register 3R/WTransmit Idle Register 1R/WTransmit Idle Register 2R/WTransmit Idle Register 3R/WTransmit Idle Definition RegisterRReceive Signaling Register 1RReceive Signaling Register 2
DS21Q41B
ADDRESSR/WREGISTER NAMERReceive Signaling Register 5RReceive Signaling Register 6RReceive Signaling Register 7RReceive Signaling Register 8RReceive Signaling Register 9RReceive Signaling Register 10RReceive Signaling Register 11RReceive Signaling Register 12R/WReceive Channel Blocking Register 1R/WReceive Channel Blocking Register 2R/WReceive Channel Blocking Register 3R/WInterrupt Mast Register 2R/WTransmit Signaling Register 1R/WTransmit Signaling Register 2R/WTransmit Signaling Register 3R/WTransmit Signaling Register 4R/WTransmit Signaling Register 5R/WTransmit Signaling Register 6R/WTransmit Signaling Register 7R/WTransmit Signaling Register 8R/WTransmit Signaling Register 9R/WTransmit Signaling Register 10R/WTransmit Signaling Register 11R/WTransmit Signaling Register 12R/WTest Register(2)R/WTest Register(2)R/WTransmit FDL RegisterR/WInterrupt Mask Register 1
NOTES:
1. Address 25 also contains Multiframe Out of Sync Count Register 1.
2. The Test Registers are used only by the factory; these registers must be cleared (set to all 0s) on
power-up initialization to insure proper operation.
3. Any unused register address will allow the status of the interrupts to appear on the bus.
DS21Q41B
DS21Q41B FRAMER DECODE Table 1-6
FS1FS0FRAMER ACCESSED0#01#10#21#3
2.0 PARALLEL PORT
The DS21Q41B is controlled via either a non-mutliplexed (MUX=0) or multiplexed (MUX=1) by an
external microcontroller or microprocessor. The DS21Q41B can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics for more details.
3.0 CONTROL REGISTERS
The operation of each framer within the DS21Q41B is configured via a set of seven registers. Typically,
the control registers are only accessed when the system is first powered up. Once the DS21Q41B has
been initialized, the control registers will only need to be accessed when there is a change in the system
configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), and three Common Control Registers (CCR1, CCR2, and CCR3).
DS21Q41B
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) (LSB)
LCVCRFARCOOF1OOF2SYNCCCYNCTSYNCERESYNC
SYMBOLPOSITIONNAME AND DESCRIPTION
LCVCRFRCR1.7Line Code Violation Count Register Function Select.
0=do not count excessive 0s
1=count excessive 0s
ARCRCR1.6Auto Resync Criteria.
0=Resync on OOF or RCL event
1=Resync on OOF only
OOF1RCR1.5Out Of Frame Select 1.
0=2/4 frame bits in error
1=2/5 frame bits in error
OOF2RCR1.4Out Of Frame Select 2.
0=follow RCR1.5
1=2/6 frame bits in error
SYNCCRCR1.3Sync Criteria. In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern
1=cross couple Ft and Fs pattern
In ESF Framing Mode.
0=search for FPS pattern only
1=search for FPS and verify with CRC6
SYNCTRCR1.2Sync Time.
0=qualify 10 bits
1=qualify 24 bits
SYNCERCR1.1Sync Enable.
0=auto resync enabled
1=auto resync disabled
RESYNCRCR1.0Resync. When toggled from low to high, a resynchronization of
the receive side framer is initiated. Must be cleared and set again
for a subsequent resync.
DS21Q41B
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB) (LSB)
RCSZBTSIRSDWRSMRSIOD4YMFSBEMOSCRF
SYMBOLPOSITIONNAME AND DESCRIPTION
RCSRCR2.7Receive Code Select.
0=idle code (7F Hex)
1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
ZBTSIRCR2.6ZBTSI Enable.
0=ZBTSI disabled
1=ZBTSI enabled
RSDWRCR2.5RSYNC Double-Wide.
0=do not pulse double-wide in signaling frames
1=do pulse double-wide in signaling frames (note: this bit must
be set to 0 when RCR2.4=1 or when RCR2.3=1)
RSMRCR2.4RSYNC Mode Select.
0=frame mode (see the timing in Section 12)
1=multiframe mode (see the timing in Section 12)
RSIORCR2.3RSYNC I/O Select.
0=RSYNC is an output
1=RSYNC is an input (only valid if elastic store enabled) (note:
this bit must be set to 0 when CCR1.2=0)
D4YMRCR2.2D4 Yellow Alarm Select.
0=0s in bit 2 of all channels
1=a one in the S-bit position of frame 12
FSBERCR2.1PCVCR Fs Bit Error Report Enable.
0=do not report bit errors in Fsbit position; only Ft bit position
1=report bit errors in Fs bit position as well as Ft bit position
MOSCRFRCR2.0Multiframe Out of Sync Count Register Function Select.
0=count errors in the framing bit position
1=count the number of multiframes out of sync
DS21Q41B
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) (LSB)
LOTCMCTFPTTCPTRBSEGB7STLINKTBLTYEL
SYMBOLPOSITIONNAME AND DESCRIPTION
LOTCMCTCR1.7Loss Of Transmit Clock Mux Control. Determines whether
the transmit side formatter should switch to the ever present
RCLK if the TCLK input should fail to transition (see Figure 1-1
for details).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops
TFPTTCR1.6Transmit Framing Pass Through. (see note below)
0=Ft or FPS bits sourced internally
1=Ft or FPS bits sampled at TSER during F-bit time
TCPTTCR1.5Transmit CRC Pass Through. (see note below)
0=source CRC6 bits internally
1=CRC6 bits sampled at TSER during F-bit time
RBSETCR1.4Robbed Bit Signaling Enable. (see note below)
0=no signaling is inserted in any channel
1=signaling is inserted in all channels (the TTR registers can be
used to block insertion on a channel by channel basis)
GB7STCR1.3Global Bit 7 Stuffing. (see note below)
0=allow the TTR registers to determine which channels
containing all 0s are to be Bit 7 stuffed
1=force Bit 7 stuffing in all 0-byte channels regardless of how
the TTR registers are programmed
TLINKTCR1.2TLINK Select. (see note below)
0=source FDL or Fs bits from TFDL register
1=source FDL or Fs bits from the TLINK pin
TBLTCR1.1Transmit Blue Alarm. (see note below)
0=transmit data normally
1=transmit an unframed all ones code at TPOS and TNEG
TYELTCR1.0Transmit Yellow Alarm. (see note below)
0=do not transmit yellow alarm
1=transmit yellow alarm
Note: for a detailed description of how the bits in TCR1 affect the transmit side formatter of the
DS21Q41, please see Figure 12-9.
DS21Q41B
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB) (LSB)
TEST1TEST0ZBTSITSDWTSMTSIOD4YMB7ZS
SYMBOLPOSITIONNAME AND DESCRIPTION
TEST1TCR2.7Test Mode Bit 1 for Output Pins. See Table 3-1.
TEST0TCR2.6Test Mode Bit 0 for Output Pins. See Table 3-1.
ZBTSITCR2.5ZBTSI Enable.
0=ZBTSI disabled
1=ZBTSI enabled
TSDWTCR2.4TSYNC Double-Wide. (Note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0=do not pulse double-wide in signaling frames
1=do pulse double-wide in signaling frames
TSMTCR2.3TSYNC Mode Select.
0=frame mode (see the timing in Section 12)
1=multiframe mode (see the timing in Section 12)
TSIOTCR2.2TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
D4YMTCR2.1D4 Yellow Alarm Select.
0=0s in bit 2 of all channels
1=a 1 in the S-bit position of frame 12
B7ZSTCR2.0Bit 7 0 Suppression Enable.
0=no stuffing occurs
1=Bit 7 force to a 1 in channels with all 0s
OUTPUT PIN TEST MODES Table 3-1
TEST1TEST0EFFECT ON OUTPUT PINS0Operate normally1Force all output pins 3-state (including all I/O pins and parallel port pins)0Force all output pins low (including all I/O pins except parallel port pins)1Force all output pins high (including all I/O pins except parallel port pins)
DS21Q41B
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB) (LSB)
TESEODFRSAOTSCLKMRSCLKMRESEPLBFLB
SYMBOLPOSITIONNAME AND DESCRIPTION
TESECCR1.7Transmit Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
ODFCCR1.6Output Data Format.
0=bipolar data at TPOS and TNEG
1=NRZ data at TPOS; TNEG=0
RSAOCCR1.5Receive Signaling All ones.
0=allow robbed signaling bits to appear at RSER
1=force all robbed signaling bits at RSER to 1
TSCLKMCCR1.4TSYSCLK Mode Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
RSCLKMCCR1.3RSYSCLK Mode Select.
0=if RSYSCLK is 1.544 MHz
1=if RSYSCLK is 2.048 MHz
RESECCR1.2Receive Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
PLBCCR1.1Payload Loopback.
0=loopback disabled
1=loopback enabled
FLBCCR1.0Framer Loopback.
0=loopback disabled
1=loopback enabled
PAYLOAD LOOPBACK
When CCR1.1 is set to a one, the DS21Q41B will be forced into Payload LoopBack (PLB). Normally,
this loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS21Q41B
will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back; they are
reinserted by the DS21Q41B. When PLB is enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.
2. All of the receive side signals will continue to operate normally.
3. The TCHCLK and TCHBLK signals are forced low.
DS21Q41B
FRAMER LOOPBACK
When CCR1.0 is set to a 1, the DS21Q41B will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q41B will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1s code will be transmitted at TPOS and TNEG.
2. Data at RPOS and RNEG will be ignored.
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB) (LSB)
TFMTB8ZSTSLC96TFDLRFMRB8ZSRSLC96RFDL
SYMBOLPOSITIONNAME AND DESCRIPTION
TFMCCR2.7Transmit Frame Mode Select.
0=D4 framing mode
1=ESF framing mode
TB8ZSCCR2.6Transmit B8ZS Enable.
0=B8ZS disabled
1=B8ZS enabled
TSLC96CCR2.5Transmit SLC-96/Fs Bit Insertion Enable.
0=SLC-96 disabled
1=SLC-96 enabled
TFDLCCR2.4Transmit 0 Stuffer Enable.
0=0 stuffer disabled
1=0 stuffer enabled
RFMCCR2.3Receive Frame Mode Select.
0=D4 framing mode
1=ESF framing mode
RB8ZSCCR2.2Receive B8ZS Enable.
0=B8ZS disabled
1=B8ZS enabled
RSLC96CCR2.1Receive SLC-96 Enable.
0=SLC-96 disabled
1=SLC-96 enabled
RFDLCCR2.0Receive 0 Destuffer Enable.
0=0 destuffer disabled
1=0 destuffer enabled
DS21Q41B
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB) (LSB)
ESMDMESRRLOSRSMSPDETLDTLU-
SYMBOLPOSITIONNAME AND DESCRIPTION
ESMDMCCR3.7Elastic Store Minimum Delay Mode. See Section 10.3 for
details.
0=elastic stores operate at full two-frame depth
1=elastic stores operate at 32-bit depth
ESRCCR3.6Elastic Store Reset. Setting this bit from a 0 to a 1 will force the
elastic stores to a known depth. Should be toggled after
RSYSCLK and TSYSCLK have been applied and are stable.
Must be cleared and set again for a subsequent reset.
RLOSCCR3.5Function of the RLOS/LOTC Output.
0=Receive Loss of Sync (RLOS)
1=Loss of Transmit Clock (LOTC)
RSMSCCR3.4RSYNC Multiframe Skip Control. Useful in framing format
conversions from D4 to ESF.
0=RSYNC will output a pulse at every multiframe
1=RSYNC will output a pulse at every other multiframe note:
for this bit to have any affect, the RSYNC must be set to output
multiframe pulses (RCR2.4=1 and RCR2.3=0).
PDECCR3.3Pulse Density Enforcer Enable.
0=disable transmit pulse density enforcer
1=enable transmit pulse density enforcer
TLDCCR3.2Transmit Loop Down Code (001).
0=transmit data normally
1=replace normal transmitted data with loop down code
TLUCCR3.1Transmit Loop Up Code (00001).
0=transmit data normally
1=replace normal transmitted data with loop up codeCCR3.0Not Assigned. Must be set to 0 when written
LOOP CODE GENERATION
When either the CCR3.1 or CCR3.2 bits are set to one, the DS21Q41B will replace the normal
transmitted payload with either the Loop Up or Loop Down code respectively. The DS21Q41B will
overwrite the repeating loop code pattern with the framing bits. The SCT will continue to transmit the
loop codes as long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the
same time.
DS21Q41B
PULSE DENSITY ENFORCER
The DS21Q41B always examines both the transmit and receive data streams for violations of the
following rules which are required by ANSI T1.403-1989: - no more than 15 consecutive 0s - at least N
ones in each and every time window of 8 x (N +1) bits where N=1 through 23. Violations for the transmit
and receive data streams are reported in the RIR2.2 and RIR2.1 bits, respectively.
When the CCR3.3 is set to 1, the DS21Q41B will force the transmitted stream to meet this requirement
no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0
since B8ZS encoded data streams cannot violate the pulse density requirements.
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS21Q41B should be configured for operation by writing
to all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the
internal registers cannot be predicted on power-up. Finally, after the TSYSCLK and RSYSCLK inputs
are stable, the ESR bit should be toggled from a 0 to a 1 (this step can be skipped if the elastic stores are
disabled).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS21Q41B,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register 1 (RIR1), and Receive
Information Register 2 (RIR2). When a particular event has occurred (or is occurring), the appropriate bit
in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched
fashion. This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again or if the alarm(s) is still present.
The user will always precede a read of these registers with a write. The byte written to the register will
inform the DS21Q41B which bits the user wishes to read and have cleared. The user will write a byte to
one of these four registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions
he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read
register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the
read register will not be updated and the previous value will be held. A write to the status and information
registers will be immediately followed by a read of the same register. The read result should be logically
AND’ed with the mask byte that was just written and this value should be written back into the same
register to insure that the bit does indeed clear. This second write is necessary because the alarms and
events in the status registers occur asynchronously in respect to their access via the parallel port. The
write-read-write scheme is unique to the four status registers and it allows an external microcontroller or
microprocessor to individually poll certain bits without disturbing the other bits in the register. This
operation is key in controlling the DS21Q41B with higher-order software languages.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT output pin.
All four framers within the DS21Q41B share the INT output. Each of the alarms and events in the SR1
and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1
(IMR1) and Interrupt Mask Register 2 (IMR2) respectively. The user can determine which framer has
active interrupts by polling the Interrupt Status Register (ISR).
DS21Q41B
ISR: INTERRUPT STATUS REGISTER (any unused address)
(MSB) (LSB)
F3SR2F3SR1F2SR2F2SR1F1SR2F1SR1F0SR2F0SR1
SYMBOLPOSITIONNAME AND DESCRIPTION
F3SR2ISR.7Status of Interrupt for SR2 in Framer 3.
1=interrupt active.
F3SR1ISR.6Status of Interrupt for SR1 in Framer 3.
1=interrupt active.
F2SR2ISR.5Status of Interrupt for SR2 in Framer 2.
1=interrupt active.
F2SR1ISR.4Status of Interrupt for SR1 in Framer 2.
1=interrupt active.
F1SR2ISR.3Status of Interrupt for SR2 in Framer 1.
1=interrupt active.
F1SR1ISR.2Status of Interrupt for SR1 in Framer 1.
1=interrupt active.
F0SR2ISR.1Status of Interrupt for SR2 in Framer 0.
1=interrupt active.
F0SR1ISR.0Status of Interrupt for SR1 in Framer 0.
1=interrupt active.
DS21Q41B
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB) (LSB)
COFA8ZD16ZDRESFRESESEFEB8ZSFBE
SYMBOLPOSITIONNAME AND DESCRIPTION
COFARIR1.7Change of Frame Alignment. Set when the last resync resulted
in a change of frame or multiframe alignment.
8ZDRIR1.6Eight 0 Detect. Set when a string of at least eight consecutive 0s
(regardless of the length of the string) have been received at
RPOS and RNEG.
16ZDRIR1.5Sixteen 0 Detect. Set when a string of at least 16 consecutive 0s
(regardless of the length of the string) have been received at
RPOS and RNEG.
RESFRIR1.4Receive Elastic Store Full. Set when the receive elastic store
buffer fills and a frame is deleted.
RESERIR1.3Receive Elastic Store Empty. Set when the receive elastic store
buffer empties and a frame is repeated.
SEFERIR1.2Severely Errored Framing Event. Set when 2 out of 6 framing
bits (Ft or FPS) are received in error.
B8ZSRIR1.1B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOS and RNEG independent of whether the B8ZS
mode is selected or not via CCR2.6. Useful for automatically
setting the line coding.
FBERIR1.0Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit
is received in error.
DS21Q41B
RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB) (LSB)
RLOSCRCLCTESFTESETSLIPRBLCRPDVTPDV
SYMBOLPOSITIONNAME AND DESCRIPTION
RLOSCRIR2.7Receive Loss of Sync Clear. Set when the framer achieves
synchronization; will remain set until read.
RCLCRIR2.6Receive Carrier Loss Clear. Set when the carrier signal is
restored; will remain set until read.
TESFRIR2.5Transmit Elastic Store Full. Set when the transmit elastic store
buffer fills and a frame is deleted.
TESERIR2.4Transmit Elastic Store Empty. Set when the transmit elastic
store buffer empties and a frame is repeated.
TSLIPRIR2.3Transmit Elastic Store Slip Occurrence. Set when the transmit
elastic store has either repeated or deleted a frame.
TBLCRIR2.2Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is
no longer detected; will remain set until read.
RPDVRIR2.1Receive Pulse Density Violation. Set when the receive data
stream does not meet the ANSI T1.403 requirements for pulse
density.
TPDVRIR2.0Transmit Pulse Density Violation. Set when the transmit data
stream does not meet the ANSI T1.403 requirements for pulse
density.
DS21Q41B
SR1: STATUS REGISTER 1 (Address=20 Hex)
(MSB) (LSB)
LUPLDNLOTCRSLIPRBLRYELRCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPSR1.7Loop Up Code Detected. Set when the repeating ...00001...
loop up code is being received.
LDNSR1.6Loop Down Code Detected. Set when the repeating ...001...
loop down code is being received.
LOTCSR1.5Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 5.2 μs). Will force the
RLOS/LOTC pin high if enabled via CCR1.6. Also will force
transmit side formatter to switch to RCLK if so enabled via
TCR1.7. Based on RCLK.
RSLIPSR1.4Receive Elastic Store Slip Occurrence. Set when the receive
elastic store has either repeated or deleted a frame.
RBLSR1.3Receive Blue Alarm. Set when an unframed all ones code is
received at RPOS and RNEG.
RYELSR1.2Receive Yellow Alarm. Set when a yellow alarm is received at
RPOS and RNEG.
RCLSR1.1Receive Carrier Loss. Set when 192 consecutive 0s have been
detected at RPOS and RNEG.
RLOSSR1.0Receive Loss of Sync. Set when the device is not synchronized
to the receive T1 stream.
DS21Q41B
DS21Q41B ALARM SET & CLEAR CRITERIA Table 4-2
ALARMSET CRITERIACLEAR CRITERIA
Blue Alarm (AIS)
(see note 1 below)
when over a 3 ms window, five
or less 0s are received
when over a 3 ms window, six or
more 0s are received
Yellow Alarm (RAI)
1. D4 bit 2 mode (RCR2.2=0)
when bit 2 of 256 consecutive
channels is set to 0 for at least
254 occurrences
when bit 2 of 256 consecutive
channels is set to 0 for less than
254 occurrences
2. D4 12th F-bit mode
(RCR2.2=1; this mode is also
referred to as the "Japanese
Yellow Alarm")
when the 12th framing bit is set
to one for two consecutive
occurrences
when the 12th framing bit is set to
0 for two consecutive occurrences
3. ESF modewhen 16 consecutive patterns of
00FF appear in the FDL
when 14 or less patterns of 00FF
hex out of 16 possible appear in
the FDL
Red Alarm (RCL)
(this alarm is also referred to
as Loss of Signal)
when 192 consecutive 0s are
received
when 14 or more ones out of 112
possible bit positions are received
starting with the first one received
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm
detectors should be able to operate properly in the presence of a 10-3 error rate and they should not
falsely trigger on a framed all 1s signal. The blue alarm criteria in the DS21Q41B has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
2. ANSI specifications use a different nomenclature than the DS21Q41B does; the following terms are
equivalent:
RBL=AIS
RCL=LOS
RLOS=LOF
RYEL=RAI
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard “loop up” or “loop down” codes are being
received by the DS21Q41B. When a loop up code has been received for 5 seconds, the CPE is expected
to loop the recovered data (without correcting BPVs) back to the source. The loop down code indicates
that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS21Q41B will detect the loop up/down codes in both framed and unframed circumstances with bit error
rates as high as 10**-2. The loop code detector has a nominal integration period of 48 ms. Hence, after
about 48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it
is recommend that the software poll the DS21Q41B every 100 ms to 500 ms until 5 seconds has elapsed
to insure that the code is continuously present.
DS21Q41B
SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB) (LSB)
RMFTMFSECRFDLTFDLRMTCHRAFLORC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7Receive Multiframe. Set on receive multiframe boundaries.
TMFSR2.6Transmit Multiframe. Set on transmit multiframe boundaries.
SECSR2.51-Second Timer. Set on increments of 1 second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds.
RFDLSR2.4Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
TFDLSR2.3Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
RMTCHSR2.2Receive FDL Match Occurrence. Set when the RFDL matches
either RFDLM1 or RFDLM2.
RAFSR2.1Receive FDL Abort. Set when eight consecutive 1s are received
in the FDL.
LORCSR2.0Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 μs (3 μs ± 1 μs).
DS21Q41B
IMR1: INTERRUPT MASK REGISTER (Address=7F Hex)
(MSB) (LSB)
LUPLDNLOTCSLIPRBLRYELRCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPIMR1.7Loop Up Code Detected.
0=interrupt masked
1=interrupt enabled
LDNIMR1.6Loop Down Code Detected.
0=interrupt masked
1=interrupt enabled
LOTCIMR1.5Loss of Transmit Clock.
0=interrupt masked
1=interrupt enabled
SLIPIMR1.4Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
RBLIMR1.3Receive Blue Alarm.
0=interrupt masked
1=interrupt enabled
RYELIMR1.2Receive Yellow Alarm.
0=interrupt masked
1=interrupt enabled
RCLIMR1.1Receive Carrier Loss.
0=interrupt masked
1=interrupt enabled
RLOSIMR1.0Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
DS21Q41B
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB) (LSB)
RMFTMFSECRFDLTFDLRMTCHRAFLORC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive Multiframe.
0=interrupt masked
1=interrupt enabled
TMFIMR2.6Transmit Multiframe.
0=interrupt masked
1=interrupt enabled
SECIMR2.5One Second Timer.
0=interrupt masked
1=interrupt enabled
RFDLIMR2.4Receive FDL Buffer Full.
0=interrupt masked
1=interrupt enabled
TFDLIMR2.3Transmit FDL Buffer Empty.
0=interrupt masked
1=interrupt enabled
RMTCHIMR2.2Receive FDL Match Occurrence.
0=interrupt masked
1=interrupt enabled
RAFIMR2.1Receive FDL Abort.
0=interrupt masked
1=interrupt enabled
LORCIMR2.0Loss of Receive Clock.
0=interrupt masked
1=interrupt enabled
DS21Q41B
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS21Q41B that record bipolar violations, excessive 0s, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on 1-second boundaries as
determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data is
lost. All three counters will saturate at their respective maximum counts and they will not rollover (note:
only the Line Code Violation Count Register has the potential to overflow).
5.1 Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 High (LCVCR1) is the most significant word and LCVCR2 is the
least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive 0s. See Table 5-1 for details of exactly what the LCVCRs count. If the
B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter is
always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address=23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address=24 Hex)
(MSB) (LSB)
LCV15LCV14LCV13LCV12LCV11LCV10LCV9LCV8LCVCR1
LCV7LCV6LCV5LCV4LCV3LCV2LCV1LCV0LCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CV16LCVCR1.7MSB of the 16-bit code violation count
CV0LCVCR2.0LSB of the 16-bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5-1
COUNT EXCESSIVE
0S (RCR1.7)
B8ZS ENABLED
(CCR2.2)
WHAT IS COUNTED IN THE LCVCRsnoBPVs
yesnoBPVs + 16 consecutive 0syesBPVs (B8ZS code words not counted)
yesyesBPVs + 8 consecutive 0s
5.2 Path Code Violation Count Register (PCVCR)
When the receive side of the DS21Q41B is set to operate in the ESF framing mode (CCR2.3=1), PCVCR
will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to
operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing
bit position. Via the RCR2.1 bit, the DS21Q41B can be programmed to also report errors in the Fs
framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1)
conditions. See Table 5-2 for a detailed description of exactly what errors the PCVCR counts.
DS21Q41B
PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address=25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address=26 Hex)
(MSB) (LSB)
(note 1)(note 1)(note 1)(note 1)CRC/FB11CRC/FB10CRC/FB9CRC/FB8PCVCR1
CRC/FB7CRC/FB6CRC/FB5CRC/FB4CRC/FB3CRC/FB2CRC/FB1CRC/FB0PCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC/FB11PCVCR1.3MSB of the 12-bit CRC6 error or frame bit error count (note 2)
CRC/FB0PCVCR2.0LSB of the 12-bit CRC6 error or frame bit error count (note 2)
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register.
2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in
the framing bit position (in the D4 framing mode; CCR2.3=0).
PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 5-2
FRAMING MODE
(CCR2.3)
COUNT Fs ERRORS
(RCR2.1)
WHAT IS COUNTED IN THE PCVCRsnoerrors in the Ft patternyeserrors in both the Ft and Fs patterns
ESFdon't careerrors in the CRC6 code words
5.3 Multiframes Out of Sync Count Register (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)
conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS=1)
conditions. See Table 5-3 for a detailed description of what the MOSCR is capable of counting.

Partno	Mfg	Dc	Qty	Available	Descript
DS21Q41BT		N/a	20	avai	Quad T1 Framer
DS21Q41BT	DALLAS	N/a	54	avai	Quad T1 Framer