DS21Q552 ,Quad T1 Transceiver (5V/3.3V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q554 ,Quad E1 Transceiver (5V/3.3V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q554 ,Quad E1 Transceiver (5V/3.3V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q554B+ ,Quad T1/E1 Transceiver (3.3V, 5.0V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q554N ,Quad E1 Transceiver (5V/3.3V)Applications • 256–lead MCM BGA package (27mm X 27mm) • Low Power 5V CMOS or Low Power 3.3V CMOS wi ..
DS21Q55DK ,Quad T1/E1/J1 Transceiver Design Kit Daughter CardFEATURES The DS21Q55DK is an easy-to-use evaluation board Demonstrates Key Functions of DS21Q55 Q ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS21Q352-DS21Q354-DS21Q552-DS21Q554
Quad T1/E1 Transceiver (3.3V,5.0V)
DALLAS SEMICONDUCTORPreliminary
Quad T1/E1 Transceiver (5V)
Quad T1/E1 Transceiver (3.3V)
DS21Q552/DS21Q554
DS21Q352/DS21Q354
FEATURESFour (4) Completely Independent T1 or E1 TransceiversIn One Small 27mm x 27mm PackageEach Transceiver Contains a Short & Long Haul Line InterfacePlus a Full Featured Framer with Alarm Detection/Generation,Elastic Stores, Hardware Based Signaling Support, Per DS0Channel Control and HDLC ControllerEach Multi-Chip Module (MCM) Contains Four Die of:DS21352 (DS21Q352)DS21552 (DS21Q552)DS21354 (DS21Q354)DS21554 (DS21Q554)Selection Guide: Supply Device T1 3.3V DS21Q352T1 5V DS21Q552E1 3.3V DS21Q354E1 5V DS21Q554See the Specific DS21352/DS21552 and DS21354/DS21554Data Sheets for Details on their Feature Set and OperationAll Four T1 or E1 Transceivers Can be Concatenated into a Single8.192MHz Backplane Data StreamIEEE 1149.1 JTAG-Boundary Scan ArchitectureDS21Q352/DS21Q552 and DS21Q354/DS21Q554 are Pin Compatibleto Allow the Same Footprint to Support T1 and E1 Applications256–lead MCM BGA package (27mm X 27mm)Low Power 5V CMOS or Low Power 3.3V CMOS with 5V
Tolerant Input & Outputs
DESCRIPTIONThe Quad T1 and E1 Transceiver MCMs offer a high density packaging arrangement for the
DS21352/DS21552 T1 Single-Chip Transceivers and the DS21354/DS21554 E1 Single-Chip Transceivers.
Four silicon die of one of these devices is packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1. All of the functions available on the DS21352/DS21552 and
DS21354/DS21554 are also available in the MCM packaged version however in order to minimize package
size, some signals have been deleted. These differences are detailed in Table 1.
This data sheet describes the electrical connections and the mechanical dimensions only. Please see the
DS21352/DS21552 and DS21354/DS21554 data sheets for full details on all of the features and the
operating characteristics of the device.
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
Changes from Normal DS21Q352/DS21Q552 & DS21Q354/DS21Q554 Configuration Table 11. The following signals are not available: XTALD / 8XCLK / TESO / TDATA / RCL / RDATA
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIG
TSSYNC
TSYSCLK
TSER
TSIG
RMSYMC
TCLK
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0/AD0 to D7/AD7
A0 to A7/ALE
RD*
WR*
BTS
CS*
MUX
TEST
Signals Not Connected & Left Open Circuited
Include: 8XCLK / XTALD / RDATA / RCL
SCT # 1
DS21352 / DS21552 /
DS21354 / DS21554
RSIGF
RTIP
RRING
TTIP
TRING
RSER
RSYSCLK
RSYNC
TCHBLK
TCHCLK
TLINK
TLCLK
LIUC
MCLK
RFSYNC
TESO
TDATA
TSYNC
RCLKO
RPOSO
RNEGO
RNEGI
RPOSI
RCLKI
TCLKO
TCLKI
TPOSO
TNEGO
TPOSI
TNEGI
FMS
See Connecting Page
DVSS
RVSS
TVSS
DVDD
TVDD
RVDD
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIG
TSSYNC
TSYSCLK
TSER
TSIG
RMSYMC
TCLK
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0/AD0 to D7/AD7
A0 to A7/ALE
RD*
WR*
BTS
CS*
MUX
TEST
Signals Not Connected & Left Open Circuited
Include: 8XCLK / XTALD / RDATA / RCL
SCT # 2
DS21352 / DS21552 /
DS21354 / DS21554
RSIGF
RTIP
RRING
TTIP
TRING
RSER
RSYSCLK
RSYNC
TCHBLK
TCHCLK
TLINK
TLCLK
LIUC
MCLK
RFSYNC
TESO
TDATA
TSYNC
RCLKO
RPOSO
RNEGO
RNEGI
RPOSI
RCLKI
TCLKO
TCLKI
TPOSO
TNEGO
TPOSI
TNEGI
FMS
See Connecting Page
See Connecting Page
DVSS
RVSS
TVSS
DVDD
TVDD
RVDD
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIG
TSSYNC
TSYSCLK
TSER
TSIG
RMSYMC
TCLK
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0/AD0 to D7/AD7
A0 to A7/ALE
RD*
WR*
BTS
CS*
MUX
TEST
Signals Not Connected & Left Open Circuited
Include: 8XCLK / XTALD / RDATA / RCL
SCT # 3
DS21352 / DS21552 /
DS21354 / DS21554
RSIGF
RTIP
RRING
TTIP
TRING
RSER
RSYSCLK
RSYNC
TCHBLK
TCHCLK
TLINK
TLCLK
LIUC
MCLK
RFSYNC
TESO
TDATA
TSYNC
RCLKO
RPOSO
RNEGO
RNEGI
RPOSI
RCLKI
TCLKO
TCLKI
TPOSO
TNEGO
TPOSI
TNEGI
FMS
See Connecting Page
See Connecting Page
DVSS
RVSS
TVSS
DVDD
TVDD
RVDD
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIG
TSSYNC
TSYSCLK
TSER
TSIG
RMSYMC
TCLK
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0/AD0 to D7/AD7
A0 to A7/ALE
RD*
WR*
BTS
CS*
MUX
TEST
Signals Not Connected & Left Open Circuited
Include: 8XCLK / XTALD / RDATA / RCL
SCT # 4
DS21352 / DS21552 /
DS21354 / DS21554
RSIGF
RTIP
RRING
TTIP
TRING
RSER
RSYSCLK
RSYNC
TCHBLK
TCHCLK
TLINK
TLCLK
LIUC
MCLK
RFSYNC
TESO
TDATA
TSYNC
RCLKO
RPOSO
RNEGO
RNEGI
RPOSI
RCLKI
TCLKO
TCLKI
TPOSO
TNEGO
TPOSI
TNEGI
FMS
See Connecting Page
DVSS
RVSS
TVSS
DVDD
TVDD
RVDD
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
Lead Description Sorted by Symbol Table 2
LeadSymbolI/ODescription8MCLK1O8.192 MHz Clock Based on RCLK1.
H178MCLK2O8.192 MHz Clock Based on RCLK2.8MCLK3O8.192 MHz Clock Based on RCLK3.
V138MCLK4O8.192 MHz Clock Based on RCLK4.A0IAddress Bus Bit 0 (lsb).
L17A1IAddress Bus Bit 1.A2IAddress Bus Bit 2.A3IAddress Bus Bit 3.A4IAddress Bus Bit 4.A5IAddress Bus Bit 5.A6IAddress Bus Bit 6.A7/ALEIAddress Bus Bit 7 (msb) / Address Latch Enable.BTSIBus Type Select (0 = Intel / 1 = Motorola),CI1ICarry Input for Interleaved Bus Operation for SCT1.
F18CI2ICarry Input for Interleaved Bus Operation for SCT2.CI3ICarry Input for Interleaved Bus Operation for SCT3.
T20CI4ICarry Input for Interleaved Bus Operation for SCT4.CO1OCarry Output for Interleaved Bus Operation for SCT1.
B17CO2OCarry Output for Interleaved Bus Operation for SCT2.CO3OCarry Output for Interleaved Bus Operation for SCT3.
J20CO4OCarry Output for Interleaved Bus Operation for SCT4.CS1*IChip Select for SCT1.
A14CS2*IChip Select for SCT2.CS3*IChip Select for SCT3.
K17CS4*IChip Select for SCT4.
U11D0/AD0I/OData Bus Bit 0/ Address/Data Bus Bit 0 (lsb).
J19D1/AD1I/OData Bus Bit 1/ Address/Data Bus Bit 1.
W15D2/AD2I/OData Bus Bit 2/Address/Data Bus Bit 2.D3/AD3I/OData Bus Bit 3/Address/Data Bus Bit 3.D4/AD4I/OData Bus Bit 4/Address/Data Bus Bit 4.D5/AD5I/OData Bus Bit 5/Address/Data Bus Bit 5.D6/AD6I/OData Bus Bit 6/Address/Data Bus Bit 6.D7/AD7I/OData Bus Bit 7/Address/Data Bus Bit 7 (msb).DVDD1–Digital Positive Supply.DVDD1–Digital Positive Supply.DVDD1–Digital Positive Supply.DVDD1–Digital Positive Supply.
B12DVDD2–Digital Positive Supply.
C12DVDD2–Digital Positive Supply.
C16DVDD2–Digital Positive Supply.
D18DVDD2–Digital Positive Supply.DVDD3–Digital Positive Supply.DVDD3–Digital Positive Supply.DVDD3–Digital Positive Supply.DVDD3–Digital Positive Supply.
G20DVDD4–Digital Positive Supply.
M17DVDD4–Digital Positive Supply.
M20DVDD4–Digital Positive Supply.
P18DVDD4–Digital Positive Supply.DVSS1–Digital Signal Ground.DVSS1–Digital Signal Ground.DVSS1–Digital Signal Ground.
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
A17DVSS2–Digital Signal Ground.
A20DVSS2–Digital Signal Ground.
B11DVSS2–Digital Signal Ground.
C13DVSS2–Digital Signal Ground.DVSS3–Digital Signal Ground.DVSS3–Digital Signal Ground.DVSS3–Digital Signal Ground.DVSS3–Digital Signal Ground.
H20DVSS4–Digital Signal Ground
L20DVSS4–Digital Signal Ground
N17DVSS4–Digital Signal Ground
U13DVSS4–Digital Signal GroundINT*OInterrupt for all four SCTs.
Y15JTCLKIJTAG Clock.JTDIIJTAG Data Input.
H18JTDO2OJTAG Data Output from SCT2.
V17JTDO3OJTAG Data Output from SCT3.
V19JTDO4OJTAG Data Output from SCT4.
W13JTMSIJTAG Test Mode Select.
V18JTRST*IJTAG Reset.LIUCILine Interface Connect for all Four SCTs.MCLK1IMaster Clock for SCT1 and SCT3.
W20MCLK2IMaster Clock for SCT2 and SCT4.
U10MUXIMux Bus Select.RCHBLK1OReceive Channel Block for SCT1.
G17RCHBLK2OReceive Channel Block for SCT2.RCHBLK3OReceive Channel Block for SCT3.
Y12RCHBLK4OReceive Channel Block for SCT4.RCHCLK1OReceive Channel Clock for SCT1.
D14RCHCLK2OReceive Channel Clock for SCT2.RCHCLK3OReceive Channel Clock for SCT3.
U14RCHCLK4OReceive Channel Clock for SCT4.RCLK1OReceive Clock Output from the Framer on SCT1.
B13RCLK2OReceive Clock Output from the Framer on SCT2.RCLK3OReceive Clock Output from the Framer on SCT3.
M18RCLK4OReceive Clock Output from the Framer on SCT4.RCLKI1IReceive Clock Input for the LIU on SCT1.
A15RCLKI2IReceive Clock Input for the LIU on SCT2.RCLKI3IReceive Clock Input for the LIU on SCT3.
R17RCLKI4IReceive Clock Input for the LIU on SCT4.RCLKO1OReceive Clock Output from the LIU on SCT1.
C14RCLKO2OReceive Clock Output from the LIU on SCT2.RCLKO3OReceive Clock Output from the LIU on SCT3.
T17RCLKO4OReceive Clock Output from the LIU on SCT4.RD*(DS*)IRead Input (Data Strobe)RFSYNC1OReceive Frame Sync (before the receive elastic store) for SCT1.
D17RFSYNC2OReceive Frame Sync (before the receive elastic store) for SCT2.RFSYNC3OReceive Frame Sync (before the receive elastic store) for SCT3.
V14RFSYNC4OReceive Frame Sync (before the receive elastic store) for SCT4.RLCLK1OReceive Link Clock for SCT1.
A12RLCLK2OReceive Link Clock for SCT2.RLCLK3OReceive Link Clock for SCT3.
K18RLCLK4OReceive Link Clock for SCT4.RLINK1OReceive Link Data for SCT1.
A13RLINK2OReceive Link Data for SCT2.RLINK3OReceive Link Data for SCT3.
