DS21FF42+ Fast Delivery |IC PHOENIX CO.,LIMITED

DS21FF42+ ,4 x 4 16 Channel T1 Framer / 4 x 3 12 Channel T1 FramerFEATURESP 300-pin MCM 1.27mm pitch BGA package 16 or 12 completely independent T1 framers(27mm x ..
DS21FF44 ,4x3 Twelve Channel E1 Framer / 4x4 Sixteen Channel E1 FramerAPPLICATIONS 16 or 12 completely independent E1 framers DSLAMsin one small 27mm x 27mm package ..
DS21Q348 ,3.3V E1/T1/J1 line interfaceFEATURES PIN CONFIGURATIONS 111 PRELMINARY Complete E1, T1, or J1 Line Interface Unit 44TOP VIEW ( ..
DS21Q348N ,3.3V E1/T1/J1 line interfacePIN DESCRIPTION Complete E1, T1, or J1 line interface unit44(LIU) Supports both long-haul and sho ..
DS21Q352 ,Quad T1/E1 Transceiver (3.3V,5.0V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q352B+ ,Quad T1/E1 Transceiver (3.3V, 5.0V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS21FF42+
4 x 4 16 Channel T1 Framer / 4 x 3 12 Channel T1 Framer
FEATURESP16 or 12 completely independent T1 framers
in one small 27mm x 27mm, 1.27mm pitch
BGA packageEach multichip module (MCM) contains
four (FF) or three (FT) DS21Q42 dieEach quad framer can be concatenated into a
single 8.192MHz backplane data streamIEEE 1149.1 JTAG-Boundary Scan
ArchitectureDS21FF42 and DS21FT42 are pin
compatible with DS21FF44 and DS21FT44,
respectively, to allow the same footprint to
support T1 and E1 applications300-pin MCM 1.27mm pitch BGA package
(27mm x 27mm)Low-power 3.3V CMOS with 5V tolerant
input and outputs
APPLICATIONSDSLAMsMultiplexers/DemultiplexersSwitchesHigh-Density Line Cards
ORDERING INFORMATION
PARTCHANNELPIN-PACKAGETEMP RANGE
DS21FT4212300 BGA, 27mm x 27mm0°C to +70°C
DS21FT42N12300 BGA, 27mm x 27mm-40°C to +85°C
DS21FF4216300 BGA, 27mm x27mm0°C to +70°C
DS21FF42N16300 BGA, 27mm x 27mm-40°C to +85°C
1. MULTICHIP MODULE DESCRIPTION
The 4 x 4 and 4 x 3 multichip modules (MCM) offer a high-density packaging arrangement for the
DS21Q42 T1 Enhanced Quad Framer. Either three (DS21FT42) or four (DS21FF42) silicon die of these
devices is packaged in an MCM with the electrical connections as shown in Figure 1-1.
All of the functions available on the DS21Q42 are also available in the MCM packaged version.
However, in order to minimize package size, some signals have been deleted or combined. These
differences are detailed in Table 1-1. In the 4 x 3 (FT) version, the fourth quad framer is not populated
and hence all of the signals to and from this fourth framer are absent and should be treated as No
Connects (NC). Table 2-1 lists all of the signals on the MCM and it also lists the absent signals for the
4 x 3.
The availability of both a 12-channel and a 16-channel version allow the maximum framer density with
the lowest cost. For example, in a T3 application, two devices (one DS21FF42 and one DS21FT42)
provide 28 framers without the additional cost and power consumption of any unused framers that appear
in an octal approach.
DS21FT42/DS21FF42
4 x 3 12-Channel T1 Framer
4 x 4 16-Channel T1 Framer

DS21FT42/DS21FF42
CHANGES FROM NORMAL DS21Q42 CONFIGURATION Table 1-1
1) TSYSCLK and RSYSCLK are tied together.
2) The following signals are not available:
RFSYNC/RLCLK/RLINK/RCHCLK/RMSYNC/RLOS/LOTC/TCHBLK/TLCLK/TLINK/TCHCLK
DS21FF42/DS21FT42 SCHEMATIC Figure 1-1
8MCLK
CLKSI
RCLK1/2/3/4
RPOS1/2/3/4
RNEG1/2/3/4
RSER1/2/3/4
RSIG1/2/3/4
RSYNC1/2/3/4
RSYSCLK1/2/3/4
TCLK1/2/3/4
TNEG1/2/3/4
TPOS1/2/3/4
TSER1/2/3/4
TSIG1/2/3/4
TSSYNC1/2/3/4
TSYNC1/2/3/4
TSYSCLK1/2/3/4
TLINK0/1/2/3
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
FMS
D0 to D7
A0 to A7
RD*
WR*
BTS
MUX
CS*
FS0/FS1
TEST
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHCLK
RMSYNC
RFSYNC
TLCLK
TCHCLK
TCHBLK
DS21Q42 # 1
RCLK5/6/7/8
RPOS5/6/7/8
RNEG5/6/7/8
RSER5/6/7/8
RSIG5/6/7/8
RSYNC5/6/7/8
RSYSCLK5/6/7/8
TCLK5/6/7/8
TNEG5/6/7/8
TPOS5/6/7/8
TSER5/6/7/8
TSIG5/6/7/8
TSSYNC5/6/7/8
TSYNC5/6/7/8
TSYSCLK5/6/7/8
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0 to D7
A0 to A7
RD*
WR*
BTS
MUX
CS*
FS0/FS1
TEST
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHCLK
RMSYNC
RFSYNC
TLCLK
TCHCLK
TCHBLK
8MCLK
DS21Q42 # 2
See Connecting Page
RCHBLK5/6/7/8
RCHBLK1/2/3/4
DVDD
DVSS
DVSS
TLINK0/1/2/3
FMS
CLKSI
DVSS
DVSSDVDD
DS21FT42/DS21FF42
DS21FF42/DS21FT42 SCHEMATIC Figure 1-1 (continued)
CLKSI
RCLK9/10/11/12
RPOS9/10/11/12
RNEG9/10/11/12
RSER9/10/11/12
RSIG9/10/11/12
RSYNC9/10/11/12
RSYSCLK9/10/11/12
TCLK9/10/11/12
TNEG9/10/11/12
TPOS9/10/11/12
TSER9/10/11/12
TSIG9/10/11/12
TSSYNC9/10/11/12
TSYNC9/10/11/12
TSYSCLK9/10/11/12
TLINK0/1/2/3
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
FMS
D0 to D7
A0 to A7
RD*
WR*
BTS
MUX
CS*
FS0/FS1
TEST
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHCLK
RMSYNC
RFSYNC
TLCLK
TCHCLK
TCHBLK
8MCLK
DS21Q42 # 3
RCLK13/14/15/16
RPOS13/14/15/16
RNEG13/14/15/16
RSER13/14/15/16
RSIG13/14/15/16
RSYNC13/14/15/16
RSYSCLK13/14/15/16
TCLK13/14/15/16
TNEG13/14/15/16
TPOS13/14/15/16
TSER13/14/15/16
TSIG13/14/15/16
TSSYNC13/14/15/16
TSYNC13/14/15/16
TSYSCLK13/14/15/16
JTDO
JTDI
JTCLK
JTMS
JTRST
INT*
D0 to D7
A0 to A7
RD*
WR*
BTS
MUX
CS*
FS0/FS1
TEST
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RLCLK
RCHCLK
RMSYNC
RFSYNC
TLCLK
TCHCLK
TCHBLK
8MCLK
DS21Q42 # 4
RCHBLK13/14/15/16
RCHBLK9/10/11/12
DVDD
DVSS
DVSS
TLINK0/1/2/3
FMS
CLKSI
DVSS
DVSSDVDD
See Connecting Page
jtdot
jtdof
The Fourth Quad Framer
is Not Populated
on the 12 Channel
DS21FT42
DS21FT42/DS21FF42
TABLE OF CONTENTS
FEATURES................................................................................................................................................1MULTICHIP MODULE (MCM) DESCRIPTION.........................................................................1MCM PIN DESCRIPTION................................................................................................................6DS21FF42 (4 X 4) PCB LAND PATTERN.....................................................................................13DS21FT42 (4 X 3) PCB LAND PATTERN.....................................................................................14DS21Q42 FEATURES......................................................................................................................15DS21Q42 INTRODUCTION...........................................................................................................15DS21Q42 PIN FUNCTION DESCRIPTION..................................................................................18DS21Q42 REGISTER MAP.............................................................................................................26PARALLEL PORT...........................................................................................................................30
10.CONTROL, ID AND TEST REGISTERS..................................................................................30
11.STATUS AND INFORMATION REGISTERS.........................................................................41
12.ERROR COUNT REGISTERS....................................................................................................48
13.DS0 MONITORING FUNCTION...............................................................................................51
14.SIGNALING OPERATION.........................................................................................................54
14.1PROCESSOR BASED SIGNALING.....................................................................................................................54
14.2HARDWARE BASED SIGNALING.....................................................................................................................56
15.PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK....................................57
15.1TRANSMIT SIDE CODE GENERATION...........................................................................................................57
15.1.1Simple Idle Code Insertion and Per–Channel Loopback................................................................................57
15.1.2Per–Channel Code Insertion............................................................................................................................58
15.2RECEIVE SIDE CODE GENERATION..............................................................................................................59
15.2.1Simple Code Insertion......................................................................................................................................59
15.2.2Per–Channel Code Insertion............................................................................................................................60
16.CLOCK BLOCKING REGISTERS............................................................................................61
DS21FT42/DS21FF42
17.ELASTIC STORES OPERATION..............................................................................................61
17.1RECEIVE SIDE.......................................................................................................................................................62
17.2TRANSMIT SIDE...................................................................................................................................................62
17.3MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE...........................................................62
18.HDLC CONTROLLER................................................................................................................63
18.1HDLC FOR DS0S......................................................................................................................................................63
19.FDL/FS EXTRACTION AND INSERTION..............................................................................64
19.1HDLC AND BOC CONTROLLER FOR THE FDL...........................................................................................64
19.1.1General Overview..............................................................................................................................................64
19.1.2Status Register for the HDLC..........................................................................................................................65
19.1.3HDLC/BOC Register Description....................................................................................................................67
19.2LEGACY FDL SUPPORT......................................................................................................................................75
19.2.1Overview............................................................................................................................................................75
19.2.2Receive Section.................................................................................................................................................75
19.2.3Transmit Section...............................................................................................................................................76
19.3D4/SLC–96 OPERATION......................................................................................................................................77
20.PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION........................77
21.TRANSMIT TRANSPARENCY..................................................................................................80
22.INTERLEAVED PCM BUS OPERATION................................................................................81
23.JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.......................83
23.1DESCRIPTION............................................................................................................................................................83
23.2TAP CONTROLLER STATE MACHINE......................................................................................................................84
23.3INSTRUCTION REGISTER AND INSTRUCTIONS.........................................................................................................87
23.4TEST REGISTERS.......................................................................................................................................................89
24.TIMING DIAGRAMS...................................................................................................................94
25.OPERATING PARAMETERS..................................................................................................102
26.MCM PACKAGE DIMENSIONS.............................................................................................113
DS21FT42/DS21FF42
MCM PIN DESCRIPTION
PIN DESCRIPTION SORTED BY SYMBOL Table 2-1
PINSYMBOLI/ODESCRIPTION8MCLKO8.192 MHz Clock Based on CLKSI.
G20A0IAddress Bus Bit 0 (lsb).
H20A1IAddress Bus Bit 1.
G19A2IAddress Bus Bit 2.
H19A3IAddress Bus Bit 3.
G18A4IAddress Bus Bit 4.
H18A5IAddress Bus Bit 5.
G17A6IAddress Bus Bit 6.
H17A7IAddress Bus Bit 7 (msb).
W15BTSIBus Timing Select. 0 = Intel / 1 = Motorola.CLKSIIReference clock for the 8.192 MHz clock synthesizer.CS1*IChip Select for Quad Framer 1.CS2*IChip Select for Quad Framer 2.
Y15CS3*IChip Select for Quad Framer 3.
E19CS4*/NCIChip Select for Quad Framer 4. NC on Four x Three.
L20D0I/OData Bus Bit 0 (lsb).
M20D1I/OData Bus Bit 1.
L19D2I/OData Bus Bit 2.
M19D3I/OData Bus Bit 3.
L18D4I/OData Bus Bit 4.
M18D5I/OData Bus Bit 5.
L17D6I/OData Bus Bit 6.
M17D7I/OData Bus Bit 7 (msb).DVDD1–Digital Positive Supply for Framer 1.DVDD1–Digital Positive Supply for Framer 1.DVDD1–Digital Positive Supply for Framer 1.DVDD2–Digital Positive Supply for Framer 2.DVDD2–Digital Positive Supply for Framer 2.DVDD2–Digital Positive Supply for Framer 2.
V19DVDD3–Digital Positive Supply for Framer 3.
T12DVDD3–Digital Positive Supply for Framer 3.
L16DVDD3–Digital Positive Supply for Framer 3.
D17DVDD4/NC–Digital Positive Supply for Framer 4. NC on Four x Three.
F16DVDD4/NC–Digital Positive Supply for Framer 4. NC on Four x Three.
B11DVDD4/NC–Digital Positive Supply for Framer 4. NC on Four x Three.DVSS1–Digital Signal Ground for Framer 1.DVSS1–Digital Signal Ground for Framer 1.DVSS1–Digital Signal Ground for Framer 1.DVSS2–Digital Signal Ground for Framer 2.DVSS2–Digital Signal Ground for Framer 2.
DS21FT42/DS21FF42
PINSYMBOLI/ODESCRIPTION
R16DVSS3–Digital Signal Ground for Framer 3.
Y20DVSS3–Digital Signal Ground for Framer 3.
J20DVSS4/NC–Digital Signal Ground for Framer 4. NC on Four x Three.
A11DVSS4/NC–Digital Signal Ground for Framer 4. NC on Four x Three.
D19DVSS4/NC–Digital Signal Ground for Framer 4. NC on Four x Three.
Y14FS0IFramer Select 0 for the Parallel Control Port.
W14FS1IFramer Select 1 for the Parallel Control Port.
G16INT*OInterrupt for all four Quad Framers.
V14JTCLKIJTAG Clock.
E10JTDIIJTAG Data Input.
A19JTDOF/NCOJTAG Data Output for Four x Four Version. NC on Four x
Three.
T17JTDOTOJTAG Data Output for Four x Three Version.
H16JTMSIJTAG Test Mode Select.
K17JTRST*IJTAG Reset.
A13TESTITri-State. 0 = do not tri-state / 1 = tri-state all outputs & I/O
signals
P17MUXIBus Operation Select. 0 = non-multiplexed bus / 1 =
multiplexed busRCHBLK1OReceive Channel Blocking Clock.RCHBLK2OReceive Channel Blocking Clock.RCHBLK3OReceive Channel Blocking Clock.RCHBLK4OReceive Channel Blocking Clock.RCHBLK5OReceive Channel Blocking Clock.RCHBLK6OReceive Channel Blocking Clock.RCHBLK7OReceive Channel Blocking Clock.RCHBLK8OReceive Channel Blocking Clock.RCHBLK9OReceive Channel Blocking Clock.
W12RCHBLK10OReceive Channel Blocking Clock.
V17RCHBLK11OReceive Channel Blocking Clock.
U17RCHBLK12OReceive Channel Blocking Clock.
D16RCHBLK13/NCOReceive Channel Blocking Clock. NC on Four x Three.
K20RCHBLK14/NCOReceive Channel Blocking Clock. NC on Four x Three.
B18RCHBLK15/NCOReceive Channel Blocking Clock. NC on Four x Three.
B16RCHBLK16/NCOReceive Channel Blocking Clock. NC on Four x Three.RCLK1IReceive Clock for Framer 1RCLK2IReceive Clock for Framer 2.
D10RCLK3IReceive Clock for Framer 3.RCLK4IReceive Clock for Framer 4.RCLK5IReceive Clock for Framer 5.RCLK6IReceive Clock for Framer 6.RCLK7IReceive Clock for Framer 7.RCLK8IReceive Clock for Framer 8.
DS21FT42/DS21FF42
PINSYMBOLI/ODESCRIPTION
Y18RCLK11IReceive Clock for Framer 11.
N17RCLK12IReceive Clock for Framer 12.
D14RCLK13/NCIReceive Clock for Framer 13. NC on Four x Three.
P20RCLK14/NCIReceive Clock for Framer 14. NC on Four x Three.
C18RCLK15/NCIReceive Clock for Framer 15. NC on Four x Three.
C12RCLK16/NCIReceive Clock for Framer 16. NC on Four x Three.
E18RD*IRead Input.RNEG1IReceive Negative Data for Framer 1.RNEG2IReceive Negative Data for Framer 2.RNEG3IReceive Negative Data for Framer 3.RNEG4IReceive Negative Data for Framer 4.RNEG5IReceive Negative Data for Framer 5.RNEG6IReceive Negative Data for Framer 6.RNEG7IReceive Negative Data for Framer 7.RNEG8IReceive Negative Data for Framer 8.RNEG9IReceive Negative Data for Framer 9.
W11RNEG10IReceive Negative Data for Framer 10.
W17RNEG11IReceive Negative Data for Framer 11.
T20RNEG12IReceive Negative Data for Framer 12.
E14RNEG13/NCIReceive Negative Data for Framer 13. NC on Four x Three.
N20RNEG14/NCIReceive Negative Data for Framer 14. NC on Four x Three.
C20RNEG15/NCIReceive Negative Data for Framer 15. NC on Four x Three.
B13RNEG16/NCIReceive Negative Data for Framer 16. NC on Four x Three.RPOS1IReceive Positive Data for Framer 1.RPOS2IReceive Positive Data for Framer 2.RPOS3IReceive Positive Data for Framer 3.RPOS4IReceive Positive Data for Framer 4.RPOS5IReceive Positive Data for Framer 5.RPOS6IReceive Positive Data for Framer 6.RPOS7IReceive Positive Data for Framer 7.RPOS8IReceive Positive Data for Framer 8.
T10RPOS9IReceive Positive Data for Framer 9.
V11RPOS10IReceive Positive Data for Framer 10.
Y19RPOS11IReceive Positive Data for Framer 11.
R19RPOS12IReceive Positive Data for Framer 12.
D15RPOS13/NCIReceive Positive Data for Framer 13. NC on Four x Three.
J18RPOS14/NCIReceive Positive Data for Framer 14. NC on Four x Three.
A20RPOS15/NCIReceive Positive Data for Framer 15. NC on Four x Three.
A14RPOS16/NCIReceive Positive Data for Framer 16. NC on Four x Three.RSER1OReceive Serial Data from Framer 1.RSER2OReceive Serial Data from Framer 2.RSER3OReceive Serial Data from Framer 3.RSER4OReceive Serial Data from Framer 4.
DS21FT42/DS21FF42
PINSYMBOLI/ODESCRIPTIONRSER7OReceive Serial Data from Framer 7.RSER8OReceive Serial Data from Framer 8.
U11RSER9OReceive Serial Data from Framer 9.
Y12RSER10OReceive Serial Data from Framer 10.
V16RSER11OReceive Serial Data from Framer 11.
T16RSER12OReceive Serial Data from Framer 12.
E16RSER13/NCOReceive Serial Data from Framer 13. NC on Four x Three.
F20RSER14/NCOReceive Serial Data from Framer 14. NC on Four x Three.
C16RSER15/NCOReceive Serial Data from Framer 15. NC on Four x Three.
A12RSER16/NCOReceive Serial Data from Framer 16. NC on Four x Three.RSIG1OReceive Signaling Output from Framer 1.RSIG2OReceive Signaling Output from Framer 2.RSIG3OReceive Signaling Output from Framer 3.RSIG4OReceive Signaling Output from Framer 4.RSIG5OReceive Signaling Output from Framer 5.RSIG6OReceive Signaling Output from Framer 6.RSIG7OReceive Signaling Output from Framer 7.RSIG8OReceive Signaling Output from Framer 8.
U10RSIG9OReceive Signaling Output from Framer 9.
Y11RSIG10OReceive Signaling Output from Framer 10.
W19RSIG11OReceive Signaling Output from Framer 11.
U20RSIG12OReceive Signaling Output from Framer 12.
E15RSIG13/NCOReceive Signaling Output from Framer 13. NC on Four x
Three.
K19RSIG14/NCOReceive Signaling Output from Framer 14. NC on Four x
Three.
C17RSIG15/NCOReceive Signaling Output from Framer 15. NC on Four x
Three.
A15RSIG16/NCOReceive Signaling Output from Framer 16. NC on Four x
Three.RSYNC1I/OReceive Frame/Multiframe Sync for Framer 1.RSYNC2I/OReceive Frame/Multiframe Sync for Framer 2.RSYNC3I/OReceive Frame/Multiframe Sync for Framer 3.RSYNC4I/OReceive Frame/Multiframe Sync for Framer 4.RSYNC5I/OReceive Frame/Multiframe Sync for Framer 5.RSYNC6I/OReceive Frame/Multiframe Sync for Framer 6.RSYNC7I/OReceive Frame/Multiframe Sync for Framer 7.RSYNC8I/OReceive Frame/Multiframe Sync for Framer 8.
T11RSYNC9I/OReceive Frame/Multiframe Sync for Framer 9.
V13RSYNC10I/OReceive Frame/Multiframe Sync for Framer 10.
V15RSYNC11I/OReceive Frame/Multiframe Sync for Framer 11.
P18RSYNC12I/OReceive Frame/Multiframe Sync for Framer 12.
J17RSYNC13/NCI/OReceive Frame/Multiframe Sync for Framer 13. NC on Four x
DS21FT42/DS21FF42
PINSYMBOLI/ODESCRIPTION
Three.
B17RSYNC15/NCI/OReceive Frame/Multiframe Sync for Framer 15. NC on Four x
Three.
B12RSYNC16/NCI/OReceive Frame/Multiframe Sync for Framer 16. NC on Four x
Three.SYSCLK1ISystem Clock for Framer 1.SYSCLK2ISystem Clock for Framer 2.SYSCLK3ISystem Clock for Framer 3.SYSCLK4ISystem Clock for Framer 4.SYSCLK5ISystem Clock for Framer 5.SYSCLK6ISystem Clock for Framer 6.SYSCLK7ISystem Clock for Framer 7.SYSCLK8ISystem Clock for Framer 8.SYSCLK9ISystem Clock for Framer 9.SYSCLK10ISystem Clock for Framer 10.
U12SYSCLK11ISystem Clock for Framer 11.
R17SYSCLK12ISystem Clock for Framer 12.
E13SYSCLK13/NCISystem Clock for Framer 13. NC on Four x Three.
N18SYSCLK14/NCISystem Clock for Framer 14. NC on Four x Three.
E20SYSCLK15/NCISystem Clock for Framer 15. NC on Four x Three.
C14SYSCLK16/NCISystem Clock for Framer 16. NC on Four x Three.TCLK1ITransmit Clock for Framer 1.TCLK2ITransmit Clock for Framer 2.TCLK3ITransmit Clock for Framer 3.TCLK4ITransmit Clock for Framer 4.TCLK5ITransmit Clock for Framer 5.TCLK6ITransmit Clock for Framer 6.TCLK7ITransmit Clock for Framer 7.TCLK8ITransmit Clock for Framer 8.
U13TCLK9ITransmit Clock for Framer 9.
Y13TCLK10ITransmit Clock for Framer 10.
T18TCLK11ITransmit Clock for Framer 11.
P16TCLK12ITransmit Clock for Framer 12.
K16TCLK13/NCITransmit Clock for Framer 13. NC on Four x Three.
F19TCLK14/NCITransmit Clock for Framer 14. NC on Four x Three.
E17TCLK15/NCITransmit Clock for Framer 15. NC on Four x Three.
C11TCLK16/NCITransmit Clock for Framer 16. NC on Four x Three.TNEG1OTransmit Negative Data from Framer 1.TNEG2OTransmit Negative Data from Framer 2.TNEG3OTransmit Negative Data from Framer 3.
A10TNEG4OTransmit Negative Data from Framer 4.TNEG5OTransmit Negative Data from Framer 5.TNEG6OTransmit Negative Data from Framer 6.
DS21FT42/DS21FF42
PINSYMBOLI/ODESCRIPTION
U14TNEG9OTransmit Negative Data from Framer 9.
V12TNEG10OTransmit Negative Data from Framer 10.
W18TNEG11OTransmit Negative Data from Framer 11.
T19TNEG12OTransmit Negative Data from Framer 12.
D11TNEG13/NCOTransmit Negative Data from Framer 13. NC on Four x Three.
K18TNEG14/NCOTransmit Negative Data from Framer 14. NC on Four x Three.
C19TNEG15/NCOTransmit Negative Data from Framer 15. NC on Four x Three.
B15TNEG16/NCOTransmit Negative Data from Framer 16. NC on Four x Three.TPOS1OTransmit Positive Data from Framer 1.TPOS2OTransmit Positive Data from Framer 2.TPOS3OTransmit Positive Data from Framer 3.
B10TPOS4OTransmit Positive Data from Framer 4.TPOS5OTransmit Positive Data from Framer 5.TPOS6OTransmit Positive Data from Framer 6.TPOS7OTransmit Positive Data from Framer 7.TPOS8OTransmit Positive Data from Framer 8.
T14TPOS9OTransmit Positive Data from Framer 9.
Y10TPOS10OTransmit Positive Data from Framer 10.
V18TPOS11OTransmit Positive Data from Framer 11.
V20TPOS12OTransmit Positive Data from Framer 12.
E12TPOS13/NCOTransmit Positive Data from Framer 13. NC on Four x Three.
N19TPOS14/NCOTransmit Positive Data from Framer 14. NC on Four x Three.
B19TPOS15/NCOTransmit Positive Data from Framer 15. NC on Four x Three.
B14TPOS16/NCOTransmit Positive Data from Framer 16. NC on Four x Three.TSER1ITransmit Serial Data for Framer 1.TSER2ITransmit Serial Data for Framer 2.TSER3ITransmit Serial Data for Framer 3.TSER4ITransmit Serial Data for Framer 4.TSER5ITransmit Serial Data for Framer 5.TSER6ITransmit Serial Data for Framer 6.TSER7ITransmit Serial Data for Framer 7.TSER8ITransmit Serial Data for Framer 8.
M16TSER9ITransmit Serial Data for Framer 9.TSER10ITransmit Serial Data for Framer 10.
W16TSER11ITransmit Serial Data for Framer 11.
W20TSER12ITransmit Serial Data for Framer 12.
D13TSER13/NCITransmit Serial Data for Framer 13. NC on Four x Three.
F17TSER14/NCITransmit Serial Data for Framer 14. NC on Four x Three.
D18TSER15/NCITransmit Serial Data for Framer 15. NC on Four x Three.
A18TSER16/NCITransmit Serial Data for Framer 16. NC on Four x Three.TSIG1ITransmit Signaling Input for Framer 1.TSIG2ITransmit Signaling Input for Framer 2.TSIG3ITransmit Signaling Input for Framer 3.
PINSYMBOLI/ODESCRIPTIONTSIG6ITransmit Signaling Input for Framer 6.TSIG7ITransmit Signaling Input for Framer 7.TSIG8ITransmit Signaling Input for Framer 8.
U15TSIG9ITransmit Signaling Input for Framer 9.
V10TSIG10ITransmit Signaling Input for Framer 10.
U18TSIG11ITransmit Signaling Input for Framer 11.
R18TSIG12ITransmit Signaling Input for Framer 12.
E11TSIG13/NCITransmit Signaling Input for Framer 13. NC on Four x Three.
P19TSIG14/NCITransmit Signaling Input for Framer 14. NC on Four x Three.
B20TSIG15/NCITransmit Signaling Input for Framer 15. NC on Four x Three.
A16TSIG16/NCITransmit Signaling Input for Framer 16. NC on Four x Three.TSSYNC1ITransmit System Sync for Framer 1.TSSYNC2ITransmit System Sync for Framer 2.TSSYNC3ITransmit System Sync for Framer 3.TSSYNC4ITransmit System Sync for Framer 4.TSSYNC5ITransmit System Sync for Framer 5.TSSYNC6ITransmit System Sync for Framer 6.TSSYNC7ITransmit System Sync for Framer 7.TSSYNC8ITransmit System Sync for Framer 8.
T15TSSYNC9ITransmit System Sync for Framer 9.TSSYNC10ITransmit System Sync for Framer 10.
Y17TSSYNC11ITransmit System Sync for Framer 11.
U19TSSYNC12ITransmit System Sync for Framer 12.
C13TSSYNC13/NCITransmit System Sync for Framer 13. NC on Four x Three.
R20TSSYNC14/NCITransmit System Sync for Framer 14. NC on Four x Three.
D20TSSYNC15/NCITransmit System Sync for Framer 15. NC on Four x Three.
A17TSSYNC16/NCITransmit System Sync for Framer 16. NC on Four x Three.TSYNC1I/OTransmit Sync for Framer 1.TSYNC2I/OTransmit Sync for Framer 2.TSYNC3I/OTransmit Sync for Framer 3.TSYNC4I/OTransmit Sync for Framer 4.TSYNC5I/OTransmit Sync for Framer 5.TSYNC6I/OTransmit Sync for Framer 6.TSYNC7I/OTransmit Sync for Framer 7.TSYNC8I/OTransmit Sync for Framer 8.
T13TSYNC9I/OTransmit Sync for Framer 9.
W13TSYNC10I/OTransmit Sync for Framer 10.
U16TSYNC11I/OTransmit Sync for Framer 11.
N16TSYNC12I/OTransmit Sync for Framer 12.
J16TSYNC13/NCI/OTransmit Sync for Framer 13. NC on Four x Three.
F18TSYNC14/NCI/OTransmit Sync for Framer 14. NC on Four x Three.
C15TSYNC15/NCI/OTransmit Sync for Framer 15. NC on Four x Three.
D12TSYNC16/NCI/OTransmit Sync for Framer 16. NC on Four x Three.
DS21FT42/DS21FF42
2. DS21FF42 (4 X 4) PCB LAND PATTERN Figure 3-1
The diagram shown below is the pin pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.234567891011121314151617181920rpos
rclk
sync1
tsync
tclk
dvss
rsync
rch
blk
rneg
tneg
dvss
rser
testrpos
rsig
tsig
sync
tser
jtdofrposrsync
rneg
tpos
tser
sys
clk
clksi8
mclk
sys
clk
rclk
tpos
dvdd
rsync
rneg
tpos
tneg
rch
blk
rsync
rch
blk
tpos
tsigrser
rch
blk
tneg
tsig
tclk
rser
dvdd
rser4rpos
tsig
tclk
rclk
sync
sys
clk
tsync
rser
rsig
rclk
tneg
rnegtclk
dvdd
rsig
rsig
dvss
rsync
tser
rsig4rneg
rclk
tneg
tsync
tser
rclk
rpos
rch
blk
dvdd
tser
dvss
synctser
sys
clk
tsync
dvdd
sys
clk
rch
blk
tsync
sync
dvss
jtditsig
tpos
sys
clk
rneg
rsig
rser
tclk
rd*cs4*sys
clktsig
sync
tser
tsync
tneg
dvdd
tser
tsync
tclk
rserrsync
rsig
rch
blk
tsig
sync
int*A6A4A2A0rpos
rneg
rser
rpos
tclk
jtmsA7A5A3A1tneg
tpos
rclk
rsync
tpos
tsync
rsync
rpos
rsync
dvssrclk
tclk
dvdd
dvss
rsig
tclk
jtrst*tneg
rsig
rch
blktneg
tpos
tsig
sync
tser
dvddD4D2D0rpos
rneg
rclk
sys
clk
tsync
tserD5D3D1rch
blk
rsig
rsync
rser
rch
blk
tsync
rclk
sys
clk
tpos
rnegrser
dvdd
rneg
rpos
tneg
tclk
muxrsync
tsig
rclktclk
tsync
tpos
sync
tsig
dvss
sys
clk
tsig
rpos
synctser
sys
clk
tser
sys
clk
tsync
tclk
rser
cs1*rclk
rpos
rsync
dvdd
tsync
tpos
sync
rser
jtdottclk
tneg
rnegts
sync
tsig
dvss
dvss
rsync
rch
blk
dvdd
dvss
rneg
rsig
rser
sys
clk
tclk
tneg
tsig
tsync
rch
blk
tsig
tssyn
rsigrclk
tneg
rneg
rsig
rpos
rsig
rneg
tneg
tsig
tsig
rpos
tneg
rsync
jtclkrsync
rser
rch
blk
tpos
dvdd
tpostpos
rpos
sys
clk
rser
tsync
rclk
tpos
sync
tser
rclk
rneg
rch
blk
tsync
fs1btstser
rneg
tneg
rsig
tserrch
blk
rsync
tclk
cs2*sys
clk
tser
sync
rch
blk
sys
clk
tpos
rsig
rser
tclk
fs0cs3*wr*ts
sync
rclk
rpos
dvss
DS21FT42/DS21FF42
3. DS21FT42 (4 X 3) PCB LAND PATTERN Figure 4-1
The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.234567891011121314151617181920rpos
rclk
sync1
tsync
tclk
dvss
rsync
rch
blk
rneg
tnegnctestnsnsncncncncncrsync
rneg
tpos
tser
sys
clk
clksi8
mclk
sys
clk
rclk
tposncncncncncncncncncrser
rch
blk
tneg
tsig
tclk
rser
dvdd
rser4rpos
tsigncncncnsncncncncnctclk
dvdd
rsig
rsig
dvss
rsync
tser
rsig4rneg
rclkncncncncncncncncnctser
sys
clk
tsync
dvdd
sys
clk
rch
blk
tsync
sync
dvss
jtdincncncncncncncrd*ncnctsig
sync
tser
tsync
tnegncncncncrsync
rsig
rch
blk
tsig
sync
int*A6A4A2A0rpos
rneg
rser
rpos
tclk
jtmsA7A5A3A1tneg
tpos
rclk
rsync
tposncncncncrclk
tclk
dvdd
dvss
rsigjtrst*ncncnctneg
tpos
tsig
sync
tser
dvddD4D2D0rpos
rneg
rclk
sys
clk
tsync
tserD5D3D1rch
blk
rsig
rsync
rser
rch
blk
tsync
rclkncncrser
dvdd
rneg
rpos
tneg
tclk
muxrsyncnctclk
tsync
tpos
sync
tsig
dvss
sys
clk
tsig
rpostser
sys
clk
tser
sys
clk
tsync
tclk
rser
cs1*rclk
rpos
rsync
dvdd
tsync
tpos
sync
rser
jtdottclk
tneg
rnegts
sync
tsig
dvss
dvss
rsync
rch
blk
dvdd
dvss
rneg
rsig
rser
sys
clk
tclk
tneg
tsig
tsync
rch
blk
tsig
tssyn
rsigrclk
tneg
rneg
rsig
rpos
rsig
rneg
tneg
tsig
tsig
rpos
tneg
rsync
jtclkrsync
rser
rch
blk
tpos
dvdd
tpostpos
rpos
sys
clk
rser
tsync
rclk
tpos
sync
tser
rclk
rneg
rch
blk
tsync
fs1btstser
rneg
tneg
rsig
tserrch
blk
rsync
tclk
cs2*sys
clk
tser
sync
rch
blk
sys
clk
tpos
rsig
rser
tclk
fs0cs3*wr*ts
sync
rclk
rpos
dvss
DS21FT42/DS21FF42
4. DS21Q42 FEATURESFour T1 DS1/ISDN–PRI/J1 framing
transceiversAll four framers are fully independentEach of the four framers contain dual two-
frame elastic store slip buffers that can connect
to asynchronous backplanes up to 8.192 MHz8-bit parallel control port that can be used
directly on either multiplexed or
nonmultiplexed buses (Intel or Motorola)Programmable output clocks for Fractional T1Fully independent transmit and receive
functionalityIntegral HDLC controller with 64-byte buffers.
Configurable for FDL or DS0 operationGenerates and detects in-band loop codes from
1 to 8 bits in length including CSU loop codesPin compatible with DS21Q44 E1 Enhanced
Quad E1 Framer3.3V supply with 5V tolerant I/O; low power
CMOSAvailable in 128--pin TQFP packageIEEE 1149.1 support
FUNCTIONAL DIAGRAMceiveramer
Elastic
Storeransmitrmatter
Elastic
Store
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3ontrol Port
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
5. DS21Q42 INTRODUCTION
The DS21Q42 is a superset version of the popular DS21Q41 Quad T1 framer offering the new features
listed below. All of the original features of the DS21Q41 have been retained and software created for the
original device is transferable to the DS21Q42.
DS21FT42/DS21FF42
NEW FEATURESAdditional hardware signaling capability including:Receive signaling re-insertion to a backplane multiframe syncAvailability of signaling in a separate PCM data streamSignaling freezingInterrupt generated on change of signaling dataFull HDLC controller with 64–byte buffers in both transmit and receive paths. Configurable for FDL
or DS0 accessPer–channel code insertion in both transmit and receive pathsAbility to monitor one DS0 channel in both the transmit and receive pathsRCL, RLOS, RRA, and RAIS alarms now interrupt on change of stateDetects AIS-CI8.192 MHz clock synthesizerPer–channel loopbackAbility to calculate and check CRC6 according to the Japanese standardAbility to pass the F–Bit position through the elastic stores in the 2.048 MHz backplane modeIEEE 1149.1 supportFEATURESFour T1 DS1/ISDN–PRI/J1 framing transceiversAll four framers are fully independentFrames to D4, ESF, and SLC–96 R formatsEach of the four framers contain dual two–frame elastic store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz8–bit parallel control port that can be used directly on either multiplexed or non–multiplexed buses
(Intel or Motorola)Extracts and inserts robbed bit signalingDetects and generates yellow (RAI) and blue (AIS) alarmsProgrammable output clocks for Fractional T1Fully independent transmit and receive functionalityGenerates and detects in–band loop codes from 1 to 8 bits in length including CSU loop codesContains ANSI one’s density monitor and enforcerLarge path and line error counters including BPV, CV, CRC6, and framing bit errorsPin compatible with DS21Q44 E1 Enhanced Quad E1 Framer3.3V supply with 5V tolerant I/O; low power CMOSAvailable in 128–pin TQFP package
DS21FT42/DS21FF42
FUNCTIONAL DESCRIPTION
The receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the
receive side elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK
input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock.
The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side of the DS21Q42 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission.
READER’S NOTE:
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us
frame, there are 24 8–bit channels plus a framing bit. It is assumed that the framing bit is sent first
followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is
the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data
sheet, the following abbreviations will be used:Superframe (12 frames per multiframe) Multiframe Structure
SLC–96Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
ESFExtended Superframe (24 frames per multiframe) Multiframe Structure
B8ZSBipolar with 8 Zero Substitution
CRCCyclical Redundancy CheckTerminal Framing Pattern in D4Signaling Framing Pattern in D4
FPSFraming Pattern in ESFMultiframe
BOCBit Oriented Code
HDLCHigh Level Data Link Control
FDLFacility Data Link
DS21FT42/DS21FF42
DS21Q42 ENHANCED QUAD T1 FRAMER Figure 5-1
6. DS21Q42 PIN FUNCTION DESCRIPTION
This section describes the signals on the DS21Q42 die. Signals that are not bonded out or have limited
functionality in the DS21FT42 and DS21FF42 are noted in italics.
VSS
VDD
FRAMER #1
FRAMER #3
FRAMER #2
FRAMER #0
Parallel & Test Control Port
(routed to all blocks)
D0 to D7 /
AD0 to AD7
FS1BTSINT*WR*
(R/W*)
RD*
(DS*)
FS0CS*TESTALE
(AS)/
A0 to A5,
MUX8
FMS
r Loop
bac
yload Loo
pbac
ener
tio
En
C G
ener
atio
llo
larm G
ener
ati
ignal
ing Ins
rtio
r Cha
In
rtio
it I
rtio
Receive Side Framer
Transmit Side Formatter
V C
ter
rm D
tio
er-C
hannel
Code
Ins
ert
Elastic
Store
ne'
Dens
ity
rcer
Loop
de G
ner
atio
ne'
ens
ity M
oni
tor
sync
data
clock
sync
data
clock
TSYNC
TCLK
TCHCLK
TSER
TCHBLK
RCHCLK
RCHBLK
RLCLK
RMSYNC
TSSYNC
TSYSCLK
RLINK
RSER
RSYSCLK
RSYNC
RFSYNC
TLINK
TLCLK
FDL Extraction
Timing Control
Elastic
Store
Sync Control
Timing Control
ync
roni
Loop
Co
de De
tec
tor
C/F
ram
e E
rro
r C
ignal
g E
l Ma
Signaling
Buffer
RSIG
Hardware
Signaling
InsertionTSIG
Remote
Lo
opbac
8MCLK
r-Chann
ode Ins
er-C
hannel
Loopb
64-Byte Buffer
BOM Detection
RPOS
RCLK
RNEG
TPOS
TNEG
CLKS I
FDL Insertion
64-Byte Buffer
BOM Generation
HDLC Engine
DS0 Insertion
HDLC Engine
DS0 Insertion
PowerJTAG Port
JTRST*
JTMS
JTCLK
JTDI
JTDO
RLOS/LOTC1
Note:
1. Alternate pin functions. Consult data sheet for restrictions.
LOTC DET
&
MUX
8.192MHz Clock
Synthesizer
DS21FT42/DS21FF42
TRANSMIT SIDE PINS
Signal Name:TCLK
Signal Description:Transmit Clock
Signal Type:Input
A 1.544 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:TSER
Signal Description:Transmit Serial Data
Signal Type:Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:TCHCLK
Signal Description:Transmit Channel Clock
Signal Type:Output
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store
is enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS
= 1 (DS21Q41 emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:TCHBLK
Signal Description:Transmit Channel Block
Signal Type:Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384 Kbps service,
768 Kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications,
for external per–channel loopback, and for per–channel conditioning. See Section 16 for details. This
signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:TSYSCLK
Signal Description:Transmit System Clock
Signal Type:Input
1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz. This pin is tied to the RSYSCLK signal in the DS21FF42/DS21FT42.
Signal Name:TLCLK
Signal Description:Transmit Link Clock
Signal Type:Output
4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 19 for details. This signal is
not bonded out in the DS21FF42/DS21FT42.
DS21FT42/DS21FF42
Signal Name:TLINK
Signal Description:Transmit Link Data
Signal Type:Input
If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either
the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 19 for
details. This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:TSYNC
Signal Description:Transmit Sync
Signal Type:Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via
TCR2.2, the DS21Q42 can be programmed to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide
pulses at signaling frames. See Section 24 for details.
Signal Name:TSSYNC
Signal Description:Transmit System Sync
Signal Type:Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame
or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store.
Signal Name:TSIG
Signal Description:Transmit Signaling Input
Signal Type:Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM T1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when
FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:TPOS
Signal Description:Transmit Positive Data Output
Signal Type:Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (CCR1.6) control bit.
Signal Name:TNEG
Signal Description:Transmit Negative Data Output
Signal Type:Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
RECEIVE SIDE PINS
Signal Name:RLINK
Signal Description:Receive Link Data
Signal Type:Output
Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
DS21FT42/DS21FF42
Signal Name:RLCLK
Signal Description:Receive Link Clock
Signal Type:Output
A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output. This signal is not bonded out in the
DS21FF42/DS21FT42.
Signal Name:RCHCLK
Signal Description:Receive Channel Clock
Signal Type:Output
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS =
1 (DS21Q41 emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:RCHBLK
Signal Description:Receive Channel Block
Signal Type:Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications,
for external per–channel loopback, and for per–channel conditioning. See Section 16 for details.
Signal Name:RSER
Signal Description:Receive Serial Data
Signal Type:Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:RSYNC
Signal Description:Receive Sync
Signal Type:Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or
multiframe (RCR2.4 = 1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can
also be set to output double–wide pulses on signaling frames. If the receive side elastic store is enabled
via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section 24 for details.
Signal Name:RFSYNC
Signal Description:Receive Frame Sync
Signal Type:Output
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. This
signal is not bonded out in the DS21FF42/DS21FT42.
DS21FT42/DS21FF42
Signal Name:RMSYNC
Signal Description:Receive Multiframe Sync
Signal Type:Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q41 emulation). This signal is not bonded
out in the DS21FF42/DS21FT42.
Signal Name:RSYSCLK
Signal Description:Receive System Clock
Signal Type:Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied
low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz. This pin is
tied to the TSYSCLK signal in the DS21FF42/DS21FT42.
Signal Name:RSIG
Signal Description:Receive Signaling Output
Signal Type:Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is
enabled. This function is available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:RLOS/LOTC
Signal Description:Receive Loss of Sync / Loss of Transmit Clock
Signal Type:Output
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q41
emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:CLKSI
Signal Description:8 MHz Clock Reference
Signal Type:Input
A 1.544 MHz reference clock used in the generation of 8MCLK. This function is available when FMS =
0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:8MCLK
Signal Description:8 MHz Clock
Signal Type:Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is
available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
DS21FT42/DS21FF42
Signal Name:RPOS
Signal Description:Receive Positive Data Input
Signal Type:Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name:RNEG
Signal Description:Receive Negative Data Input
Signal Type:Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name:RCLK
Signal Description:Receive Clock Input
Signal Type:Input
Clock used to clock data through the receive side framer.
PARALLEL CONTROL PORT PINS
Signal Name:INT*
Signal Description:Interrupt
Signal Type:Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the HDLC Status Register. Active low, open drain output.
Signal Name:FMS
Signal Description:Framer Mode Select
Signal Type:Input
Set low to select DS21Q42 feature set. Set high to select DS21Q41 emulation. FMS is tied to ground for
the DS21FF42/DS21FT42.
Signal Name:MUX
Signal Description:Bus Operation
Signal Type:Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:D0 to D7/ AD0 to AD7
Signal Description:Data Bus or Address/Data Bus
Signal Type:Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as a 8–bit multiplexed address / data bus.
DS21FT42/DS21FF42
Signal Name:A0 to A5, A7
Signal Description:Address Bus
Signal Type:Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:ALE(AS)/A6
Signal Description:A6 or Address Latch Enable (Address Strobe)
Signal Type:Input
In non–multiplexed bus operation (MUX = 0), serves as address Bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.
Signal Name:BTS
Signal Description:Bus Type Select
Signal Type:Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name:RD*(DS*)
Signal Description:Read Input (Data Strobe)
Signal Type:Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 25.
Signal Name:FS0 AND FS1
Signal Description:Framer Selects
Signal Type:Input
Selects which of the four framers to be accessed.
Signal Name:CS*
Signal Description:Chip Select
Signal Type:Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name:WR*( R/W*)
Signal Description:Write Input(Read/Write)
Signal Type:Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name:TEST
Signal Description:3–State Control
Signal Type:Input
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when
FMS = 0 and JTRST* is tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST* =
DS21FT42/DS21FF42
Signal Name:JTRST*
Signal Description:IEEE 1149.1 Test Reset
Signal Type:Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the DEVICE ID mode allowing normal device
operation. If boundary scan is not used and FMS = 0, this pin should be held low. This function is
available when FMS = 0. When FMS=1, this pin is held LOW internally. This pin is pulled up internally
by a 10K ohm resistor. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:JTMS
Signal Description:IEEE 1149.1 Test Mode Select
Signal Type:Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should
be left unconnected. This function is available when FMS = 0. FMS is tied to ground for the
DS21FF42/DS21FT42.
Signal Name:JTCLK
Signal Description:IEEE 1149.1 Test Clock Signal
Signal Type:Input
This signal is used to shift data into JTDI pin on the rising edge and out of JTDO pin on the falling edge.
If not used, this pin should be connected to VSS. This function is available when FMS = 0. FMS is tied
to ground for the DS21FF42/DS21FT42.
Signal Name:JTDI
Signal Description:IEEE 1149.1 Test Data Input
Signal Type:Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin is pulled up
internally by a 10K ohm resistor. If not used, this pin should be left unconnected. This function is
available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:JTDO
Signal Description:IEEE 1149.1 Test Data Output
Signal Type:Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0. FMS is tied to ground for the
DS21FF42/DS21FT42.
SUPPLY PINS
Signal Name:VDD
Signal Description:Positive Supply
Signal Type:Supply
2.97 to 3.63 volts.
DS21FT42/DS21FF42
Signal Name:VSS
Signal Description:Signal Ground
Signal Type:Supply
0.0 volts.
7. DS21Q42 REGISTER MAP
REGISTER MAP SORTED BY ADDRESS Table 7-1
ADDRESSR/WREGISTER NAMEREGISTER
ABBREVIATIONR/WHDLC ControlHCRR/WHDLC StatusHSRR/WHDLC Interrupt MaskHIMRR/WReceive HDLC InformationRHIRR/WReceive Bit Oriented CodeRBOCRReceive HDLC FIFORHFRR/WTransmit HDLC InformationTHIRR/WTransmit Bit Oriented CodeTBOCWTransmit HDLC FIFOTHFR–Not used(set to 00H)R/WCommon Control 7CCR7–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)RDevice IDIDRR/WReceive Information 3RIR3R/WCommon Control 4CCR4R/WIn–Band Code ControlIBCCR/WTransmit Code DefinitionTCDR/WReceive Up Code DefinitionRUPCDR/WReceive Down Code DefinitionRDNCDR/WTransmit Channel Control 1TCC1R/WTransmit Channel Control 2TCC2R/WTransmit Channel Control 3TCC3R/WCommon Control 5CCR5RTransmit DS0 MonitorTDS0MR/WReceive Channel Control 1RCC1R/WReceive Channel Control 2RCC2R/WReceive Channel Control 3RCC3R/WCommon Control 6CCR6RReceive DS0 MonitorRDS0MR/WStatus 1SR1R/WStatus 2SR2
DS21FT42/DS21FF42
ADDRESSR/WREGISTER NAMEREGISTER
ABBREVIATIONRLine Code Violation Count 2CVCR2RPath Code Violation Count 1PCVCR1RPath Code violation Count 2PCVCR2RMultiframe Out of Sync Count 2MOSCR2RReceive FDL RegisterRFDLR/WReceive FDL Match 1RMTCH1R/WReceive FDL Match 2RMTCH2R/WReceive Control 1RCR1R/WReceive Control 2RCR2R/WReceive Mark 1RMR1R/WReceive Mark 2RMR2R/WReceive Mark 3RMR3R/WCommon Control 3CCR3R/WReceive Information 2RIR2R/WTransmit Channel Blocking 1TCBR1R/WTransmit Channel blocking 2TCBR2R/WTransmit Channel Blocking 3TCBR3R/WTransmit Control 1TCR1R/WTransmit Control 2TCR2R/WCommon Control 1CCR1R/WCommon Control 2CCR2R/WTransmit Transparency 1TTR1R/WTransmit Transparency 2TTR2R/WTransmit Transparency 3TTR3R/WTransmit Idle 1TIR1R/WTransmit Idle 2TIR2R/WTransmit Idle 3TIR3R/WTransmit Idle DefinitionTIDRR/WTransmit Channel 9TC9R/WTransmit Channel 10TC10R/WTransmit Channel 11TC11R/WTransmit Channel 12TC12R/WTransmit Channel 13TC13R/WTransmit Channel 14TC14R/WTransmit Channel 15TC15R/WTransmit Channel 16TC16R/WTransmit Channel 17TC17R/WTransmit Channel 18TC18R/WTransmit Channel 19TC19R/WTransmit Channel 20TC20R/WTransmit Channel 21TC21R/WTransmit Channel 22TC22
DS21FT42/DS21FF42
ADDRESSR/WREGISTER NAMEREGISTER
ABBREVIATIONR/WTransmit Channel 1TC1R/WTransmit Channel 2TC2R/WTransmit Channel 3TC3R/WTransmit Channel 4TC4R/WTransmit Channel 5TC5R/WTransmit Channel 6TC6R/WTransmit Channel 7TC7R/WTransmit Channel 8TC8R/WReceive Channel 17RC17R/WReceive Channel 18RC18R/WReceive Channel 19RC19R/WReceive Channel 20RC20R/WReceive Channel 21RC21R/WReceive Channel 22RC22R/WReceive Channel 23RC23R/WReceive Channel 24RC24RReceive Signaling 1RS1RReceive Signaling 2RS2RReceive Signaling 3RS3RReceive Signaling 4RS4RReceive Signaling 5RS5RReceive Signaling 6RS6RReceive Signaling 7RS7RReceive Signaling 8RS8RReceive Signaling 9RS9RReceive Signaling 10RS10RReceive Signaling 11RS11RReceive Signaling 12RS12R/WReceive Channel Blocking 1RCBR1R/WReceive Channel Blocking 2RCBR2R/WReceive Channel Blocking 3RCBR3R/WInterrupt Mask 2IMR2R/WTransmit Signaling 1TS1R/WTransmit Signaling 2TS2R/WTransmit Signaling 3TS3R/WTransmit Signaling 4TS4R/WTransmit Signaling 5TS5R/WTransmit Signaling 6TS6R/WTransmit Signaling 7TS7R/WTransmit Signaling 8TS8R/WTransmit Signaling 9TS9R/WTransmit Signaling 10TS10
DS21FT42/DS21FF42
ADDRESSR/WREGISTER NAMEREGISTER
ABBREVIATION–Not used(set to 00H)R/WTest 1TEST1 (set to 00h)R/WTransmit FDL RegisterTFDLR/WInterrupt Mask Register 1IMR1R/WReceive Channel 1RC1R/WReceive Channel 2RC2R/WReceive Channel 3RC3R/WReceive Channel 4RC4R/WReceive Channel 5RC5R/WReceive Channel 6RC6R/WReceive Channel 7RC7R/WReceive Channel 8RC8R/WReceive Channel 9RC9R/WReceive Channel 10RC10R/WReceive Channel 11RC11R/WReceive Channel 12RC12R/WReceive Channel 13RC13R/WReceive Channel 14RC14R/WReceive Channel 15RC15R/WReceive Channel 16RC16R/WReceive HDLC DS0 Control Register 1RDC1R/WReceive HDLC DS0 Control Register 2RDC2R/WTransmit HDLC DS0 Control Register 1TDC1R/WTransmit HDLC DS0 Control Register 2TDC2R/WInterleave Bus Operation RegisterIBO–Not used(set to 00H)R/WTest 2TEST2 (set to 00h)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)–Not used(set to 00H)
DS21FT42/DS21FF42
NOTES:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on
power– up initialization to insure proper operation.
2. Register banks AxH, BxH, CxH, DxH, ExH, and FxH are not accessible.
8. PARALLEL PORT
The DS21Q42 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21Q42 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 25 for more details.
9. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS21Q42 is configured via a set of eleven control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21Q42 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7).
Each of the eleven registers are described in this section. There is a device Identification Register (IDR)
at address 0Fh. The MSB of this read–only register is fixed to a zero indicating that the DS21Q42 is
present. The E1 pin–for–pin compatible version of the DS21Q42 is the DS21Q44 and it also has an ID
register at address 0Fh and the user can read the MSB to determine which chip is present since in the
DS21Q42 the MSB will be set to a zero and in the DS21Q44 it will be set to a one. The lower four bits
of the IDR are used to display the die revision of the chip.
POWER–UP SEQUENCE
The DS21Q42 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach on each framer within the DS21Q42.
1. Clear framer’s register space by writing 00H to the addresses 00H through 09FH.
2. Program required registers to achieve desired operating mode.
NOTE:
When emulating the DS21Q41 feature set (FMS = 1), the full address space (00H through 09FH) must be
initialized. DS21Q41 emulation requires address pin A7 to be used. FMS is tied to ground for the
DS21FF42/DS21FT42.
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).
DS21FT42/DS21FF42
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)(LSB)
T1E1000ID3ID2ID1ID0
SYMBOLPOSITIONNAME AND DESCRIPTION
T1E1IDR.7T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3IDR.3Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
ID2IDR.1Chip Revision Bit 2.
ID1IDR.2Chip Revision Bit 1.
ID0IDR.0Chip Revision Bit 0. LSB of a decimal code that represents
the chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB)(LSB)
LCVCRFARCOOF1OOF2SYNCCSYNCTSYNCERESYNC
SYMBOLPOSITIONNAME AND DESCRIPTION
LCVCRFRCR1.7Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
ARCRCR1.6Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1RCR1.5Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2RCR1.4Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCCRCR1.3Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCTRCR1.2Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
DS21FT42/DS21FF42
SYNCERCR1.1Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNCRCR1.0Resync. When toggled from low to high, a resynchronization
of the receive side framer is initiated. Must be cleared and
set again for a subsequent resync.
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB) (LSB)
RCSRZBTSIRSDWRSMRSIORD4YMFSBEMOSCRF
SYMBOLPOSITIONNAME AND DESCRIPTION
RCSRCR2.7Receive Code Select. See Section 15 for more details.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
RZBTSIRCR2.6Receive Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
RSDWRCR2.5RSYNC Double–Wide. (note: this bit must be set to zero
when RCR2.4 = 1 or when RCR2.3 = 1)
0 = do not pulse double wide in signaling frames
1 = do pulse double wide in signaling frames
RSMRCR2.4RSYNC Mode Select. (A Don’t Care if RSYNC is
programmed as an input)
0 = frame mode (see the timing in Section 24)
1 = multiframe mode (see the timing in Section 24)
RSIORCR2.3RSYNC I/O Select. (note: this bit must be set to zero when
CCR1.2 = 0)
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
RD4YMRCR2.2Receive Side D4 Yellow Alarm Select.
0 = zeros in Bit 2 of all channels
1 = a one in the S–bit position of frame 12
FSBERCR2.1PCVCR Fs–Bit Error Report Enable.
0 = do not report bit errors in Fs–bit position; only Ft bit
position
1 = report bit errors in Fs–bit position as well as Ft bit
position
MOSCRFRCR2.0Multiframe Out of Sync Count Register Function Select.
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
DS21FT42/DS21FF42
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB)(LSB)
LOTCMCTFPTTCPTTSSEGB7STFDLSTBLTYEL
SYMBOLPOSITIONNAME AND DESCRIPTION
LOTCMCTCR1.7Loss Of Transmit Clock Mux Control. Determines
whether the transmit side formatter should switch to RCLK if
the TCLK input should fail to transition (see Figure 6-1 for
details).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
TFPTTCR1.6Transmit F–bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSER
TCPTTCR1.5Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F–bit time
TSSETCR1.4Software Signaling Insertion Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels from the TS1-TS12
registers (the TTR registers can be used to block insertion on
a channel by channel basis)
GB7STCR1.3Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels
containing all zeros are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all 0-byte channels regardless of
how the TTR registers are programmed
TFDLSTCR1.2TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register
(legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC
controller or the TLINK pin
TBLTCR1.1Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
TYELTCR1.0Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
NOTE:
For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 24-15.
DS21FT42/DS21FF42
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB)(LSB)
TEST1TEST0TZBTSITSDWTSMTSIOTD4YMTB7ZS
SYMBOLPOSITIONNAME AND DESCRIPTION
TEST1TCR2.7Test Mode Bit 1 for Output Pins. See Table 10–1.
TEST0TCR2.6Test Mode Bit 0 for Output Pins. See Table 10–1.
TZBTSITCR2.5Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSDWTCR2.4TSYNC Double–Wide. (note: this bit must be set to zero
when TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSMTCR2.3TSYNC Mode Select.
0 = frame mode (see the timing in Section 24)
1 = multiframe mode (see the timing in Section 24)
TSIOTCR2.2TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
TD4YMTCR2.1Transmit Side D4 Yellow Alarm Select.
0 = zeros in Bit 2 of all channels
1 = a one in the S–bit position of frame 12
TB7ZSTCR2.0Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a one in channels with all zeros
OUTPUT PIN TEST MODES Table 9-1
TEST 1TEST 0EFFECT ON OUTPUT PINS0operate normally1force all of the selected framer’s output pins 3–state
(excludes other framers I/O pins and parallel port pins)0force all of the selected framer’s output pins low (excludes
other framers I/O pins and parallel port pins)1force all of the selected framer’s output pins high (excludes
other framers I/O pins and parallel port pins)
DS21FT42/DS21FF42
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)(LSB)
TESEODFRSAOTSCLKMRSCLKMRESEPLBFLB
SYMBOLPOSITIONNAME AND DESCRIPTION
TESECCR1.7Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
ODFCCR1.6Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
RSAOCCR1.5Receive Signaling All One’s. This bit should not be enabled
if hardware signaling is being utilized. See Section 14 for
more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKMCCR1.4TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSCLKMCCR1.3RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESECCR1.2Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLBCCR1.1Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLBCCR1.0Framer Loopback.
0 = loopback disabled
1 = loopback enabled
PAYLOAD LOOPBACK
When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing
applications. In a PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs
corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS21Q42. When PLB is
enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK
2. All of the receive side signals will continue to operate normally
3. The TCHCLK and TCHBLK signals are forced low
4. Data at the TSER, and TSIG pins is ignored
5. The TLCLK signal will become synchronous with RCLK instead of TCLK
DS21FT42/DS21FF42
FRAMER LOOPBACK
When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback
is useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all one’s code will be transmitted at TPOS and TNEG
2. Data at RPOS and RNEG will be ignored
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will
cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)(LSB)
TFMTB8ZSTSLC96TZSERFMRB8ZSRSLC96RZSE
SYMBOLPOSITIONNAME AND DESCRIPTION
TFMCCR2.7Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZSCCR2.6Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
TSLC96CCR2.5Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this
bit to a one in D4 framing applications. Must be set to one to
source the Fs pattern. See Section 19 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
TZSECCR2.4Transmit FDL Zero Stuffer Enable. Set this bit to zero if
using the internal HDLC/BOC controller instead of the
legacy support for the FDL. See Section 19 for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
RFMCCR2.3Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZSCCR2.2Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
RSLC96CCR2.1Receive SLC–96 Enable. Only set this bit to a one in
D4/SLC–96 framing applications. See Section 19 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
RZSECCR2.0Receive FDL Zero Destuffer Enable. Set this bit to zero if
using the internal HDLC/BOC controller instead of the
legacy support for the FDL. See Section 19 for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB)(LSB)
RESMDMTCLKSRCRLOSF RSMSPDEECUSTLOOPTESMDM
SYMBOLPOSITIONNAME AND DESCRIPTION
RESMDMCCR3.7Receive Elastic Store Minimum Delay Mode. See Section
17 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
TCLKSRCCCR3.6Transmit Clock Source Select. This function allows the
user to internally select RCLK as the clock source for the
transmit side formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RLOSFCCR3.5Function of the RLOS/LOTC Output. Active only when
FMS = 1 (DS21Q41 emulation).
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
FMS is tied to ground for the DS21FF42/DS21FT42.
RSMSCCR3.4RSYNC Multiframe Skip Control. Useful in framing
format conversions from D4 to ESF. This function is not
available when the receive side elastic store is enabled.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
note: for this bit to have any affect, the RSYNC must be set
to output multiframe pulses (RCR2.4=1 and RCR2.3=0).
PDECCR3.3Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
ECUSCCR3.2Error Counter Update Select. See Section 12 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOPCCR3.1Transmit Loop Code Enable. See Section 20 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD register
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
TESMDMCCR3.0Transmit Elastic Store Minimum Delay Mode. See
Section 17 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
PULSE DENSITY ENFORCER
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:No more than 15 consecutive zerosAt least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)(LSB)
RSRERPCSIRFSA1RFERFFTHSETPCSITIRFS
SYMBOLPOSITIONNAME AND DESCRIPTION
RSRECCR4.7Receive Side Signaling Re–Insertion Enable. See Section
14 for details.
0 = do not re-insert signaling bits into the data stream
presented at the RSER pin
1 = reinsert the signaling bits into data stream presented at
the RSER pin
RPCSICCR4.6Receive Per–Channel Signaling Insert. See Section 14 for
more details.
0 = do not use RCHBLK to determine which channels should
have signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
RFSA1CCR4.5Receive Force Signaling All Ones. See Section 14 for more
details.
0 = do not force extracted robbed–bit signaling bit positions
to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFECCR4.4Receive Freeze Enable. See Section 14 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and
RSER if CCR4.7 = 1).
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
RFFCCR4.3Receive Force Freeze. Freezes receive side signaling at
RSIG (and RSER if CCR4.7=1); will override Receive
Freeze Enable (RFE). See Section 14 for details.
0 = do not force a freeze event
1 = force a freeze event
THSECCR4.2Transmit Hardware Signaling Insertion Enable. See
Section 14 for details.
0 = do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin.
1 = Insert the signaling from the TSIG pin into data stream
presented at the TSER pin.
TPCSICCR4.1Transmit Per–Channel Signaling Insert. See Section 14
for details.
0 = do not use TCHBLK to determine which channels should
have signaling inserted from the TSIG pin.
1 = use TCHBLK to determine which channels should have
signaling inserted from the TSIG pin.
TIRFSCCR4.0Transmit Idle Registers (TIR) Function Select. See
Section 15 for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
(i.e., Per = Channel Loopback function)
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB)(LSB)
TJC––TCM4TCM3TCM2TCM1TCM0
SYMBOLPOSITIONNAME AND DESCRIPTION
TJCCCR5.7Transmit Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculationCCR5.6Not Assigned. Must be set to zero when written.CCR5.5Not Assigned. Must be set to zero when written.
TCM4CCR5.4Transmit Channel Monitor Bit 4. MSB of a channel
decode that determines which transmit channel data will
appear in the TDS0M register. See Section 13 for details.
TCM3CCR5.3Transmit Channel Monitor Bit 3.
TCM2CCR5.2Transmit Channel Monitor Bit 2.
TCM1CCR5.1Transmit Channel Monitor Bit 1.
TCM0CCR5.0Transmit Channel Monitor Bit 0. LSB of the channel
decode.
DS21FT42/DS21FF42
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB)(LSB)
RJCRESALGNTESALGNRCM4RCM3RCM2RCM1RCM0
SYMBOLPOSITIONNAME AND DESCRIPTION
RJCCCR6.7Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
RESALGNCCR6.6Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers
to a minimum separation of half a frame. No action will be
taken if the pointer separation is already greater or equal to
half a frame. If pointer separation is less then half a frame,
the command will be executed and data will be disrupted.
Should be toggled after RSYSCLK has been applied and is
stable. Must be cleared and set again for a subsequent align.
See Section 17 for details.
TESALGNCCR6.5Transmit Elastic Store Align. Setting this bit from a zero to
a one may force the transmit elastic store’s write/read
pointers to a minimum separation of half a frame. No action
will be taken if the pointer separation is already greater or
equal to half a frame. If pointer separation is less then half a
frame, the command will be executed and data will be
disrupted. Should be toggled after TSYSCLK has been
applied and is stable. Must be cleared and set again for a
subsequent align. See Section 17 for details.
RCM4CCR6.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 13 for details.
RCM3CCR6.3Receive Channel Monitor Bit 3.
RCM2CCR6.2Receive Channel Monitor Bit 2.
RCM1CCR6.1Receive Channel Monitor Bit 1.
RCM0CCR6.0Receive Channel Monitor Bit 0. LSB of the channel
decode.
DS21FT42/DS21FF42
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB)(LSB)RLBRESRTESR––––
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR7.7Not Assigned. Should be set to zero when written to.
RLBCCR7.6Remote Loopback.
0 = loopback disabled
1 = loopback enabled
RESRCCR7.5Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one
frame. Receive data is lost during the reset. Should be
toggled after RSYSCLK has been applied and is stable. Do
not leave this bit set high.
TESRCCR7.4Transmit Elastic Store Reset. Setting this bit from a zero to
a one will force the transmit elastic store to a depth of one
frame. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. Do
not leave this bit set high.CCR7.3Not Assigned. Should be set to zero when written to.CCR7.2Not Assigned. Should be set to zero when written to.CCR7.1Not Assigned. Should be set to zero when written to.CCR7.0Not Assigned. Should be set to zero when written to.
REMOTE LOOPBACK
When CCR7.6 is set to a one, the DS21Q42 will be forced into Remote LoopBack (RLB). In this
loopback, data input via the RPOS and RNEG pins will be transmitted back to the TPOS and TNEG pins.
Data will continue to pass through the receive side framer of the DS21Q42 as it would normally and the
data from the transmit side formatter will be ignored. Please see Figure 6-1 for more details.
10. STATUS AND INFORMATION REGISTERS
There is a set of nine registers per channel that contain information on the current real time status of a
framer in the DS21Q42, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers
1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller. The
specific details on the four registers pertaining to the HDLC and BOC controller are covered in Section
19 but they operate the same as the other status registers in the DS21Q42 and this operation is described
below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these nine registers
will be set to a one. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched
fashion. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the
bit will remain set if the alarm is still present). There are bits in the four HDLC and BOC status registers
DS21FT42/DS21FF42
The user will always precede a read of any of the nine registers with a write. The byte written to the
register will inform the DS21Q42 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in
the bit positions he or she does not wish to obtain the latest information on. When a one is written to a
bit location, the read register will be updated with the latest information. When a zero is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q42 with higher–order software languages.
The SR1, SR2, and FDLS registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The FIMR register is covered in Section 19. The
INTERRUPT STATUS REGISTER can be used to determine which framer is requesting interrupt
servicing and the type of the request: status or the HDLC controller.
The interrupts caused by alarms in SR1 (namely RYEL, RCL, RBL, RLOS and LOTC) act differently
than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, RSLIP, RMF, TMF, SEC,
RFDL, TFDL, RMTCH, RAF, and RSC) and HIMR. The alarm caused interrupts will force the INT* pin
low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear
criteria in Table 11-1). The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
ISR: INTERRUPT STATUS REGISTER (Any address from A0H to FFH)
(MSB)(LSB)
F3HDLCF3SRF2HDLCF2SRF1HDLCF1SRF0HDLCF0SR
SYMBOLPOSITIONNAME AND DESCRIPTION
F3HDLCISR.7FRAMER 3 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F3SRISR.6FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
F2HDLCISR.5FRAMER 2 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F2SRISR.4FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F1HDLCISR.3FRAMER 1 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F1SRISR.2FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F0HDLCISR.1FRAMER 0 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F0SRISR.0FRAMER 0 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB)(LSB)
COFA8ZD16ZDRESFRESESEFEB8ZSFBE
SYMBOLPOSITIONNAME AND DESCRIPTION
COFARIR1.7Change of Frame Alignment. Set when the last resync
resulted in a change of frame or multiframe alignment.
8ZDRIR1.6Eight Zero Detect. Set when a string of at least eight
consecutive zeros (regardless of the length of the string) have
been received at RPOS and RNEG.
16ZDRIR1.5Sixteen Zero Detect. Set when a string of at least sixteen
consecutive zeros (regardless of the length of the string) have
been received at RPOS and RNEG.
RESFRIR1.4Receive Elastic Store Full. Set when the receive elastic
store buffer fills and a frame is deleted.
RESERIR1.3Receive Elastic Store Empty. Set when the receive elastic
store buffer empties and a frame is repeated.
SEFERIR1.2Severely Errored Framing Event. Set when 2 out of 6
framing bits (Ft or FPS) are received in error.
B8ZSRIR1.1B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOS and RNEG independent of whether the
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
FBERIR1.0Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing
bit is received in error.
RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB)(LSB)
RLOSCRCLCTESFTESETSLIPRBLCRPDVTPDV
SYMBOLPOSITIONNAME AND DESCRIPTION
RLOSCRIR2.7Receive Loss of Sync Clear. Set when the framer achieves
synchronization; will remain set until read.
RCLCRIR2.6Receive Carrier Loss Clear. Set when the carrier signal is
restored; will remain set until read. See Table 11-1.
TESFRIR2.5Transmit Elastic Store Full. Set when the transmit elastic
store buffer fills and a frame is deleted.
TESERIR2.4Transmit Elastic Store Empty. Set when the transmit
elastic store buffer empties and a frame is repeated.
TSLIPRIR2.3Transmit Elastic Store Slip Occurrence. Set when the
transmit elastic store has either repeated or deleted a frame.
RBLCRIR2.2Receive Blue Alarm Clear. Set when the Blue Alarm (AIS)
is no longer detected; will remain set until read. See Table
RPDVRIR2.1Receive Pulse Density Violation. Set when the receive data
stream does not meet the ANSI T1.403 requirements for
pulse density.
TPDVRIR2.0Transmit Pulse Density Violation. Set when the transmit
data stream does not meet the ANSI T1.403 requirements for
pulse density.
RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
(MSB)(LSB)––LORC–––RAIS-CI
SYMBOLPOSITIONNAME AND DESCRIPTIONRIR3.7Not Assigned. Could be any value when read.RIR3.6Not Assigned. Could be any value when read.RIR3.5Not Assigned. Could be any value when read.
LORCRIR3.4Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 us (3 us ��1 us).RIR3.3Not Assigned. Could be any value when read.RIR3.2Not Assigned. Could be any value when read.RIR3.1Not Assigned. Could be any value when read.
DS21FT42/DS21FF42
SR1: STATUS REGISTER 1 (Address=20 Hex)
(MSB)(LSB)
LUPLDNLOTCRSLIPRBLRYELRCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPSR1.7Loop Up Code Detected. Set when the loop up code as
defined in the RUPCD register is being received. See
Section 20 for details.
LDNSR1.6Loop Down Code Detected. Set when the loop down code
as defined in the RDNCD register is being received. See
Section 20 for details.
LOTCSR1.5Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 5.2 us). Will force the
RLOS/LOTC pin high if enabled via CCR3.5. Also will
force transmit side formatter to switch to RCLK if so enabled
via TCR1.7.
RSLIPSR1.4Receive Elastic Store Slip Occurrence. Set when the
receive elastic store has either repeated or deleted a frame.
RBLSR1.3Receive Blue Alarm. Set when an unframed all one’s code
is received at RPOS and RNEG.
RYELSR1.2Receive Yellow Alarm. Set when a yellow alarm is received
at RPOS and RNEG.
RCLSR1.1Receive Carrier Loss. Set when a red alarm is received at
RPOS and RNEG.
RLOSSR1.0Receive Loss of Sync. Set when the device is not
synchronized to the receive T1 stream.
DS21FT42/DS21FF42
ALARM CRITERIA Table 10-1
ALARMSET CRITERIACLEAR CRITERIA
Blue Alarm (AIS) (see note 1
below)
when over a 3 ms window, 5 or
less zeros are received
when over a 3 ms window, 6
or more zeros are received
Yellow Alarm (RAI)
1. D4 Bit 2 mode(RCR2.2=0)
2. D4 12th F–bit mode
(RCR2.2=1; this mode is also
referred to as the “Japanese
Yellow Alarm”)
3. ESF mode
when Bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences
when the 12th framing bit is set
to one for two consecutive
occurrences
when 16 consecutive patterns of
00FF appear in the FDL
when Bit 2 of 256 consecutive
channels is set to zero for less
than 254 occurrences
when the 12th framing bit is
set to zero for two consecutive
occurrences
when 14 or less patterns of
00FF hex out of 16 possible
appear in the FDL
Red Alarm (RCL) (this alarm is
also referred to as Loss Of
Signal)
when 192 consecutive zeros are
received
when 14 or more ones out of
112 possible bit positions are
received starting with the first
one received
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all ones signal. Blue alarm
detectors should be able to operate properly in the presence of a 10–3 error rate and they should not
falsely trigger on a framed all ones signal. The blue alarm criteria in the DS21Q42 has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
2. ANSI specifications use a different nomenclature than the DS21Q42 does; the following terms are
equivalent:
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
DS21FT42/DS21FF42
SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB)(LSB)
RMF TMF SEC RFDL TFDL RMTCH RAF RSC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2.7Receive Multiframe. Set on receive multiframe boundaries.
TMFSR2.6Transmit Multiframe. Set on transmit multiframe
boundaries.
SECSR2.5One Second Timer. Set on increments of one second based
on RCLK; will be set in increments of 999 ms, 999 ms, and
1002 ms every 3 seconds.
RFDLSR2.4Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
TFDLSR2.3Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
RMTCHSR2.2Receive FDL Match Occurrence. Set when the RFDL
matches either RMTCH1 or RMTCH2.
RAFSR2.1Receive FDL Abort. Set when eight consecutive one’s are
received in the FDL.
RSCSR2.0Receive Signaling Change. Set when the DS21Q42 detects
a change of state in any of the robbed–bit signaling bits.
IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)
(MSB)(LSB)
LUPLDNLOTCSLIPRBLRYELRCLRLOS
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPIMR1.7Loop Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
LDNIMR1.6Loop Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
LOTCIMR1.5Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
SLIPIMR1.4Elastic Store Slip Occurrence.
0 = interrupt masked
1 = interrupt enabled
RBLIMR1.3Receive Blue Alarm.
0 = interrupt masked
1 = interrupt enabled
RYEIMR1.2Receive Yellow Alarm.
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
RCLIMR1.1Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
RLOSIMR1.0Receive Loss of Sync.
0 = interrupt masked
1 = interrupt enabled
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB)(LSB)
RMFTMFSECRFDLTFDLRMTCHRAFRSC
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2.7Receive Multiframe.
0 = interrupt masked
1 = interrupt enabled
TMFIMR2.6Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
SECIMR2.5One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDLIMR2.4Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
TFDLIMR2.3Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
RMTCHIMR2.2Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
RAFIMR2.1Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
RSCIMR2.0Receive Signaling Change.
0 = interrupt masked
1 = interrupt enabled
11. ERROR COUNT REGISTERS
There are a set of three counters in each framer that record bipolar violations, excessive zeros, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on either one second boundaries
(CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence,
these registers contain performance data from either the previous second or the previous 42 ms. The user
DS21FT42/DS21FF42
respective maximum counts and they will not rollover (note: only the Line Code Violation Count
Register has the potential to overflow but the bit error would have to exceed 10-2 before this would
occur).
LINE CODE VIOLATION COUNT REGISTER (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive zeros. See Table 12-1 for details of exactly what the LCVCRs count. If
the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This
counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
(MSB)(LSB)
LCV15LCV14LCV13LCV12LCV11LCV10LCV9LCV8LCVCR1
LCV7LCV6LCV5LCV4LCV3LCV2LCV1LCV0LCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
LCV15LCVCR1.7MSB of the 16–bit code violation count
LCV0LCVCR2.0LSB of the 16–bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 11-1
COUNT EXCESSIVE
ZEROS
(RCR1.7)
B8ZS ENABLED
(CCR2.2)
WHAT IS COUNTED
IN THE LCVCRsnoBPVs
yesnoBPVs + 16 consecutive zerosyesBPVs (B8ZS code words not
counted)
yesyesBPV’s + 8 consecutive zeros
PATH CODE VIOLATION COUNT REGISTER
(PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1),
PCVCR will automatically be set as a 12–bit counter that will record errors in the CRC6 code words.
When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the
Ft framing bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs
framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1)
conditions. See Table 12-2 for a detailed description of exactly what errors the PCVCR counts.
DS21FT42/DS21FF42
PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)
(MSB)(LSB)
(note 1)(note 1)(note 1)(note 1)CRC/
FB11
CRC/
FB10
CRC/
FB9
CRC/
FB8
PCVCR1
CRC/
FB7
CRC/
FB6
CRC/
FB5
CRC/
FB4
CRC/
FB3
CRC/
FB2
CRC/
FB1
CRC/
FB0
PCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC/FB11PCVCR1.3MSB of the 12–Bit CRC6 Error or Frame Bit Error
Count (note #2)
CRC/FB0PCVCR2.0LSB of the 12–Bit CRC6 Error or Frame Bit Error Count
(note #2)
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register
2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in
the framing bit position (in the D4 framing mode; CCR2.3=0).
PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 11-2
FRAMING MODE
(CCR2.3)
COUNT Fs ERRORS
(RCR2.1)
WHAT IS COUNTED
IN THE PCVCRsnoerrors in the Ft patternyeserrors in both the Ft & Fs
patterns
ESFdon’t careerrors in the CRC6 code words
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)
conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS =
1)conditions. See Table 12-3 for a detailed description of what the MOSCR is capable of counting.
DS21FT42/DS21FF42
MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1(Address = 25 Hex)
MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2(Address = 27 Hex)
(MSB)(LSB)
MOS/
FB11
MOS/
FB10
MOS/
FB9
MOS/
FB8
(note 1)(note 1)(note 1)(note 1)MOSCR1
MOS/
FB7
MOS/
FB6
MOS/
FB5
MOS/
FB4
MOS/
FB3
MOS/
FB2
MOS/
FB1
MOS/
FB0
MOSCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
MOS/FB11MOSCR1.7MSB of the 12–Bit Multiframes Out of Sync or F–Bit
Error Count (note #2)
MOS/FB0MOSCR2.0LSB of the 12–Bit Multiframes Out of Sync or F–Bit
Error Count (note #2)
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of
sync (RCR2.0=1)
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 11-3
FRAMING MODE
(CCR2.3)
COUNT MOS OR F–BIT
ERRORS
(RCR2.0)
WHAT IS COUNTED
IN THE MOSCRsMOSnumber of multiframes out of
syncF–Biterrors in the Ft pattern
ESFMOSnumber of multiframes out of
sync
ESFF–Biterrors in the FPS pattern
12. DS0 MONITORING FUNCTION
Each framer in the DS21Q42 has the ability to monitor one DS0 64 Kbps channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the
CCR5 register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be
properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0
Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the
Receive DS0 (RDS0M) register.
DS21FT42/DS21FF42
The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the
appropriate T1 channel. Channels 1 through 24 map to register values 0 through 23. For example, if
DS0 channel 6 (timeslot 5) in the transmit direction and DS0 channel 15 (timeslot 14) in the receive
direction needed to be monitored, then the following values would be programmed into CCR5 and
CCR6:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
[repeated here from section 10 for convenience]
(MSB)(LSB)
TJC––TCM4TCM3TCM2TCM1TCM0
SYMBOLPOSITIONNAME AND DESCRIPTION
TJCCCR5.7Transmit Japanese CRC Enable. See Section 10 for
details.CCR5.5Not Assigned. Must be set to zero when written.CCR5.5Not Assigned. Must be set to zero when written.
TCM4CCR5.4Transmit Channel Monitor Bit 4. MSB of a channel
decode that determines which transmit DS0 channel data will
appear in the TDS0M register.
TCM3CCR5.3Transmit Channel Monitor Bit 3.
TCM2CCR5.2Transmit Channel Monitor Bit 2.
TCM1CCR5.1Transmit Channel Monitor Bit 1.
TCM0CCR5.0Transmit Channel Monitor Bit 0. LSB of the channel
decode that determines which transmit DS0 channel data will
appear in the TDS0M register.
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
(MSB)(LSB)B2B3B4B5B6B7B8
SYMBOLPOSITIONNAME AND DESCRIPTIONTDS0M.7Transmit DS0 Channel Bit 1. MSB of the DS0 channel
(first bit to be transmitted).TDS0M.6Transmit DS0 Channel Bit 2.TDS0M.5Transmit DS0 Channel Bit 3.TDS0M.4Transmit DS0 Channel Bit 4.TDS0M.3Transmit DS0 Channel Bit 5.
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTIONTDS0M.2Transmit DS0 Channel Bit 6.TDS0M.1Transmit DS0 Channel Bit 7.TDS0M.0Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 10 for convenience]
(MSB)(LSB)
RJCRESALGNTESALGNRCM4RCM3RCM2RCM1RCM0
SYMBOLPOSITIONNAME AND DESCRIPTION
RJCCCR6.7Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
RESALGNCCR6.6Receive Elastic Store Align. Setting this bit from a zero to a
one will force the receive elastic store’s write/read pointers to
a minim separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after RSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 17 for details.
TESALGNCCR6.5Transmit Elastic Store Align. Setting this bit from a zero to
a one will force the transmit elastic store’s write/read pointers
to a minimum separation of half a frame. If pointer
separation is already greater than half a frame, setting this bit
will have no effect. Should be toggled after TSYSCLK has
been applied and is stable. Must be cleared and set again for
a subsequent align. See Section 17 for details.
RCM4CCR6.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 13 for details.
RCM3CCR6.3Receive Channel Monitor Bit 3.
RCM2CCR6.2Receive Channel Monitor Bit 2.
RCM1CCR6.1Receive Channel Monitor Bit 1.
RCM0CCR6.0Receive Channel Monitor Bit 0. LSB of the channel
decode.
DS21FT42/DS21FF42
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex)
(MSB)(LSB)B2B3B4B5B6B7B8
SYMBOLPOSITIONNAME AND DESCRIPTIONRDS0M.7Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).RDS0M.6Receive DS0 Channel Bit 2.RDS0M.5Receive DS0 Channel Bit 3.RDS0M.4Receive DS0 Channel Bit 4.RDS0M.3Receive DS0 Channel Bit 5.RDS0M.2Receive DS0 Channel Bit 6.RDS0M.1Receive DS0 Channel Bit 7.RDS0M.0Receive DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be received).
13. SIGNALING OPERATION
Each framer in the DS21Q42 contains provisions for both processor based (i.e., software based) signaling
bit access and for hardware based access. Both the processor based access and the hardware based access
can be used simultaneously if necessary. The processor based signaling is covered in Section 14.1 and
the hardware based signaling is covered in Section 14.2.
14.1PROCESSOR BASED SIGNALING
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are
received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at
RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)(LSB)
A(8)A(7)A(6)A(5)A(4)A(3)A(2)A(1)RS1 (60)
A(16)A(15)A(14)A(13)A(12)A(11)A(10)A(9)RS2 (61)
A(24)A(23)A(22)A(21)A(20)A(19)A(18)A(17)RS3 (62)
B(8)B(7)B(6)B(5)B(4)B(3)B(2)B(1)RS4 (63)
B(16)B(15)B(14)B(13)B(12)B(11)B(10)B(9)RS5 (64)
B(24)B(23)B(22)B(21)B(20)B(19)B(18)B(17)RS6 (65)
A/C(8)A/C(7)A/C(6)A/C(5)A/C(4)A/C(3)A/C(2)A/C(1)RS7 (66)
A/C(16)A/C(15)A/C(14)A/C(13)A/C(12)A/C(11)A/C(10)A/C(9)RS8 (67)
A/C(24)A/C(23)A/C(22)A/C(21)A/C(20)A/C(19)A/C(18)A/C(17)RS9 (68)
B/D(8)B/D(7)B/D(6)B/D(5)B/D(4)B/D(3)B/D(2)B/D(1)RS10 (69)
B/D(16)B/D(15)B/D(14)B/D(13)B/D(12)B/D(11)B/D(10)B/D(9)RS11 6A)
DS21FT42/DS21FF42
SYMBOLPOSITIONNAME AND DESCRIPTION
D(24)RS12.7Signaling Bit D in Channel 24
A(1)RS1.0Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing
mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from the
previous multiframe. Hence, whether the framer is operated in either framing mode, the user needs only
to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on
multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status
Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are
frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent
signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also
available at the RSIG and RSER pins.
A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be
set. The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting the
IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out
of the RS1 to RS12 registers before the data will be lost.
TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB)(LSB)
A(8)A(7)A(6)A(5)A(4)A(3)A(2)A(1)TS1 (70)
A(16)A(15)A(14)A(13)A(12)A(11)A(10)A(9)TS2 (71)
A(24)A(23)A(22)A(21)A(20)A(19)A(18)A(17)TS3 (72)
B(8)B(7)B(6)B(5)B(4)B(3)B(2)B(1)TS4 (73)
B(16)B(15)B(14)B(13)B(12)B(11)B(10)B(9)TS5 (74)
B(24)B(23)B(22)B(21)B(20)B(19)B(18)B(17)TS7 (75)
A/C(8)A/C(7)A/C(6)A/C(5)A/C(4)A/C(3)A/C(2)A/C(1)TS7 (76)
A/C(16)A/C(15)A/C(14)A/C(13)A/C(12)A/C(11)A/C(10)A/C(9)TS8 (77)
A/C(24)A/C(23)A/C(22)A/C(21)A/C(20)A/C(19)A/C(18)A/C(17)TS9 (78)
B/D(8)B/D(7)B/D(6)B/D(5)B/D(4)B/D(3)B/D(2)B/D(1)TS10 (79)
B/D(16)B/D(15)B/D(14)B/D(13)B/D(12)B/D(11)B/D(10)B/D(9)TS11 (7A)
B/D(24)B/D(23)B/D(22)B/D(21)B/D(20)B/D(19)B/D(18)B/D(17)TS12 (7B)
SYMBOLPOSITIONNAME AND DESCRIPTION
D(24)TS12.7Signaling Bit D in Channel 24
A(1)TS1.0Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF
framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe
DS21FT42/DS21FF42
mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4
framing mode, there are only two signaling bits per channel (A and B). However in the D4 framing
mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The
framer will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
14.2HARDWARE BASED SIGNALING
RECEIVE SIDE
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the
signaling bits from the receive data stream and buffering them over a four multiframe buffer and
outputting them in a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode
is always enabled. In this mode, the receive elastic store may be enabled or disabled. If the receive
elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz.
In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each
channel. The RSIG data is updated once a multiframe (3 ms) unless a freeze is in effect. In the D4
framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel.
Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is
updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 24 for
some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data will be re–aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be
either 1.544 MHz or 2.048 MHz.
If the signaling re–insertion mode is enabled, the user can control which channels have signaling re–
insertion performed on a channel–by–channel basis by setting the RPCSI control bit high (CCR4.6) and
then programming the RCHBLK output pin to go high in the channels in which the signaling re–insertion
should not occur. If the RPCSI bit is set low, then signaling re–insertion will occur in all channels when
the signaling re–insertion mode is enabled (RSRE=1). How to control the operation of the RCHBLK
output pin is covered in Section 16.
In both hardware based signaling operating modes, the user has the option to replace all of the extracted
robbed–bit signaling bit positions with ones. This option is enabled via the RFSA1 control bit (CCR4.5)
and it can be invoked on a per–channel basis by setting the RPCSI control bit (CCR4.6) high and then
programming RCHBLK appropriately just like the per–channel signaling re–insertion operates.
The signaling data in the four multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore
TR– TSY–000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit
(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.
The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG
pin (and at the RSER pin if RSRE=1). When freezing is enabled (RFE=1), the signaling data will be held
in the last known good state until the corrupting error condition subsides. When the error condition
subsides, the signaling data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4
DS21FT42/DS21FF42
TRANSMIT SIDE
Via the THSE control bit (CCR4.2), the framer can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
user has the ability to control which channels are to have signaling data from the TSIG pin inserted into
them on a channel–by–channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is
enabled, channels in which the TCHBLK output has been programmed to be set high in, will not have
signaling data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the
framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is
enabled, the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.
14. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
Each framer in the DS21Q42 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section
15.1. The receive direction is from the T1 line to the backplane and is covered in Section 15.2.
15.1TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 15.1.1 was a
feature contained in the original DS21Q41 while the second method which is covered in Section 15.1.2 is
a new feature of the DS21Q42.
15.1.1Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 24 T1 channels. If this method is
used, then the CCR4.0 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.

Partno	Mfg	Dc	Qty	Available	Descript
DS21FF42+	MAIXM	N/a	1500	avai	4 x 4 16 Channel T1 Framer / 4 x 3 12 Channel T1 Framer