DS2196LN ,T1 Dual Framer LIUFEATURES The DS2196 T1 dual framer LIU is designed for T1 § Two full-featured framers and a short/l ..
DS2196LN ,T1 Dual Framer LIUTABLE OF CONTENTS1 INTRODUCTION.. 61.1 FEATURE HIGHLIGHTS...... 61.2 TYPICAL
DS2196LN+ ,T1 Dual Framer LIUFEATURES The DS2196 T1 dual framer LIU is designed for T1 § Two full-featured framers and a short/l ..
DS21FF42 ,4 x 4 16 Channel T1 Framer / 4 x 3 12 Channel T1 FramerFEATURESP 300-pin MCM 1.27mm pitch BGA package 16 or 12 completely independent T1 framers(27mm x ..
DS21FF42+ ,4 x 4 16 Channel T1 Framer / 4 x 3 12 Channel T1 FramerFEATURESP 300-pin MCM 1.27mm pitch BGA package 16 or 12 completely independent T1 framers(27mm x ..
DS21FF44 ,4x3 Twelve Channel E1 Framer / 4x4 Sixteen Channel E1 FramerAPPLICATIONS 16 or 12 completely independent E1 framers DSLAMsin one small 27mm x 27mm package ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2196LN
T1 Dual Framer LIU
GENERAL DESCRIPTION The DS2196 T1 dual framer LIU is designed for T1 transmission equipment. The DS2196 combines dual optimized framers together with a LIU. This
combination allows the users to extract and insert
facility data-link (FDL) messages in the receive and transmit paths, collect line performance data, and
perform basic channel conditioning and maintenance. The DS2196 contains all of the necessary functions
for connection to T1 lines whether they are DS1 long
haul or DSX–1 short haul. The clock recovery
circuitry automatically adjusts to T1 lines from 0ft to over 6000ft in length. The device can generate both DSX–1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms.
The device contains a set of internal registers that the user can access and use to control the unit’s operation
of the unit. Quick access through the parallel control port allows a single controller to handle many T1
lines. The device fully meets all of the latest T1
specifications.
PACKAGE OUTLINE
FEATURES § Two full-featured framers and a short/long-haul
line interface unit (LIU) in one small package § Based on Dallas Semiconductor’s single-chip
transceiver (SCT) family § Two HDLC controllers with 64-byte buffers that
can be used for the FDL or DS0 channels § Supports NPRMs and SPRMs as per ANSI
T1.403-1998 § Can be combined with a short/long-haul LIU or a
HDSL modem chipset to create a low-cost office
repeater/NIU/CSU, or a HDSL1/HDSL2 terminal
unit with enhanced monitoring and data link
control
§ Supports fractional T1 § Can convert from D4 to ESF framing and ESF to
D4 framing § 32-bit or 128-bit crystal-less jitter attenuator
§ Can generate and detect repeating in-band
patterns from 1 to 8 bits or 16 bits in length
§ Detects and generates RAI-CI and AIS-CI § Generates DS1 idle codes § On-chip programmable BERT generator and
detector
§ All key signals are routed to pins to support
numerous hardware configurations § Supports both NRZ and bipolar interfaces
§ Can create errors in the F-bit position and BERT
interface data paths
§ 8-bit parallel control port that can be used
directly on either multiplexed or nonmultiplexed
buses (Intel or Motorola) § IEEE 1149.1 JTAG Boundary Scan
§ 3.3V supply with 5V tolerant inputs and outputs § 100-pin LQFP (14 mm x 14 mm) package
ORDERING INFORMATION TEMP RANGE 0ºC to +70ºC -40ºC to +85ºC
T1 Dual Framer LIU
DS2196
TABLE OF CONTENTSINTRODUCTION................................................................................................................................61.1 FEATURE HIGHLIGHTS..................................................................................................................61.2 TYPICAL APPLICATIONS.............................................................................................................10
1.3 FUNCTIONAL DESCRIPTION.......................................................................................................10
PIN DESCRIPTION..........................................................................................................................10PIN FUNCTION DESCRIPTION....................................................................................................13REGISTER MAP...............................................................................................................................21PARALLEL PORT............................................................................................................................27CONTROL, ID, AND TEST REGISTERS.....................................................................................27
7 STATUS AND INFORMATION REGISTERS............................................................................51
8 ERROR COUNT REGISTERS.......................................................................................................64SIGNALING OPERATION..............................................................................................................68
10 DS0 MONITORING FUNCTION..................................................................................................70
11 PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.....................................7211.1TRANSMIT SIDE CODE GENERATION..................................................................................72
11.2RECEIVE SIDE CODE GENERATION......................................................................................73
12 PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION.........................74
13 CLOCK BLOCKING REGISTERS..............................................................................................83
14 TRANSMIT TRANSPARENCY....................................................................................................85
15 BERT FUNCTION..........................................................................................................................8615.1BERT REGISTER DESCRIPTION..............................................................................................88
16 ERROR INSERTION FUNCTION...............................................................................................96
17 HDLC CONTROLLER..................................................................................................................9917.1HDLC FOR DS0S.........................................................................................................................100
18 FDL/FS EXTRACTION AND INSERTION..............................................................................10118.1HDLC AND BOC CONTROLLER FOR THE FDL..................................................................101
18.1.1General Overview.................................................................................................................10118.1.2Status Register for the HDLC...............................................................................................103
18.1.3Basic Operation Details........................................................................................................103
18.1.4HDLC/BOC Register Description........................................................................................105
DS2196
18.2LEGACY FDL SUPPORT..........................................................................................................115
18.2.1Overview...............................................................................................................................115
18.2.2Receive Section.....................................................................................................................115
18.2.3Transmit Section...................................................................................................................11618.3D4/SLC–96 OPERATION..........................................................................................................117
LINE INTERFACE FUNCTION................................................................................................11819.1RECEIVE CLOCK AND DATA RECOVERY.........................................................................118
19.2TRANSMIT WAVESHAPING AND LINE DRIVING.............................................................119
19.3 JITTER ATTENUATOR..........................................................................................................120
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT......................12420.1DESCRIPTION................................................................................................................................124
20.2TAP CONTROLLER STATE MACHINE............................................................................................125
20.3INSTRUCTION REGISTER AND INSTRUCTIONS................................................................................127
TIMING DIAGRAMS..................................................................................................................133OPERATING PARAMETERS...................................................................................................141100-PIN LQFP PACKAGE SPECIFICATIONS......................................................................157
DS2196
LIST OF FIGURES
Figure 1-1: T1 Dual Framer LIU..............................................................................................................9
Figure 15-1: BERT Mux Diagram..........................................................................................................87
Figure 19-1: External Analog Connections..........................................................................................121
Figure 19-2: Jitter Tolerance.................................................................................................................122
Figure 19-3: Transmit Waveform Template........................................................................................122Figure 19-4: Jitter Attenuation..............................................................................................................123
Figure 20-1: Boundary Scan Architecture...........................................................................................124
Figure 20-2: TAP Controller State Machine........................................................................................127
Figure 21-1: Receive Side D4 Timing....................................................................................................133
Figure 21-2: Receive Side ESF Timing.................................................................................................134Figure 21-3: Receive Side Boundary Timing.......................................................................................135
Figure 21-4: Transmit Side D4 Timing.................................................................................................136
Figure 21-5: Transmit Side ESF Timing..............................................................................................137
Figure 21-6: Transmit Side Boundary Timing....................................................................................138
Figure 21-7: Transmit Data Flow..........................................................................................................139Figure 21-8: Receive Data Flow.............................................................................................................140
Figure 22-1: Intel Bus Read AC Timing (BTS=0 / MUX = 1)............................................................146
Figure 22-2: Intel Bus Write Timing (BTS=0 / MUX=1)....................................................................147
Figure 22-3: Motorola Bus AC Timing (BTS = 1 / MUX = 1)............................................................148
Figure 22-4: Intel Bus Read AC Timing (BTS=0 / MUX=0)..............................................................149Figure 22-5: Intel Bus Write AC Timing (BTS=0 / MUX=0).............................................................150
Figure 22-6: Motorola Bus Read AC Timing (BTS=1 / MUX=0)......................................................151
Figure 22-7: Motorola Bus Write AC Timing (BTS=1 / MUX=0).....................................................152
Figure 22-8: Receive Side AC Timing...................................................................................................153
Figure 22-9: Receive Line Interface AC Timing..................................................................................154Figure 22-10: Transmit Side AC Timing..............................................................................................155
Figure 22-11: Transmit Line Interface Side AC Timing.....................................................................156
DS2196
LIST OF TABLES
Table 2-1: Pin Description Sorted by Pin Number................................................................................10
Table 4-1: Register Map Sorted by Address..........................................................................................21
Table 6-1: Output Pin Test Modes..........................................................................................................36
Table 6-2: Receive Data Source Mux Modes.........................................................................................37
Table 6-3: TPOSB/TNEGB Data Source Select.....................................................................................38Table 7-1: Receive T1 Level Indication..................................................................................................57
Table 7-2: Alarm Criteria........................................................................................................................59
Table 8-1: Line Code Violation Counting Arrangements.....................................................................66
Table 8-2: Path Code Violation Counting Arrangements.....................................................................67
Table 8-3: Multiframes Out Of Sync Counting Arrangements............................................................67Table 12-1: Transmit Code Length.........................................................................................................75
Table 12-2: Receive Code Length ...........................................................................................................75
Table 15-1: Bert Pattern Select Options.................................................................................................89
Table 15-2: Repetitive Pattern Length Options.....................................................................................90
Table 15-3: Bert Rate Insertion Select....................................................................................................91Table 16-1: Error Rate Options..............................................................................................................98
Table 16-2: Error Insertion examples.....................................................................................................99
Table 17-1: Transmit HDLC Configuration..........................................................................................99
Table 18-1: HDLC/BOC Controller Register List...............................................................................102
Table 19-1: Line Build Out Select In LICR.........................................................................................119Table 19-2: Transformer Specifications...............................................................................................120
Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture............................128
Table 20-2: ID Code Structure..............................................................................................................128
Table 20-3: Device ID Codes..................................................................................................................129
Table 20-4: Boundary Scan Register Description................................................................................130
DS2196
1. INTRODUCTION
The DS2196 is a derivative of the DS21352 T1 SCT. The feature set has been optimized for transport
applications commonly found in T1 transmission equipment. The DS2196 register map and register bit
definitions are compatible with the DS21352/DS21552, allowing for easy migration to the DS2196.
Interface designs requiring per-channel code insertion, elastic stores, and ANSI 1’s density monitoring
should use the DS21352 or DS21552.
1.1 Feature HighlightsMain features– Two full-featured independent framersShort/long haul LIU100-pin LQFP small package3.3V operation with 5V tolerant I/O8-bit parallel control port– Multiplexed or nonmultiplexed busesIntel or Motorola formatsPolled or interrupt environmentsHDLC SupportTwo independent HDLC controllers– 64-byte Rx and Tx buffersAccess FDL or single/multiple DS0
channelsANSI T1.403-1998 supportNPRMs– SPRMsRAI-CI detection and generationAIS-CI detection and generationFormat ConversionD4 to ESF framing– ESF to D4 framingLIULong and short-haul supportReceive sensitivity: 0dB to -36dB32-bit or 128-bit crystal-less jitterattenuatorDSX-1 and CSU line buildout optionsProvisions for custom waveform
generationDS1 Idle Code Generation– User-definedFixed 7F HexDigital milliwattIn-band repeating pattern generator and
detector– Programmable pattern generatorThree programmable pattern detectorsPatterns from 1 to 8 bits or 16 bits inlengthProgrammable on-chip bit error-rate testingPseudorandom patterns including QRSSUser-defined repetitive patternsDaly pattern– Error insertionBit and error countsPayload Error InsertionError insertion in the payload portion of
the T1 frame in the transmit path– Errors can be inserted over the entire
frame or selected channelsInsertion options include continuous and
absolute number with selectable insertion
ratesFunction IsolationAll key signals are routed to pinsLIU, Framer A, and Framer B can be
disconnected from each otherSupports both NRZ and bipolar interfacesF-bit corruption for line testingProgrammable output clocks for FractionalFully independent transmit and receive
functionality in each framerLarge path and line error counters including
BPV, CV, CRC6, and framing bit errorsAbility to calculate and check CRC6
according to the Japanese standardAbility to generate Yellow Alarm accordingto the Japanese standardPer channel loopbackRCL, RLOS, RRA, and RAIS alarms
interrupt on change of stateHardware pins to indicate receive loss-of-sync and receive bipolar violationsIEEE 1149.1 JTAG Boundary Scan
DS2196
1.2 Typical Applications
1.3 Functional Description
The analog AMI/B8ZS waveform off of the T1 line is transformer coupled into the RRING and RTIP
pins of the DS2196. The device recovers clock and data from the analog signal and passes it through the
optional jitter attenuator to the receive side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS2196 contains an active filter that reconstructs the analog received
signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0dB to –36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive side
framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming alarms including,
carrier loss, loss of synchronization, blue (AIS) and yellow alarms.
The transmit side of the DS2196 is totally independent from the receive side in both the clockrequirements and characteristics. The transmit formatter will provide the necessary frame/multiframe data
overhead for T1 transmission. Once the data stream has been prepared for transmission, it is sent via the
optional jitter attenuator to the wave shaping and line driver functions. The DS2196 will drive the T1 line
from the TTIP and TRING pins via a coupling transformer. The line driver can handle both long haul
(CSU) and short haul (DSX–1) lines.
Interface
1.544 MHz
Network
Interface
1.544 MHz
Interface
OFFICE REPEATER/NIU
Telco
Interface
1.544 MHz
Interface
(Remote or
CO Located)
1.544 MHz
Interface
CSU APPLICATIONHDSL1/HDSL2 APPLICATION
T3/SONET/OPTICAL MULTIPLEXER
DS2196
Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In
each 125�s frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sentfirst followed by channel 1. Each channel is made up of 8 bits that are numbered 1 to 8. Bit number 1 is
the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The following
abbreviations are used throughout this data sheet:
DS2196
ece
ive
ide
ansm
it S
atter A
D0 to D7 /
AD0 to AD7
BTS
INT*
TSYNCA
TCLKA
TCHCLKA/
TLCLKA
TSERA
TCHBLKA/
TLINKA
WR*(R/W*)
RD*(DS*)
RCHCLKA/
RLCLKA
CS*
RCHBLKA/
RLINKA
RLOSA / LOTCA
ALE(AS) / A7
A0 to A6
MUX
RCL
RPOSLO
RNEGLO
RNEGIA
RPOSIA
TPOSLI
TNEGLI
TNEGOA/
TFSYNCA
TPOSOA/
TNRZA
RCLKLO
RCLKIA
TCLKLI
TCLKOA
TCHCLKB
TLCLKB
TCHBLKB/
TLINKB
RLOSB / LOTCB
RCHCLKB/
RLCLKB
RCHBLKB/
RLINKB
RCLKB
RMSYNCB
RSERB
RFSYNCB
WPS
PNRZPCLK
FSYNC
LCL
RPOS
RNEG
TFSY
ece
ive
ide
JTCLK
JTMS
JTDO
JTDI
JTRST*
DVSS
(3)
RVSS
TVDDTV
RVDDDVDD
(3)
RXARXBTXRBPVA
RBPVB
from
ecei
ram
er
nly in
FT
plic
SYNUOP0
UOP1
UOP2
UOP3
From
BERT
Figure 1-1. T1 Dual Framer LIU
DS2196
2. PIN DESCRIPTION
Table 2-1. Pin Description Sorted by Pin Number
DS2196
DS2196
DS2196
3. PIN FUNCTION DESCRIPTION
Transmit Side Pins
Signal Name:TCLKA/B
Signal Description:Transmit ClockSignal Type:InputA 1.544 MHz primary clock is applied here. Used to clock data through the transmit side formatters. TCLKA/B
can be internally connected to RCLKB/A via the CCR4B.2 control bit.
Signal Name:TSERA/B
Signal Description:Transmit Serial DataSignal Type:InputTransmit NRZ serial data. Sampled on the falling edge of TCLKA or TCLKB. TSERA/B can be internally
connected to RSERB/A via the CCR4B.2 control bit.
Signal Name:TSYNCA/B
Signal Description:Transmit SyncSignal Type:Input / Output
When programmed as an input, a pulse at this pin will establish either frame or multiframe boundaries for thetransmit side. Via TCR2A.2 and TCR2B.2, the DS2196 can be programmed to output either a frame or multiframe
pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2A.4 and
TCR2B.4 to output double–wide pulses at signaling frames. See Section 21 for details. TSYNCA/B can beinternally connected to RMSYNCB/A via the CCR4B.2 control bit.
Signal Name:TCHCLKA/B / TLCLKA/BSignal Description:Transmit Channel Clock / Transmit Link ClockSignal Type:Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHCLK is selected, a192-kHz clock, which pulses high during the LSB of each channel, will be output. If TLCLK is selected, either a 4
kHz or 2 kHz (ZBTSI) demand clock for the TLINK data is output. This output signal is always synchronous with
TCLKA or TCLKB. See Section 21 for details.
Signal Name:TCHBLKA/B / TLINKA/B
Signal Description:Transmit Channel Block / Transmit Link DataSignal Type:Input / Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHBLK is selected, auser programmable output that can be forced high or low during any of the 24 T1 channels is output. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as
Fractional T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for external per–channel loopback, and for per–channel conditioning. See Section 21 for
details. If TLINK is selected, this pin will be sampled on the falling edge of TCLKA or TCLKB for data insertion
into either the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 21 fordetails. This signal is always synchronous with TCLKA or TCLKB.
Signal Name:TPOSOA/B / TNRZA/BSignal Description:Transmit Positive & NRZ Data OutputSignal Type:Output
Updated on the rising edge of TCLKOA and rising or falling edge of TCLKOB with either bipolar data or NRZdata out of the transmit side formatter. This pin can be programmed to source NRZ data via the Output Data
Format (CCR1A.6 and CCR1B.6) control bits.
DS2196
Signal Name:TNEGA/B / TFSYNCA/B
Signal Description:Transmit Negative Data & Frame Sync Pulse OutputSignal Type:OutputUpdated on the rising edge of TCLKA or TCLKB with either bipolar data or a frame sync pulse out of the transmit
side formatter. This pin can be programmed to source the frame sync pulse via the Output Data Format (CCR1A.6and CCR1B.6) control bits.
Receive Framer Pins
Signal Name:RCHCLKA/B / RLCLKA/B
Signal Description:Receive Channel Clock / Receive Link ClockSignal Type:Output
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHCLK is selected, a
192-kHz clock, which pulses high during the LSB of each channel, will be output. If RLCLK is selected, either a 4kHz or 2 kHz (ZBTSI) clock for the RLINK data is output. This output signal is always synchronous with RCLKA
or RCLKB.
Signal Name:RCHBLKA/B / RLINKA/B
Signal Description:Receive Channel Block / Receive Link Data
Signal Type:OutputA dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHBLK is selected, a
user programmable output that can be forced high or low during any of the 24 T1 channels. Useful for blockingclocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional
T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert
applications, for external per–channel loopback, and for per–channel conditioning. See Section 21 for details. IfRLINK is selected, then either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLKA before the start of a
frame are output. See Section 21 for details. This signal is always synchronous with RCLKA or RCLKB.
Signal Name:RSERA/BSignal Description:Receive Serial Data
Signal Type:OutputReceived NRZ serial data. Updated on rising edges of RCLKA or RCLKB.
Signal Name:RFSYNCA/BSignal Description:Receive Frame Sync
Signal Type:OutputAn extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies frame boundaries. Via
RCR2A.5 and RCR2B.5, RFSYNC can also be set to output double–wide pulses on signaling frames. This signal
is always synchronous with RCLKA or RCLKB.
Signal Name:RMSYNCA/B
Signal Description:Receive Multiframe Sync
Signal Type:OutputAn extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies multiframe boundaries.
This signal is always synchronous with RCLKA or RCLKB.
DS2196
Signal Name:RLOSA/B / LOTCA/B
Signal Description:Receive Loss of Sync / Loss of Transmit ClockSignal Type:OutputA dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle
high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not
been toggled for 5 �sec.
Signal Name:RBPVA/BSignal Description:Receive BPV
Signal Type:OutputThis pin will toggle high for one RCLKA or RCLKB clock cycle for each bipolar Violation (BPV) detected by the
framer.
Signal Name:RPOSIA/BSignal Description:Receive Positive Data Input
Signal Type:InputSampled on the falling edge of RCLKIA and either rising or falling edge of RCLKIB for data to be clocked
through the receive side framer. RPOSIA/B and RNEGIA/B can be tied together for a NRZ interface.
RPOSIA be internally connected to RPOSLO via the CCR4A.2 control bit.
Signal Name:RNEGIA/B
Signal Description:Receive Negative Data InputSignal Type:InputSampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSIA/B and
RNEGIA/B can be tied together for a NRZ interface. RNEGIA be internally connected to RNEGLO via theCCR4A.2 control bit.
Signal Name:RCLKIA/BSignal Description:Receive Clock InputSignal Type:Input
Signal used to clock data through the receive side framers. RCLKIA can be internally connected to RCLKLO viathe CCR4A.2 control bit.
User Port Pins
Signal Name:UOP0/1/2/3Signal Description:User Output PortSignal Type:Output
These output port pins can be set low or high via the CCR7B.0 to CCR7B.3 control bits. The pins are forced lowon power-up.
DS2196
Parallel Control Port Pins
Signal Name:INT*Signal Description:Interrupt
Signal Type:OutputFlags host controller during conditions and change of states as defined in the Status Registers. Active low, open
drain output.
Signal Name:MUXSignal Description:Bus Operation
Signal Type:InputSet low to select non-multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:D0 to D7 / AD0 to AD7Signal Description:Data Bus or Address/Data BusSignal Type:Input / Output
In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1),serves as a 8–bit multiplexed address / data bus.
Signal Name:A0 to A6Signal Description:Address Bus
Signal Type:InputIn non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1),
these pins are not used and should be tied low.
Signal Name:BTSSignal Description:Bus Type Select
Signal Type:InputStrap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the
RD*(DS*), ALE (AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis
().
Signal Name:RD* (DS*)
Signal Description:Read Input (Data Strobe)Signal Type:InputRD* is an active low signal. DS* polarity is determined by the MUX pin setting. Refer to section 21 for details.
Signal Name:CS*
Signal Description:Chip Select
Signal Type:InputMust be low to read or write to the device. CS* is an active low signal.
Signal Name:ALE(AS) / A7Signal Description:A7 or Address Latch Enable (Address Strobe)
Signal Type:InputIn non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX
= 1), serves to demultiplex the bus on a positive–going edge.
Signal Name:WR*( R/W*)Signal Description:Write Input (Read/Write)Signal Type:Input
WR* is an active low signal.
DS2196
Signal Name:JTCLK
Signal Description:JTAG IEEE 1149.1 Test Serial ClockSignal Type:InputThis signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this
pin should be pulled high.
Signal Name:JTDI
Signal Description:JTAG IEEE 1149.1 Test Serial Data InputSignal Type:InputTest instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this pin should be
pulled high. This pin has an internal pull-up.
Signal Name:JTDO
Signal Description:JTAG IEEE 1149.1 Test Serial Data OutputSignal Type:OutputTest instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this pin should be leftopen circuited.
Signal Name:JTRST*
Signal Description:JTAG IEEE 1149.1 Test ResetSignal Type:Input
This signal is used to synchronously reset the test access port controller. At power up, JTRST must be set low andthen high. This action will set the device into the boundary scan bypass mode allowing normal device operation.
If boundary scan is not used, this pin should be held low. This pin has an internal pull-up.
Signal Name:JTMSSignal Description:JTAG IEEE 1149.1 Test Mode Select
Signal Type:InputThis signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If not used, this pin should be pulled high. This signal has an internal pull-up.
Line Interface Pins
Signal Name:MCLKSignal Description:Master Clock InputSignal Type:Input
A 1.544 MHz (±50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for bothclock/data recovery and for jitter attenuation. This clock is also used to source AIS within the LIU.
Signal Name:RTIP & RRINGSignal Description:Receive Tip and RingSignal Type:Input
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 19for details.
Signal Name:TTIP & TRINGSignal Description:Transmit Tip and Ring
Signal Type:OutputAnalog line driver outputs. These pins connect via a 1:2 step–up transformer to the T1 line. See Section 19 for
details.
DS2196
Signal Type:OutputThis digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream.
The signal is based on what is provided at the TNEGLI input.
Signal Name:LNRZ
Signal Description:LIU NRZ DataSignal Type:OutputThis digital output will provide either a NRZ data stream or the positive half of a bipolar data stream. The signal is
based on what is provided at the TPOSLI input.
Signal Name:LCLK
Signal Description:LIU ClockSignal Type:Output
This digital output provides the 1.544 MHz transmit LIU clock. The signal is based on what is provided at the
TCLKLI input.
Signal Name:TNEGLISignal Description:Transmit Negative Data for the LIUSignal Type:Input
This digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse
via the jitter attenuator block to the transmit line driver block and the LFSYNC output pin. Data input to this pin issampled on the falling edge of TCLKLI. TNEGLI can be internally connected to TNEGOA/TFSYNCA via the
CCR4A.2 control bit.
Signal Name:TPOSLI
Signal Description:Transmit Positive Data for the LIU
Signal Type:InputThis digital input is used to pass either the positive half of a bipolar data stream or a NRZ data stream via the jitter
attenuator block to the transmit line driver block and the LNRZ output pin. Data input to this pin is sampled on thefalling edge of TCLKLI. TPOSLI can be internally connected to TPOSOA/TNRZA via the CCR4A.2 control bit.
Signal Name:TCLKLISignal Description:Transmit Clock for the LIUSignal Type:Input
This digital input is used to pass a 1.544 MHz clock via the jitter attenuator block to the transmit line driver blockand the LCLK output pin. TCLKLI can be internally connected to TCLKOA via the CCR4A.2 control bit.
Signal Name:WNRZSignal Description:Working NRZ Data
Signal Type:Input
This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuatorblock to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of
WCLK.
Signal Name:WCLKSignal Description:Working Clock
Signal Type:InputThis digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator
block to the RCLKLO output pin.
DS2196
Signal Name:PNRZ
Signal Description:Protect NRZ Data
Signal Type:InputThis digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator
block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge ofPCLK.
Signal Name:PCLK
Signal Description:Protect ClockSignal Type:Input
This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuatorblock to the RCLKLO output pin.
Signal Name:RCLSignal Description:Receive Carrier LossSignal Type:Output
Set high when the line interface (LIU) detects a carrier loss.
Signal Name:RPOSLO
Signal Description:Receive Positive Data Output from the LIUSignal Type:OutputUpdated on the rising edge of RCLKLO with either bipolar data out of the LIU or NRZ data from the WNRZ or
PNRZ inputs.
Signal Name:RNEGLO
Signal Description:Receive Negative Data Output from the LIUSignal Type:OutputUpdated on the rising edge of RCLKLO with either bipolar data out of the LIU or NRZ data from the WNRZ or
PNRZ inputs.
Signal Name:RCLKO
Signal Description:Receive Clock OutputSignal Type:Output
Either a buffered recovered clock from the T1 line or the clock provided at the WCLK or PCLK inputs.
Signal Name:WPS
Signal Description:Working or Protect SelectSignal Type:InputThis digital input can be used to select between the WNRZ/WCLK (working) or PNRZ/PCLK (protect) data
inputs. For this pin to be active the Data Source MUX must be properly configured via the CCR1A.2, CCR1A.3,and CCR1A.4 control bits.
DS2196
Supply Pins
Signal Name:DVDDSignal Description:Digital Positive Supply
Signal Type:Supply3.3 volts ±5%. Should be tied to the RVDD and TVDD pins.
Signal Name:RVDDSignal Description:Receive Analog Positive SupplySignal Type:Supply
3.3 volts ±5%. Should be tied to the DVDD and TVDD pins.
Signal Name:TVDD
Signal Description:Transmit Analog Positive SupplySignal Type:Supply3.3 volts ±5%. Should be tied to the RVDD and DVDD pins.
Signal Name:DVSS
Signal Description:Digital Signal Ground
Signal Type:SupplyShould be tied to the RVSS and TVSS pins.
Signal Name:RVSSSignal Description:Receive Analog Signal Ground
Signal Type:Supply
0.0 volts. Should be tied to the DVSS and TVSS pins.
Signal Name:TVSSSignal Description:Transmit Analog GroundSignal Type:Supply
0.0 volts. Should be tied to the DVSS and TVSS pins.
DS2196
4. REGISTER MAP
Table 4-1. Register Map Sorted By Address
DS2196
DS2196
DS2196
DS2196
DS2196
Note: Framer A and B Test and Reserved registers are used only by the factory; these registers must be cleared (set to all 0’s) on power-up
initialization to ensure proper operation.
DS2196
5. PARALLEL PORT
The DS2196 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an
external microcontroller or microprocessor. The DS2196 can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the AC Electrical Characteristics in Section 22 for more details.
6. CONTROL, ID, AND TEST REGISTERS
Each framer in the DS2196 is configured via a set of eleven control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the DS2196 has been initialized,
the control registers will only need to be accessed when there is a change in the system configuration.
There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and
TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven registers aredescribed in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of
this read–only register is fixed to a 0 indicating that a T1 device is present. The next 3 MSBs are used to
indicate which T1 device is present. The lower 4 bits of the IDR are used to display the die revision of
the chip.
Power-Up Sequence
The DS2196 does not automatically clear its register space on power–up. After the supplies are stable,
the register space should be configured for operation by writing to all of the internal registers. This
includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach.
1. Clear DS2196 register space by writing 00h to the addresses 00h through 0FFh.
2. Program required registers to achieve desired operating mode.
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
0IDR.7Chip ID Bit 3. MSB of DS2196 identification code. Set to 0.
0IDR.6Chip ID Bit 2. DS2196 identification code. Set to 0.1IDR.5Chip ID Bit 1. DS2196 identification code. Set to 1.
1IDR.4Chip ID Bit 0. LSB of DS2196 identification code. Set to 1.
ID3IDR.3Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
ID2IDR.1Chip Revision Bit 2.ID1IDR.2Chip Revision Bit 1.ID0IDR.0Chip Revision Bit 0. LSB of a decimal code that represents
the chip revision.
DS2196
The factory in testing the DS2196 uses the two Test Registers at addresses 09 and 7D hex. On power–up,
the Test Registers should be set to 00 hex in order for the DS2196 to operate properly.
RCR1A: RECEIVE CONTROL REGISTER 1 FRAMER A (Address = 2B Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LCVCRFRCR1A.7Line Code Violation Count Register Function Select.
0 = do not count excessive 0’s1 = count excessive 0’s
ARCRCR1A.6Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1RCR1A.5Out Of Frame Select 1.0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2RCR1A.4Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in errorSYNCCRCR1A.3Sync Criteria.In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCTRCR1A.2Sync Time.
0 = qualify 10 bits
1 = qualify 24 bitsSYNCERCR1A.1Sync Enable.0 = auto resync enabled
1 = auto resync disabled
RESYNCRCR1A.0Resync. When toggled from low to high, a resynchronizationof the receive side framer is initiated. Must be cleared and set
again for a subsequent resync.
DS2196
RCR1B: RECEIVE CONTROL REGISTER 1 FRAMER B (Address = CB Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LCVCRFRCR1B.7Line Code Violation Count Register Function Select.0 = do not count excessive 0’s
1 = count excessive 0’s
ARCRCR1B.6Auto Resync Criteria.
0 = Resync on OOF or RCL event1 = Resync on OOF only
OOF1RCR1B.5Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2RCR1B.4Out Of Frame Select 2.0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCCRCR1B.3Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCTRCR1B.2Sync Time.0 = qualify 10 bits
1 = qualify 24 bits
SYNCERCR1B.1Sync Enable.
0 = auto resync enabled
1 = auto resync disabledRESYNCRCR1B.0Resync. When toggled from low to high, a resynchronization
of the receive side framer is initiated. Must be cleared and set
again for a subsequent resync.
DS2196
RCR2A: RECEIVE CONTROL REGISTER 2 FRAMER A (Address = 2C Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RCSRCR2A.7Receive Code Select. See Section 11 for more details.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)RCR2A.6Not Assigned. Should be set to 0 when written to.RCR2A.5Not Assigned. Should be set to 0 when written to.–RCR2A.4Not Assigned. Should be set to 0 when written to.RCR2A.3Not Assigned. Should be set to 0 when written to.
RD4YMRCR2A.2Receive Side D4 Yellow Alarm Select.
0 = 0s in bit 2 of all channels
1 = a 1 in the S–bit position of frame 12FSBERCR2A.1PCVCR Fs–Bit Error Report Enable.0 = do not report bit errors in Fs–bit position; only Ft bit
position
1 = report bit errors in Fs–bit position as well as Ft bit position
MOSCRFRCR2A.0Multiframe Out of Sync Count Register Function Select.0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
DS2196
RCR2B: RECEIVE CONTROL REGISTER 2 FRAMER B (Address = CC Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RCSRCR2B.7Receive Code Select. See Section 11 for more details.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)RCR2B.6Not Assigned. Should be set to 0 when written to.RCR2B.5Not Assigned. Should be set to 0 when written to.–RCR2B.4Not Assigned. Should be set to 0 when written to.RCR2B.3Not Assigned. Should be set to 0 when written to.
RD4YMRCR2B.2Receive Side D4 Yellow Alarm Select.
0 = 0’s in bit 2 of all channels
1 = a 1 in the S–bit position of frame 12FSBERCR2B.1PCVCR Fs–Bit Error Report Enable.0 = do not report bit errors in Fs–bit position; only Ft bit
position
1 = report bit errors in Fs–bit position as well as Ft bit position
MOSCRFRCR2B.0Multiframe Out of Sync Count Register Function Select.0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
DS2196
TCR1A: TRANSMIT CONTROL REGISTER 1 FRAMER A (Address = 35 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LOTCMCTCR1A.7Loss Of Transmit Clock Mux Control. Determines whether
the transmit side of Formatter A should switch to MCLK if the
TCLK input should fail to transition (see Figure 1.1 for details).
0 = do not switch to MCLK if TCLKA stops
1 = switch to MCLK if TCLKA stopsTFPTTCR1A.6Transmit F–Bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSERA
TCPTTCR1A.5Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally1 = CRC6 bits sampled at TSERA during F–bit time
RBSETCR1A.4Robbed Bit Signaling Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels (the TTR registers can
be used to block insertion on a channel by channel basis)GB7STCR1A.3Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels
containing all 0’s are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of
how the TTR registers are programmedTFDLSTCR1A.2TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register
(legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC
controller or the TLINKA pinTBLTCR1A.1Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all 1’s code at TPOSOA and
TNEGOATYELTCR1A.0Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
NOTE:
For a description of how the bits in TCR1A affect the transmit side formatter, see Figure 21-7.
DS2196
TCR1B: TRANSMIT CONTROL REGISTER 1 FRAMER B (Address = D5 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LOTCMCTCR1B.7Loss Of Transmit Clock Mux Control. Determines whether
the transmit side of Formatter B should switch to MCLK if the
TCLK input should fail to transition (see Figure 1.1 for details).
0 = do not switch to MCLK if TCLKB stops
1 = switch to MCLK if TCLKB stopsTFPTTCR1B.6Transmit F–Bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSERB
TCPTTCR1B.5Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally1 = CRC6 bits sampled at TSERB during F–bit time
RBSETCR1B.4Robbed Bit Signaling Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels (the TTR registers can
be used to block insertion on a channel by channel basis)GB7STCR1B.3Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels
containing all 0’s are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of
how the TTR registers are programmedTFDLSTCR1B.2TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register
(legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC
controller or the TLINKB pinTBLTCR1B.1Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all 1’s code at TPOSOB and
TNEGOBTYELTCR1B.0Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
NOTE:
For a description of how the bits in TCR1B affect the transmit side formatter, see Figure 21-7.
DS2196
TCR2A: TRANSMIT CONTROL REGISTER 2 FRAMER A (Address = 36 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TEST1TCR2A.7Test Mode Bit 1 for Output Pins. See Table 6–1.
TEST0TCR2A.6Test Mode Bit 0 for Output Pins. See Table 6–1.
TAISMTCR2A.5Transmit AIS Mode.
0 = normal AIS
1 = AIS-CITSDWTCR2A.4TSYNCA Double–Wide. (note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSMTCR2A.3TSYNCA Mode Select.0 = frame mode (see the timing in Section 21)
1 = multiframe mode (see the timing in Section 21)
TSIOTCR2A.2TSYNCA I/O Select.
0 = TSYNCA is an input
1 = TSYNCA is an outputTD4YMTCR2A.1Transmit Side D4 Yellow Alarm Select.0 = 0’s in bit 2 of all channels
1 = a 1 in the S–bit position of frame 12
TB7ZSTCR2A.0Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs1 = Bit 7 force to a 1 in channels with all 0’s
DS2196
TCR2B: TRANSMIT CONTROL REGISTER 2 FRAMER B (Address = D6 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTCR2B.7Not Assigned. Should be set to 0 when written to.TCR2B.6Not Assigned. Should be set to 0 when written to.
TAISMTCR2A.5Transmit AIS Mode.
0 = normal AIS
1 = AIS-CITSDWTCR2B.4TSYNCB Double–Wide. (note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSMTCR2B.3TSYNCB Mode Select.0 = frame mode (see the timing in Section 21)
1 = multiframe mode (see the timing in Section 21)
TSIOTCR2B.2TSYNCB I/O Select.
0 = TSYNCB is an input
1 = TSYNCB is an outputTD4YMTCR2B.1Transmit Side D4 Yellow Alarm Select.0 = zeros in bit 2 of all channels
1 = a 1 in the S–bit position of frame 12
TB7ZSTCR2B.0Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs1 = Bit 7 force to a 1 in channels with all 0’s
DS2196
Table 6-1: OUTPUT PIN TEST MODES
CCR1A: COMMON CONTROL REGISTER 1 FRAMER A (Address = 37 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TRAIMCCR1A.7Transmit RAI Mode. Only used in ESF framing mode.
0 = normal RAI
1 = RAI-CI
ODFCCR1A.6Output Data Format.0 = bipolar data at TPOSOA and TNEGOA
1 = NRZ data at TPOSOA; TNEGOA = TSYNCA delayed by
10 TCLKAs
RSAOCCR1A.5Receive Signaling All 1’s.
0 = allow robbed signaling bits to appear at RSERA1 = force all robbed signaling bits at RSERA to 1
RDS2CCR1A.4Receive Data Source Bit 2 See Table 6–2.
RDS1CCR1A.3Receive Data Source Bit 1 See Table 6–2.
RDS0CCR1A.2Receive Data Source Bit 0 See Table 6–2.
PLBCCR1A.1Payload Loopback.0 = loopback disabled
1 = loopback enabled
FLBCCR1A.0Framer Loopback.
0 = loopback disabled
1 = loopback enabled
DS2196
Table 6-2: Receive Data Source Mux Modes
CCR1B: COMMON CONTROL REGISTER 1 FRAMER B (Address = D7 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TRAIMCCR1B.7Transmit RAI Mode. Only used in ESF framing mode.
0 = normal RAI
1 = RAI-CIODFCCR1B.6Output Data Format.0 = bipolar data at TPOSOB and TNEGOB
1 = TX NRZ data at TPOSOB; TNEGOB =TFSYNCB=
TSYNCB delayed by 10 TCLKBs
RSAOCCR1B.5Receive Signaling All 1’s.0 = allow robbed signaling bits to appear at RSERB
1 = force all robbed signaling bits at RSERB to 1CCR1B.4Not Assigned. Should be set to 0 when written to.
TDSS1CCR1B.3TPOS/TNEG Data Source Select 1. Used to select the data
source for the TPOSOB & TNEGOB pins when FramerLoopback is active. See table 6-3.
TDSS0CCR1B.2TPOS/TNEG Data Source Select 0. Used to select the data
source for the TPOSOB & TNEGOB pins when Framer
Loopback is active. See table 6-3.
PLBCCR1B.1Payload Loopback.0 = loopback disabled
1 = loopback enabled
FLBCCR1B.0Framer Loopback.
0 = loopback disabled
1 = loopback enabled
DS2196
Table 6-3: TPOSB/TNEGB Data Source Select
Payload Loopback A
Payload Loopback When CCR1A.1 is set to a 1, the Framer/Formatter A will be forced into PayloadLoopback (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can
be enabled also in D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of
payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS
framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the
DS2196. When PLB is enabled, the following will occur:
1. The TCLKOA signal will become synchronous with RCLKA instead of TCLKA.
2. Data will be transmitted from the TRING and TTIP pins synchronous with RCLKA instead of
TCLKA.
3. All of the receive side signals will continue to operate normally.4. The TCHCLKA and TCHBLKA signals are forced low.
5. TX serial data into Formatter A is ignored.
Payload Loopback B
When CCR1B.1 is set to a 1, the Framer/Formatter B will be forced into Payload Loopback (PLB).
Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in
D4 framing applications. In a PLB situation, the DS2196 will loop the 192 bits of payload data (withBPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS2196. When PLB is
enabled, the following will occur:
1. The TCLKOB signal will become synchronous with RCLKIB instead of TCLKB.
2. Data will be transmitted from the TPOSOB and TNEGOB pins synchronous with RCLKIB instead of
TCLKB.
3. All of the receive side signals will continue to operate normally.
4. The TCHCLKB and TCHBLKB signals are forced low.5. TX serial data into Formatter B is ignored.
DS2196
Framer Loopback A
When CCR1A.0 is set to a 1, the A Framer/Formatter will enter a Framer Loopback (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the
transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1’s code will be transmitted at TPOSOA and TNEGOA outputs2. Data at RPOSIA and RNEGIA will be ignored
3. All receive side signals will take on timing synchronous with TCLKOA instead of RCLKIA.
NOTE:
The signals RCLKA and TCLKA cannot be the same clock during this loopback because this will cause
an unstable condition.
Framer Loopback B
When CCR1B.0 is set to a 1, the B Framer/Formatter will enter a Framer Loopback (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS2196 will loop data from the
transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all 1’s code will be transmitted at TPOSOB and TNEGOB outputs2. Data at RPOSIB and RNEGIB will be ignored
3. All receive side signals will take on timing synchronous with TCLKOB instead of RCLKIB.
NOTE:
The signals RCLKB and TCLKB cannot be the same clock during this loopback because this will cause
an unstable condition.
DS2196
CCR2A: COMMON CONTROL REGISTER 2 FRAMER A (Address = 38 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TFMCCR2A.7Transmit Frame Mode Select.0 = D4 framing mode
1 = ESF framing mode
TB8ZSCCR2A.6Transmit B8ZS Enable.
0 = B8ZS disabled1 = B8ZS enabled
TSLC96CCR2A.5Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this
bit to a 1 in D4 framing applications. Must be set to 1 to source
the Fs pattern. See Section 18 for details.
0 = SLC–96/Fs–bit insertion disabled1 = SLC–96/Fs–bit insertion enabled
TZSECCR2A.4Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using
the internal HDLC/BOC controller instead of the legacy support
for the FDL. See Section 18 for details.
0 = zero stuffer disabled1 = zero stuffer enabled
RFMCCR2A.3Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZSCCR2A.2Receive B8ZS Enable.0 = B8ZS disabled
1 = B8ZS enabled
RSLC96CCR2A.1Receive SLC–96 Enable. Only set this bit to a 1 in D4/SLC–
96 framing applications. See Section 18 for details.
0 = SLC–96 disabled1 = SLC–96 enabled
RFDLCCR2A.0Receive FDL Zero Destuffer Enable. Set this bit to 0 if using
the internal HDLC/BOC controller instead of the legacy support
for the FDL. See Section 18 for details.0 = zero destuffer disabled
1 = zero destuffer enabled
DS2196
CCR2B: COMMON CONTROL REGISTER 2 FRAMER B (Address = D8 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TFMCCR2B.7Transmit Frame Mode Select.0 = D4 framing mode
1 = ESF framing mode
TB8ZSCCR2B.6Transmit B8ZS Enable.
0 = B8ZS disabled1 = B8ZS enabled
TSLC96CCR2B.5Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this
bit to a 1 in D4 framing applications. Must be set to 1 to source
the Fs pattern. See Section 18 for details.
0 = SLC–96/Fs–bit insertion disabled1 = SLC–96/Fs–bit insertion enabled
TZSECCR2B.4Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using
the internal HDLC/BOC controller instead of the legacy support
for the FDL. See Section 18 for details.
0 = zero stuffer disabled1 = zero stuffer enabled
RFMCCR2B.3Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZSCCR2B.2Receive B8ZS Enable.0 = B8ZS disabled
1 = B8ZS enabled
RSLC96CCR2B.1Receive SLC–96 Enable. Only set this bit to a 1 in D4/SLC–
96 framing applications. See Section 18 for details.
0 = SLC–96 disabled1 = SLC–96 enabled
RFDLCCR2B.0Receive FDL Zero Destuffer Enable. Set this bit to 0 if using
the internal HDLC/BOC controller instead of the legacy support
for the FDL. See Section 18 for details.0 = zero destuffer disabled
1 = zero destuffer enabled
DS2196
CCR3A: COMMON CONTROL REGISTER 3 FRAMER A (Address = 30 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LIDSTCCR3A.7Line Interface TX Digital Signal Tri-state. Tri-state control
for the LIU pins LFSYNC, LCLK and LNRZ.
0 = pins not tri-stated
1 = pins tri-stated
TCLKSRCCCR3A.6Transmit Clock Source Select. This function allows the userto internally select MCLK as the clock source for the transmit
side formatter.
0 = TCLK supplied by LOTC mux (see TCR1A.7)
1 = use MCLK for TCLK
RLOSFCCR3A.5Function of the RLOSA/LOTCA Output.0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMSCCR3A.4RMSYNCA Multiframe Skip Control. Useful in framing
format conversions from D4 to ESF.
0 = RMSYNCA will output a pulse at every multiframe1 = RMSYNCA will output a pulse at every other multiframe
FBCT2CCR3A.3F Bit Corruption Type 2. Setting this bit high enables the
corruption of one Ft (D4 framing mode) or FPS (ESF framing
mode) bit in every 128 Ft or FPS bits as long as the bit remains
set.ECUSCCR3A.2Error Counter Update Select. Selects the update rate of the
error counters and the period of the One Second Timer
(SR2A.5). See Sections 7 & 8 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)TLOOPCCR3A.1Transmit Loop Code Enable. See Section 12 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD registerFBCT1CCR3A.0F Bit Corruption Type 1. A low to high transition of this bit
causes the next three consecutive Ft (D4 framing mode) or FPS
(ESF framing mode) bits to be corrupted causing the remote
end to experience a loss of synchronization.
DS2196
CCR3B: COMMON CONTROL REGISTER 3 FRAMER B (Address = D0 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR3B.7Not Assigned. Should be set to 0 when written to.
TCLKSRCCCR3B.6Transmit Clock Source Select. This function allows the user
to internally select MCLK as the clock source for the transmit
side formatter.
0 = TCLK supplied by LOTC mux (see TCR1B.7)1 = use MCLK for TCLK
RLOSFCCR3B.5Function of the RLOSB/LOTCB Output.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMSCCR3B.4RMSYNC Multiframe Skip Control. Useful in framingformat conversions from D4 to ESF.
0 = RMSYNCB will output a pulse at every multiframe
1 = RMSYNCB will output a pulse at every other multiframe
FBCT2CCR3B.3F Bit Corruption Type 2. Setting this bit high enables the
corruption of one Ft (D4 framing mode) or FPS (ESF framingmode) bit in every 128 Ft or FPS bits as long as the bit remains
set.
ECUSCCR3B.2Error Counter Update Select. Selects the update rate of the
error counters and the period of the One Second Timer
(SR2B.5). See Sections 7 & 8 for details.0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOPCCR3B.1Transmit Loop Code Enable. See Section 12 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code asdefined in TCD register
FBCT1CCR3B.0F Bit Corruption Type 1. A low to high transition of this bit
causes the next three consecutive Ft (D4 framing mode) or FPS
(ESF framing mode) bits to be corrupted causing the remoteend to experience a loss of synchronization.
DS2196
CCR4A: COMMON CONTROL REGISTER 4 FRAMER A (Address = 11 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LCLKPOLCCR4A.7LCLK Polarity Select.0 = data updated on rising edge.
1 = data updated on falling edge.
PWCLKPOLCCR4A.6PCLK/WCLK Polarity Select.
0 = data sampled on falling edge.1 = data sampled on rising edge.
BERTMENCCR4A.5Transmit BERT Mux Enable.
0 = BERT mux disabled.
1 = BERT mux enabled.
LNRZAISCCR4A.4LNRZ AIS Enable.0 = LNRZ and LFSYNC operate normally.
1 = LNRZ =1, LFSYNC = 0.CCR4A.3Not Assigned. Must be set to 0 when written.
LFAMCCCR4A.2LIU to Framer A Mux Control.
0 = LIU connected on-chip to Framer/Formatter A.1 = LIU disconnected from Framer/Formatter A.
RTDLPMCCR4A.1RX/TX Data Link Pin Mode. Determines the function of the
RCHCLKA/RLCLKA, RCHBLKA/RLINKA,
TCHCLKA/TLCLKA and TCHBLKA/TLINKA pins.
0 = RCHCLKA, RCHBLKA, TCHCLKA, TCHBLKA.1 = RLCLKA, RLINKA, TLCLKA, TLINKA.
TIRFSCCR4A.0Transmit Idle Registers (TIR) Function Select. See Section
11 for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSERA(i.e., Per Channel Loopback function)
DS2196
CCR4B: COMMON CONTROL REGISTER 4 FRAMER B (Address = B1 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RCLKIPOLCCR4B.7RCLKIB Polarity Select.0 = no inversion.
1 = invert.
TCLKOPOLCCR4B.6TCLKOB Polarity Select.
0 = no inversion.1 = invert.
BERTMENCCR4B.5Transmit BERT Mux Enable.
0 = BERT mux disabled.
1 = BERT mux enabled.CCR4B.4Not Assigned. Must be set to 0 when written.–CCR4B.3Not Assigned. Must be set to 0 when written.
FAFBMCCCR4B.2Framer/Formatter A to Framer/Formatter B Mux Control.
0 = Framer/Formatter A connected on-chip to Framer/Formatter
1 = Framer/Formatter A disconnected from Framer/Formatter BRTDLPMCCR4B.1RX/TX Data Link Pin Mode. Determines the function of the
RCHCLKB/RLCLKB, RCHBLKB/RLINKB,
TCHCLKB/TLCLKB and TCHBLKB/TLINKB pins.
0 = RCHCLKB, RCHBLKB, TCHCLKB, TCHBLKB
1 = RLCLKB, RLINKB, TLCLKB, TLINKBTIRFSCCR4B.0Transmit Idle Registers (TIR) Function Select. See Section
11 for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSERB
(i.e., Per = Channel Loopback function)
DS2196
CCR5A: COMMON CONTROL REGISTER 5 FRAMER A (Address = 19 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TJCCCR5A.7Transmit Japanese CRC6 Enable.0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
LLBCCR5A.6Local Loopback.
0 = loopback disabled1 = loopback enabled
LIAISCCR5A.5Line Interface AIS Generation Enable. See Figure 1–1 for
details. AIS generation is based on MCLK.
0 = allow normal data from TPOSIA/TNEGIA to be transmitted
at TTIP and TRING1 = force unframed all 1’s to be transmitted at TTIP and TRING
TCM4CCR5A.4Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 10 for details.
TCM3CCR5A.3Transmit Channel Monitor Bit 3.TCM2CCR5A.2Transmit Channel Monitor Bit 2.TCM1CCR5A.1Transmit Channel Monitor Bit 1.
TCM0CCR5A.0Transmit Channel Monitor Bit 0. LSB of the channel
decode.
DS2196
CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TJCCCR5B.7Transmit Japanese CRC6 Enable.0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculationCCR5B.6Not Assigned. Must be set to 0 when written.CCR5B.5Not Assigned. Must be set to 0 when written.TCM4CCR5B.4Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 10 for details.
TCM3CCR5B.3Transmit Channel Monitor Bit 3.
TCM2CCR5B.2Transmit Channel Monitor Bit 2.TCM1CCR5B.1Transmit Channel Monitor Bit 1.TCM0CCR5B.0Transmit Channel Monitor Bit 0. LSB of the channel
decode.
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RJCCCR6A.7Receive Japanese CRC6 Enable.0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
EAMSCCR6A.6Error Accumulation Mode Select.
0 = CCR3A.2 determines accumulation time1 = CCR6A.5 determines accumulation time
MECUCCR6A.5Manual Error Counter Update. When enabled by CCR6A.6,
the changing of this bit from a 0 to a 1 allows the next clock
cycle to load the error counter registers with the latest counts
and reset the counters. The user must wait a minimum of 972ns (1.5 clock periods) before reading the error count registers to
allow for proper update.
RCM4CCR6A.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 10 for details.RCM3CCR6A.3Receive Channel Monitor Bit 3.RCM2CCR6A.2Receive Channel Monitor Bit 2.
RCM1CCR6A.1
Receive Channel Monitor Bit 1.
DS2196
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RJCCCR6B.7Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
EAMSCCR6B.6Error Accumulation Mode Select.0 = CCR3B.2 determines accumulation time
1 = CCR6B.5 determines accumulation time
MECUCCR6B.5Manual Error Counter Update. When enabled by CCR6B.6,
the changing of this bit from a 0 to a 1 allows the next clock
cycle to load the error counter registers with the latest countsand reset the counters. The user must wait a minimum of 972
ns (1.5 clock periods) before reading the error count registers to
allow for proper update.
RCM4CCR6B.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in theRDS0M register. See Section 10 for details.
RCM3CCR6B.3Receive Channel Monitor Bit 3.
RCM2CCR6B.2Receive Channel Monitor Bit 2.
RCM1CCR6B.1Receive Channel Monitor Bit 1.
RCM0CCR6B.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
DS2196
CCR7A: COMMON CONTROL REGISTER 7 FRAMER A (Address = 0A Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LIRSTCCR7A.7Line Interface reset. Setting this bit from a 0 to a 1 will
initiate an internal reset that affects the clock recovery state
machine and jitter attenuator. Normally this bit is only toggled
on power–up. Must be cleared and set again for a subsequent
reset.RLBCCR7A.6Remote Loopback.0 = loopback disabled
1 = loopback enabled
AIS13-24CCR7A.5Channels 13 – 24 AIS Enable
0 = do not transmit AIS in channels 13 – 241 = transmit AIS in channels 13 - 24
AIS1-12CCR7A.4Channels 1 – 12 AIS Enable
0 = do not transmit AIS in channels 1 – 12
1 = transmit AIS in channels 1 - 12
DISRCLCCR7A.3LIU Receive Carrier Loss (RCL) pin Disable.0 = Normal operation.
1 = Disable the LIU RCL pin. Pin will always output a “0”.
The LRCL status bit in RIR3A.3 continues to report correct
LRCL status.CCR7A.2Not Assigned. Should be set to 0 when written to.–CCR7A.1Not Assigned. Should be set to 0 when written to.
LBOS3CCR7A.0Line Build Out Select Bit 3. Sets the transmitter build out; see
the Table 19–1
DS2196
CCR7B: COMMON CONTROL REGISTER 7 FRAMER B (Address = AA Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR7B.7Not Assigned. Should be set to 0 when written to.
BELBCCR7B.6Back End Loopback.
0 = loopback disabled
1 = loopback enabled
AIS13-24CCR7B.5Channels 13 – 24 AIS Enable0 = do not transmit AIS in channels 13 – 24
1 = transmit AIS in channels 13 - 24
AIS1-12CCR7B.4Channels 1 – 12 AIS Enable
0 = do not transmit AIS in channels 1 – 12
1 = transmit AIS in channels 1 - 12UOP3CCR7B.3User Defined Output Pin 3.0 = logic 0 level at pin
1 = logic 1 level at pin
UOP2CCR7B.2User Defined Output Pin 2.
0 = logic 0 level at pin1 = logic 1 level at pin
UOP1CCR7B.1User Defined Output Pin 1.
0 = logic 0 level at pin
1 = logic 1 level at pin
UOP0CCR7B.0User Defined Output Pin 0.0 = logic 0 level at pin
1 = logic 1 level at pin
Remote Loopback
When CCR7A.6 is set to a 1, the 2196 will be forced into Remote Loopback (RLB). In this loopback,data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins.
Data will continue to pass through the receive side of Framer A as it would normally and the data from
the transmit side of Formatter A will be ignored. Please see Figure 1–1 for more details.
Back End Loopback
When CCR7B.6 is set to a 1, the 2196 will be forced into Back End Loopback (BELB). In this loopback,
data input via the RPOSIB and RNEGIB pins will be transmitted back to the TPOSOB and TNEGOBpins. Data will continue to pass through the receive side of Framer B as it would normally and the data
from the transmit side of Formatter B will be ignored. Please see Figure 1–1 for more details.
Power–Up Sequence
On power–up, after the supplies are stable, the DS2196 should be configured for operation by writing to
all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of theinternal registers cannot be predicted on power–up.
DS2196
7. STATUS AND INFORMATION REGISTERS
Found in each Framer/Formatter is a set of nine registers that contain information on the current real time
status of the DS2196, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1
to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller for the
FDL. BERT generator and receiver status is contained in the BERT Information Register (BIR). The
specific details on the registers pertaining to the BERT and FDL functions are covered in Section 15 and18 but they operate the same as the other status registers in the DS2196 and this operation is described
below.
When a particular event has occurred (or is occurring), the appropriate bit in 1 of these nine registers will
be set to a 1. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion.This means that if an event or an alarm occurs and a bit is set to a 1 in any of the registers, it will remain
set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again (or in the case of the RBL, RYEL, LRCL or FRCL, and RLOS alarms, the bit
will remain set if the alarm is still present). There are bits in the four FDL status registers that are not
latched and these bits are listed in Section 18.
The user will always precede a read of any of the nine registers with a write. The byte written to the
register will inform the DS2196 which bits the user wishes to read and have cleared. The user will write
a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit
positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location,the read register will be updated with the latest information. When a 0 is written to a bit position, the read
register will not be updated and the previous value will be held. A write to the status and information
registers will be immediately followed by a read of the same register. The read result should be logically
AND’ed with the mask byte that was just written and this value should be written back into the same
register to insure that bit does indeed clear. This second write step is necessary because the alarms andevents in the status registers occur asynchronously in respect to their access via the parallel port. This
write–read– write scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2196 with higher–order software languages.
The SR1, SR2, HSR and BIR registers have the unique ability to initiate a hardware interrupt via the INT
output pin. Each of the alarms and events in the SR1, SR2, HSR and BIR can be either masked or
unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2
(IMR2), HDLC Interrupt Mask Register (HIMR) and BERT Control Register (BC1) respectively. The
BC1 register is covered in Section 15. The HIMR register is covered in Section 18.
The interrupts caused by alarms in SR1 (namely RYEL, LRCL or RCL, RBL, and RLOS) act differently
than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, LSPARE, LOTC, RMF, TMF,
SEC, RFDL, TFDL, RMTCH, RAF, and LORC) and FIMR. The alarm caused interrupts will force the
INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to theset/clear criteria in Table 7–2). The INT pin will be allowed to return high (if no other interrupts are
present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still
present.
The event caused interrupts will force the INT pin low when the event occurs. The INT pin will beallowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
DS2196
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
–ISR.7Not Assigned. Could be any value when read.BIRQISR.6BERT INTERRUPT REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
FDLSBISR.5FRAMER B FDLS INTERRUPT REQUEST.
0 = No interrupt request pending.1 = Interrupt request pending.
SR2BISR.4FRAMER B SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
SR1BISR.3FRAMER B SR1 INTERRUPT REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
FDLSAISR.2FRAMER A FDLS INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.SR2AISR.1FRAMER A SR2 INTERRUPT REQUEST.0 = No interrupt request pending.
1 = Interrupt request pending.
SR1AISR.0FRAMER A SR1 INTERRUPT REQUEST.
0 = No interrupt request pending.1 = Interrupt request pending.
DS2196
RIR1A: RECEIVE INFORMATION REGISTER 1 FRAMER A (Address = 22
Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
COFARIR1A.7Change of Frame Alignment. Set when the last resync
resulted in a change of frame or multiframe alignment.
8ZDRIR1A.6Eight Zero Detect. Set when a string of at least eight
consecutive zeros (regardless of the length of the string) have
been received at RPOSIA and RNEGIA.16ZDRIR1A.5Sixteen Zero Detect. Set when a string of at least sixteen
consecutive zeros (regardless of the length of the string) have
been received at RPOSIA and RNEGIA.RIR1A.4Not Assigned. Could be any value when read.RIR1A.3Not Assigned. Could be any value when read.SEFERIR1A.2Severely Errored Framing Event. Set when 2 out of 6
framing bits (Ft or FPS) are received in error.
B8ZSRIR1A.1B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOSIA and RNEGIA independent of whether the
B8ZS mode is selected or not via CCR2.6. Useful forautomatically setting the line coding.
FBERIR1A.0Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing
bit is received in error.
DS2196
RIR1B: RECEIVE INFORMATION REGISTER 1 FRAMER B
(Address = C2 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
COFARIR1B.7Change of Frame Alignment. Set when the last resync
resulted in a change of frame or multiframe alignment.
8ZDRIR1B.6Eight Zero Detect. Set when a string of at least eight
consecutive zeros (regardless of the length of the string) have
been received at RPOSIB and RNEGIB.16ZDRIR1B.5Sixteen Zero Detect. Set when a string of at least sixteen
consecutive zeros (regardless of the length of the string) have
been received at RPOSIB and RNEGIB.RIR1B.4Not Assigned. Could be any value when read.RIR1B.3Not Assigned. Could be any value when read.SEFERIR1B.2Severely Errored Framing Event. Set when 2 out of 6
framing bits (Ft or FPS) are received in error.
B8ZSRIR1B.1B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOSIB and RNEGIB independent of whether the
B8ZS mode is selected or not via CCR2.6. Useful forautomatically setting the line coding.
FBERIR1B.0Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing
bit is received in error.
DS2196
RIR2A: RECEIVE INFORMATION REGISTER 2 FRAMER A (Address = 31
Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RLOSCRIR2A.7Receive Loss of Sync Clear. Set when the framer achieves
synchronization; will remain set until read.
LRCLCRIR2A.6Line Interface Receive Carrier Loss Clear. Set when the
carrier signal is restored; will remain set until read. See Table
7–2.FRCLCRIR2A.5Framer Receive Carrier Loss Clear. Set when the carrier
signal is restored; will remain set until read. See Table 7–2.RIR2A.4Not Assigned. Could be any value when read.RIR2A.3Not Assigned. Could be any value when read.
RBLCRIR2A.2Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) isno longer detected; will remain set until read. See Table 7–2.RIR2A.1Not Assigned. Could be any value when read.RIR2A.0Not Assigned. Could be any value when read.
RIR2B: RECEIVE INFORMATION REGISTER 2 FRAMER B
(Address = D1 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RLOSCRIR2B.7Receive Loss of Sync Clear. Set when the framer achievessynchronization; will remain set until read.RIR2B.6Not Assigned. Could be any value when read.
FRCLCRIR2B.5Framer Receive Carrier Loss Clear. Set when the carrier
signal is restored; will remain set until read. See Table 7–2.RIR2B.4Not Assigned. Could be any value when read.–RIR2B.3Not Assigned. Could be any value when read.
RBLCRIR2B.2Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is
no longer detected; will remain set until read. See Table 7–2.RIR2B.1
Not Assigned. Could be any value when read.RIR2B.0
Not Assigned. Could be any value when read.
DS2196
RIR3A: RECEIVE INFORMATION REGISTER 3 FRAMER A (Address = 10
Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RL1RIR3A.7Receive Level Bit 1. See Table 7–1.
RL0RIR3A.6Receive Level Bit 0. See Table 7–1.
JALTRIR3A.5Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.LORCRIR3A.4Loss of Receive Clock. Set when the RCLKIA pin has not
transitioned for at least 2 �s (3 �s � 1�s).
LRCLRIR3A.3Line Interface Receive Carrier Loss. Set when 192
consecutive zeros have been received at the RRING and RTIPpins; allowed to be cleared when 14 or more 1’s out of 112
possible bit positions are received.RIR3A.2Not Assigned. Could be any value when read.RIR3A.1Not Assigned. Could be any value when read.
RAIS-CIRIR3A.0Receive AIS-CI Detect. Set when the AIS-CI pattern isdetected. (see note below)
RIR3B: RECEIVE INFORMATION REGISTER 3 FRAMER B
(Address = B0 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRIR3B.7Not Assigned. Could be any value when read.RIR3B.6Not Assigned. Could be any value when read.RIR3B.5Not Assigned. Could be any value when read.LORCRIR3B.4Loss of Receive Clock. Set when the RCLKIB pin has not
transitioned for at least 2 �s(3�s � 1�s).RIR3B.3Not Assigned. Could be any value when read.RIR3B.2Not Assigned. Could be any value when read.RIR3B.1Not Assigned. Could be any value when read.RAIS-CIRIR3A.0Receive AIS-CI Detect. Set when the AIS-CI pattern is
detected. (see note below)
DS2196
Table 7-1: RECEIVE T1 LEVEL INDICATION
NOTE:
The RAIS-CI bit is qualified with the RBL status bit (SR1A.3 and SR1B.3). Hence the RAIS-CI status
bit will not be set unless the RBL status bit is set. If the RBL bit is set and the RAIS-CI bit has
transitioned from a 1 to a 0 (i.e., it has cleared), it is recommended that the software wait at lest 1.5
seconds and then read the RAIS-CI bit again to make sure that the alarm has indeed cleared.
SR1A: STATUS REGISTER 1 FRAMER A (Address = 20 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPSR1A.7Loop Up Code Detected. Set when the loop up code as
defined in the RUPCD register is being received. See Section
12 for details.LDNSR1A.6Loop Down Code Detected. Set when the loop down code as
defined in the RDNCD register is being received. See Section
12 for details.
LOTCSR1A.5Loss of Transmit Clock. Set when the TCLKA pin has not
transitioned for one channel time (or 5.2 �s). Will force theRLOSA/LOTCA pin high if enabled via CCR1A.6. Also will
force transmit side formatter to switch to MCLK if so enabled
via TCR1A.7.
LSPARESR1A.4Spare Code Detected. Set when the spare code as defined in
the RSPARE register is being received. See Section 12 fordetails.
RBLSR1A.3Receive Blue Alarm. Set when an unframed all 1’s code is
received at RPOSIA and RNEGIA.
RYELSR1A.2Receive Yellow Alarm. Set when a yellow alarm is received
at RPOSIA and RNEGIA.FRCLSR1A.1Framer Receive Carrier Loss. Set when a red alarm is
received at RPOSIA and RNEGIA.
RLOSSR1A.0Receive Loss of Sync. Set when the device is not
synchronized to the receive T1 stream.
DS2196
SR1B: STATUS REGISTER 1 FRAMER B (Address = C0 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPSR1B.7Loop Up Code Detected. Set when the loop up code as
defined in the RUPCD register is being received. See Section
12 for details.
LDNSR1B.6Loop Down Code Detected. Set when the loop down code as
defined in the RDNCD register is being received. See Section12 for details.
LOTCSR1B.5Loss of Transmit Clock. Set when the TCLKB pin has not
transitioned for one channel time (or 5.2 �s). Will force the
RLOSB/LOTCB pin high if enabled via CCR1B.6. Also willforce transmit side formatter to switch to MCLK if so enabled
via TCR1B.7.
LSPARESR1B.4Spare Code Detected. Set when the spare code as defined in
the RSPARE register is being received. See Section 12 for
details.RBLSR1B.3Receive Blue Alarm. Set when an unframed all 1’s code is
received at RPOSIB and RNEGIB.
RYELSR1B.2Receive Yellow Alarm. Set when a yellow alarm is received
at RPOSIB and RNEGIB.
FRCLSR1B.1Framer Receive Carrier Loss. Set when a red alarm isreceived at RPOSIB and RNEGIB.
RLOSSR1B.0Receive Loss of Sync. Set when the device is not
synchronized to the receive T1 stream.
DS2196
Table 7-2: ALARM CRITERIA
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1’ss signal. Blue alarm
detectors should be able to operate properly in the presence of a 10E–3 error rate and they should not
falsely trigger on a framed all 1’ss signal. The blue alarm criteria in the DS2196 have been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
2. ANSI specifications use a different nomenclature than the DS2196 does; the following terms are
equivalent:
RBL = AISLRCL = LOS
RLOS = LOF
RYEL = RAI
DS2196
SR2A: STATUS REGISTER 2 FRAMER A (Address = 21 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2A.7Receive Multiframe. Set on receive multiframe boundaries.
TMFSR2A.6Transmit Multiframe. Set on transmit multiframe boundaries.
SECSR2A.5One Second Timer. Set on increments of one second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds. Set on increments of 42 ms (333 frames) ifCCR3A.2 = 1.
RFDLSR2A.4Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
TFDLSR2A.3Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.RMTCHSR2A.2Receive FDL Match Occurrence. Set when the RFDL
matches either RMTCH1A or RMTCH2A.
RAFSR2A.1Receive FDL Abort. Set when eight consecutive 1’s’s are
received in the FDL.
–SR2A.0Not Assigned. Could be any value when read.
SR2B: STATUS REGISTER 2 FRAMER B (Address = C1 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFSR2B.7Receive Multiframe. Set on receive multiframe boundaries.
TMFSR2B.6Transmit Multiframe. Set on transmit multiframe boundaries.
SECSR2B.5One Second Timer. Set on increments of one second based onRCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds. Set on increments of 42 ms (333 frames) if
CCR3B.2 = 1.
RFDLSR2B.4Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).TFDLSR2B.3Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
RMTCHSR2B.2Receive FDL Match Occurrence. Set when the RFDL
matches either RMTCH1B or RMTCH2B.
RAFSR2B.1Receive FDL Abort. Set when eight consecutive 1’s’s arereceived in the FDL.
–SR2B.0
Not Assigned. Could be any value when read.
DS2196
IMR1A: INTERRUPT MASK REGISTER 1 FRAMER A (Address = 7F Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPIMR1A.7Loop Up Code Detected.0 = interrupt masked
1 = interrupt enabled
LDNIMR1A.6Loop Down Code Detected.
0 = interrupt masked1 = interrupt enabled
LOTCIMR1A.5Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
LSPAREIMR1A.4Spare Code Detected.0 = interrupt masked
1 = interrupt enabled
RBLIMR1A.3Receive Blue Alarm.
0 = interrupt masked
1 = interrupt enabledRYEIMR1A.2Receive Yellow Alarm.0 = interrupt masked
1 = interrupt enabled
FRCLIMR1A.1Framer Receive Carrier Loss.
0 = interrupt masked1 = interrupt enabled
RLOSIMR1A.0Receive Loss of Sync.
0 = interrupt masked
1 = interrupt enabled
DS2196
IMR1B: INTERRUPT MASK REGISTER 1 FRAMER B (Address = FF Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
LUPIMR1B.7Loop Up Code Detected.0 = interrupt masked
1 = interrupt enabled
LDNIMR1B.6Loop Down Code Detected.
0 = interrupt masked1 = interrupt enabled
LOTCIMR1B.5Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
LSPAREIMR1A.4Spare Code Detected.0 = interrupt masked
1 = interrupt enabled
RBLIMR1B.3Receive Blue Alarm.
0 = interrupt masked
1 = interrupt enabledRYEIMR1B.2Receive Yellow Alarm.0 = interrupt masked
1 = interrupt enabled
FRCLIMR1B.1Framer Receive Carrier Loss.
0 = interrupt masked1 = interrupt enabled
RLOSIMR1B.0Receive Loss of Sync.
0 = interrupt masked
1 = interrupt enabled
DS2196
IMR2A: INTERRUPT MASK REGISTER 2 FRAMER A (Address = 6F Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2A.7Receive Multiframe.0 = interrupt masked
1 = interrupt enabled
TMFIMR2A.6Transmit Multiframe.
0 = interrupt masked1 = interrupt enabled
SECIMR2A.5One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDLIMR2A.4Receive FDL Buffer Full.0 = interrupt masked
1 = interrupt enabled
TFDLIMR2A.3Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabledRMTCHIMR2A.2Receive FDL Match Occurrence.0 = interrupt masked
1 = interrupt enabled
RAFIMR2A.1Receive FDL Abort.
0 = interrupt masked1 = interrupt enabledIMR2A.0
Not Assigned. Should be set to 0 when written to.
DS2196
IMR2B: INTERRUPT MASK REGISTER 2 FRAMER B (Address = EF Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RMFIMR2B.7Receive Multiframe.0 = interrupt masked
1 = interrupt enabled
TMFIMR2B.6Transmit Multiframe.
0 = interrupt masked1 = interrupt enabled
SECIMR2B.5One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDLIMR2B.4Receive FDL Buffer Full.0 = interrupt masked
1 = interrupt enabled
TFDLIMR2B.3Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabledRMTCHIMR2B.2Receive FDL Match Occurrence.0 = interrupt masked
1 = interrupt enabled
RAFIMR2B.1Receive FDL Abort.
0 = interrupt masked1 = interrupt enabled
–IMR2B.0Not Assigned. Should be set to 0 when written to.
8. ERROR COUNT REGISTERS
There is a set of three counters per framer that record bipolar violations, excessive zeros, errors in theCRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters can be automatically updated on either one second
boundaries (CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2
(SR2.5) or manually (CCR6.6=1 and triggering with CCR6.5). When updated automatically, the user
can use the interrupt from the one-second timer to determine when to read these registers. The user has afull second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their
respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register
has the potential to over-flow but the bit error would have to exceed 10E-2 before this would occur).
DS2196
Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive zeros. See Table 8-1 for details of exactly what the LCVCRs count. If
the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This
counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1A: LINE CODE VIOLATION COUNT REGISTER 1 FRAMER A
(Address = 23 Hex)
LCVCR2A: LINE CODE VIOLATION COUNT REGISTER 2 FRAMER A
(Address = 24 Hex)
LCVCR1B: LINE CODE VIOLATION COUNT REGISTER 1 FRAMER B
(Address = C3 Hex)
LCVCR2B: LINE CODE VIOLATION COUNT REGISTER 2 FRAMER B
(Address = C4 Hex)
(MSB)(LSB)LCVCR1LCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
LCV15LCVCR1.7
MSB of the 16–bit code violation countLCV0LCVCR2.0
LSB of the 16–bit code violation count
DS2196
Table 8-1: LINE CODE VIOLATION COUNTING ARRANGEMENTS
Path Code Violation Count Register (PCVCR) When the receive side of a framer is set to operate in the
ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12–bit counter that will record
errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR willautomatically count errors in the Ft framing bit position. Via the RCR2.1 bit, a framer can be
programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during
receive loss of synchronization (RLOS=1) conditions. See Table 8-2 for a detailed description of exactly
what errors the PCVCR counts.
PCVCR1A: PATH VIOLATION COUNT REGISTER 1 FRAMER A (Address = 25 Hex)PCVCR2A: PATH VIOLATION COUNT REGISTER 2 FRAMER A (Address = 26 Hex)
PCVCR1B: PATH VIOLATION COUNT REGISTER 1 FRAMER B (Address = C5 Hex)
PCVCR2B: PATH VIOLATION COUNT REGISTER 2 FRAMER B (Address = C6 Hex)
(MSB)(LSB)
PCVCR1
PCVCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC/FB11PCVCR1.3MSB of the 12–Bit CRC6 Error or Frame Bit Error Count(note #2)
CRC/FB0PCVCR2.0LSB of the 12–Bit CRC6 Error or Frame Bit Error Count
(note #2)
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register
2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in
the framing bit position (in the D4 framing mode; CCR2.3=0).
DS2196
Table 8-2: PATH CODE VIOLATION COUNTING ARRANGEMENTS
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)
conditions. See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1A: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 FRAMER A
(Address = 25 Hex)
MOSCR2A: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 FRAMER A
(Address = 27 Hex)
MOSCR1B: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 FRAMER B
(Address = C5 Hex)
MOSCR2B: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 FRAMER B
(Address = C7 Hex)
(MSB)(LSB)MOSCR1
MOSCR2
SYMBOLPOSITIONNAME AND DESCRIPTION
MOS/FB11MOSCR1.7MSB of the 12–Bit Multiframes Out of Sync or F–Bit ErrorCount (note #2)
MOS/FB0MOSCR2.0LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error
Count (note #2)
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out ofsync (RCR2.0=1)
DS2196
9. SIGNALING OPERATION
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream andinserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
0, then the robbed signaling bits will appear at the RSER pin in their proper position as they are received.
If CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.
RS1A TO RS12A: RECEIVE SIGNALING REGISTERS FRAMER A
(Address = 60 to 6B Hex)
RS1B TO RS12B: RECEIVE SIGNALING REGISTERS FRAMER B
(Address = E0 to EB Hex)
(MSB)(LSB)RS1RS2RS3RS4RS5RS6RS7RS8RS9RS10RS11RS12
SYMBOLPOSITIONNAME AND DESCRIPTION
D(24)RS12.7Signaling Bit D in Channel 24
A(1)RS1.0
Signaling Bit A in Channel 1
DS2196
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two framing bits per channel (A and B). In the D4 framing
mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from theprevious multiframe. Hence, whether the framer is operated in either framing mode, the user needs only
to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on
multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status
Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are
frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recentsignaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also
available at the RSER pin.
TS1A TO TS12A: TRANSMIT SIGNALING REGISTERS FRAMER A
(Address = 70 to 7B Hex)
TS1B TO TS12B: TRANSMIT SIGNALING REGISTERS FRAMER B
(Address = F0 to FB Hex)TS1TS2TS3TS4TS5TS6TS7TS8TS9TS10TS11TS12
SYMBOLPOSITIONNAME AND DESCRIPTION
D(24)TS12.7Signaling Bit D in Channel 24
A(1)TS1.0Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF
framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe
boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoingsignaling shift register that is internal to the device. The user can utilize the Transmit Multiframe
Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing
mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4
framing mode, there are only two framing bits per channel (A and B). However in the D4 framing mode,
the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The framer
DS2196
10. DS0 MONITORING FUNCTION
Each framer in the DS2196 has the ability to monitor one DS0 64 kbps channel in the transmit direction
and one DS0 channel in the receive direction at the same time. In the transmit direction the user will
determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5A &
CCR5B registers. In the receive direction, the RCM0 to RCM4 bits in the CCR6A & CCR6B registers
need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in theTransmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits
will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should
be programmed with the decimal decode of the appropriate T1 channel. Channels 1 through 24 map to
register values 0 through 23. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15
in the receive direction needed to be monitored, then the following values would be programmed intoCCR5 and CCR6:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
CCR5A: COMMON CONTROL REGISTER 5 FRAMER A (Address = 19 Hex)
CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
[Repeated here from section 6 for convenience with only the TX monitor function present]
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TCM4CCR5.4Transmit Channel Monitor Bit 4. MSB of a channel decodethat determines which transmit channel data will appear in the
TDS0M register.
TCM3CCR5.3Transmit Channel Monitor Bit 3.
TCM2CCR5.2Transmit Channel Monitor Bit 2.
TCM1CCR5.1Transmit Channel Monitor Bit 1.TCM0CCR5.0Transmit Channel Monitor Bit 0. LSB of the channel
decode.
DS2196
TDS0MA: TRANSMIT DS0 MONITOR REGISTER FRAMER A
(Address = 1A Hex)
TDS0MB: TRANSMIT DS0 MONITOR REGISTER FRAMER B
(Address = BA Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTDS0M.7Transmit DS0 Channel Bit 1. MSB of the DS0 channel (firstbit to be transmitted).TDS0M.6Transmit DS0 Channel Bit 2.TDS0M.5Transmit DS0 Channel Bit 3.TDS0M.4Transmit DS0 Channel Bit 4.TDS0M.3Transmit DS0 Channel Bit 5.B6TDS0M.2Transmit DS0 Channel Bit 6.B7TDS0M.1Transmit DS0 Channel Bit 7.TDS0M.0Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex)
CCR6B: COMMON CONTROL REGISTER 6 FRAMER B (Address = BE Hex)
[Repeated here from section 6 for convenience with only the RX monitor function present]
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
RCM4CCR5.4Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive DS0 channel data will appear in
the RDS0M register.
RCM3CCR5.3Receive Channel Monitor Bit 3.RCM2CCR5.2Receive Channel Monitor Bit 2.RCM1CCR5.1Receive Channel Monitor Bit 1.
RCM0CCR5.0Receive Channel Monitor Bit 0. LSB of the channel decode
that determines which receive DS0 channel data will appear in
the RDS0M register.
DS2196
RDS0MA: RECEIVE DS0 MONITOR REGISTER FRAMER A
(Address = 1F Hex)
RDS0MB: RECEIVE DS0 MONITOR REGISTER FRAMER B
(Address = BF Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRDS0M.7Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).B2RDS0M.6Receive DS0 Channel Bit 2.B3RDS0M.5Receive DS0 Channel Bit 3.RDS0M.4Receive DS0 Channel Bit 4.RDS0M.3Receive DS0 Channel Bit 5.RDS0M.2Receive DS0 Channel Bit 6.B7RDS0M.1Receive DS0 Channel Bit 7.B8RDS0M.0Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2196 can replace data on a channel–by–channel basis in both the transmit and receive directions.The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive
direction is from the T1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
The Transmit Idle Registers (TIR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allowsthe same 8–bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0
control bit must be set to 0.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Codecontained in the Transmit Idle Definition Register (TIDR). Bit 7 stuffing will occur over the programmed
Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
Loopback (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine whichchannels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RSYNC to
TSYNC.
DS2196
TIR1A/TIR2A/TIR3A: TRANSMIT IDLE REGISTERS FRAMER A
(Address = 3C to 3E Hex)
TIR1B/TIR2B/TIR3B: TRANSMIT IDLE REGISTERS FRAMER B
(Address = DC to DE Hex)
[Also used for Per–Channel Loopback]
(MSB)(LSB)TIR1TIR2TIR3
SYMBOLSPOSITIONSNAME AND DESCRIPTION
CH1-24TIR1.0-3.7Transmit Idle Code Insertion Control Bits.0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 impliesthat channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel Loopback;
see Figure 1–1).
TIDRA: TRANSMIT IDLE DEFINITION REGISTER FRAMER A
(Address = 3F Hex)
TIDRB: TRANSMIT IDLE DEFINITION REGISTER FRAMER B
(Address = DF Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TIDR7TIDR.7MSB of the Idle Code (this bit is transmitted first)
TIDR0TIDR.0LSB of the Idle Code (this bit is transmitted last)
11.2 RECEIVE SIDE CODE GENERATION
The Receive Mark Registers (RMR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine
which code is used. The digital milliwatt code is an eight-byte repeating pattern that represents a 1 kHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel. If a bit isset to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to
0, no replacement occurs.
DS2196
RMR1A/RMR2A/RMR3A: RECEIVE MARK REGISTERS FRAMER A
(Address = 2D to 2F Hex)
RMR1B/RMR2B/RMR3B: RECEIVE MARK REGISTERS FRAMER B
(Address = CD to CF Hex)
(MSB)(LSB)RMR1RMR2RMR3
SYMBOLSPOSITIONSNAME AND DESCRIPTIONCH1-24RMR1.0-3.7Receive Channel Mark Control Bits
0 =do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with
either the idle code or the digital milliwatt code (depends on theRCR2.7 bit)
12. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION
Each framer in the DS2196 has the ability to generate and detect a repeating bit pattern that is from one tobits and 16 bits in length. To transmit a pattern, the user will load the pattern to be sent into the
Transmit Code Definition (TCD1&TCD2) registers and select the proper length of the pattern by setting
the TC0 and TC1 bits in the In–Band Code Control (IBCC) register. When generating a 1, 2, 4, 8 or16 bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code.
Generation of a 3, 5, 6 and 7 bit pattern only requires TCD1 to be filled. Once this is accomplished, the
pattern will be transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the
transmit formatter is programmed to not insert the F–bit position) the framer will overwrite the repeating
pattern once every 193 bits to allow the F–bit position to be sent. See Figure 21-7 for more details. Asan example, if the user wished to transmit the standard “loop up” code for Channel Service Units which is
a repeating pattern of ...10000100001... then 80h would be loaded into TCD1 and the length would set to
5 bits.
Each framer can detect three separate repeating patterns. Typically, two of the detectors are used for
“loop up” and “loop down” code detection. The user will program the codes to be detected in theReceive Up Code Definition (RUPCD1 & RUPCD2) registers and the Receive Down Code Definition
(RDNCD1 & RDNCD2) registers and the length of each pattern will be selected via the IBCC register.
There is a third detector (Spare) and it is defined and controlled via the RSCD1/RSCD2 and RSCC
registers. When detecting an 8 or 16 bit pattern both receive code definition registers must be filled withthe proper code. For 8 bit patterns both receive code definition registers will be filled with the same
value. Detection of a 1, 2, 3, 4, 5, 6 and 7 bit pattern only requires the first receive code definition
register to be filled. A third or spare detector is available for user definition. The framer will detect
repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E–2.
The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the leastsignificant byte of receive code definition register resets the integration period for that detector. The code
detector has a nominal integration period of 30 ms. Hence, after about 30 ms of receiving a valid code,
the proper status bit (LUP at SR1A/B.7 , LDN at SR1A/B.6 and LSPARE at SR1A/B.4 ) will be set to a
1. Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer
every 50 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present.
DS2196
IBCCB: IN–BAND CODE CONTROL REGISTER FRAMER B
(Address = B2 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TC1IBCC.7Transmit Code Length Definition Bit 1. See Table 12–1TC0IBCC.6Transmit Code Length Definition Bit 0. See Table 12–1
RUP2IBCC.5Receive Up Code Length Definition Bit 2. See Table 12–2
RUP1IBCC.4Receive Up Code Length Definition Bit 1. See Table 12–2
RUP0IBCC.3Receive Up Code Length Definition Bit 0. See Table 12–2
RDN2IBCC.2Receive Down Code Length Definition Bit 2. See Table12-2
RDN1IBCC.1Receive Down Code Length Definition Bit 1. See Table
RDN0IBCC.0Receive Down Code Length Definition Bit 0. See Table
Table 12-1: TRANSMIT CODE LENGTH
Table 12-2: RECEIVE CODE LENGTH
DS2196
TCD1A: TRANSMIT CODE DEFINITION REGISTER 1 FRAMER A
(Address = 13 Hex)
TCD1B: TRANSMIT CODE DEFINITION REGISTER 1 FRAMER B
(Address = B3 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTCD1.7Transmit Code Definition Bit 7. First bit of the repeating pattern.TCD1.6Transmit Code Definition Bit 6.C5TCD1.5Transmit Code Definition Bit 5.C4TCD1.4Transmit Code Definition Bit 4.TCD1.3Transmit Code Definition Bit 3.TCD1.2Transmit Code Definition Bit 2. A Don’t Care if a 5-bit length is selected.TCD1.1Transmit Code Definition Bit 1. A Don’t Care if a 5 or 6 bit length isselected.TCD1.0Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or 7 bit length is
selected.
DS2196
TCD2A: TRANSMIT CODE DEFINITION REGISTER 2 FRAMER A
(Address = 16 Hex)
TCD2B: TRANSMIT CODE DEFINITION REGISTER 2 FRAMER B
(Address = B6 Hex)
Least significant byte of 16 bit codes
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTCD2.7Transmit Code Definition Bit 7. A Don’t Care if a 5, 6 or
7 bit length is selected.C6TCD2.6Transmit Code Definition Bit 6. A Don’t Care if a 5, 6 or
7 bit length is selected.TCD2.5Transmit Code Definition Bit 5. A Don’t Care if a 5, 6 or
7 bit length is selected.TCD2.4Transmit Code Definition Bit 4. A Don’t Care if a 5, 6 or7 bit length is selected.TCD2.3Transmit Code Definition Bit 3. A Don’t Care if a 5, 6 or
7 bit length is selected.TCD2.2Transmit Code Definition Bit 2. A Don’t Care if a 5, 6 or
7 bit length is selected.C1TCD2.1Transmit Code Definition Bit 1. A Don’t Care if a 5, 6 or
7 bit length is selected.TCD2.0Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or
7 bit length is selected.
DS2196
RUPCD1A: RECEIVE UP CODE DEFINITION REGISTER 1 FRAMER A
(Address = 14 Hex)
RUPCD1B: RECEIVE UP CODE DEFINITION REGISTER 1 FRAMER B
(Address = B4 Hex)
NOTE:
Writing this register resets the detector’s integration period.
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONC7RUPCD1.7Receive Up Code Definition Bit 7. First bit of the repeating
pattern.RUPCD1.6Receive Up Code Definition Bit 6. A Don’t Care if a 1 bit
length is selected.RUPCD1.5Receive Up Code Definition Bit 5. A Don’t Care if a 1 or 2 bitlength is selected.RUPCD1.4Receive Up Code Definition Bit 4. A Don’t Care if a 1 to 3 bit
length is selected.RUPCD1.3Receive Up Code Definition Bit 3. A Don’t Care if a 1 to 4 bit
length is selected.C2RUPCD1.2Receive Up Code Definition Bit 2. A Don’t Care if a 1 to 5 bit
length is selected.RUPCD1.1Receive Up Code Definition Bit 1. A Don’t Care if a 1 to 6 bit
length is selected.RUPCD1.0Receive Up Code Definition Bit 0. A Don’t Care if a 1 to 7 bitlength is selected.
DS2196
RUPCD2A: RECEIVE UP CODE DEFINITION REGISTER 2 FRAMER A
(Address = 17 Hex)
RUPCD2B: RECEIVE UP CODE DEFINITION REGISTER 2 FRAMER B
(Address = B7 Hex)
(MSB)(LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRUPCD2.7Receive Up Code Definition Bit 7. A Don’t Care if a 1 to 7 bit
length is selected.C6RUPCD2.6Receive Up Code Definition Bit 6. A Don’t Care if a 1 to 7 bit
length is selected.RUPCD2.5Receive Up Code Definition Bit 5. A Don’t Care if a 1 to 7 bit
length is selected.RUPCD2.4Receive Up Code Definition Bit 4. A Don’t Care if a 1 to 7 bitlength is selected.RUPCD2.3Receive Up Code Definition Bit 3. A Don’t Care if a 1 to 7 bit
length is selected.RUPCD2.2Receive Up Code Definition Bit 2. A Don’t Care if a 1 to 7 bit
length is selected.C1RUPCD2.1Receive Up Code Definition Bit 1. A Don’t Care if a 1 to 7 bit
length is selected.RUPCD2.0Receive Up Code Definition Bit 0. A Don’t Care if a 1 to 7 bit
length is selected.
