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DS2196LN+
T1 Dual Framer LIU
GENERAL DESCRIPTION The DS2196 T1 dual framer LIU is designed for T1
transmission equipment. The DS2196 combines dual
optimized framers together with a LIU. This
combination allows the users to extract and insert
facility data-link (FDL) messages in the receive and
transmit paths, collect line performance data, and
perform basic channel conditioning and maintenance.
The DS2196 contains all of the necessary functions
for connection to T1 lines whether they are DS1 long
haul or DSX–1 short haul. The clock recovery
circuitry automatically adjusts to T1 lines from 0ft to
over 6000ft in length. The device can generate both
DSX–1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms.
The device contains a set of internal registers that the
user can access and use to control the unit’s operation
of the unit. Quick access through the parallel control
port allows a single controller to handle many T1
lines. The device fully meets all of the latest T1
specifications.
PACKAGE OUTLINE
FEATURES § Two full-featured framers and a short/long-haul
line interface unit (LIU) in one small package
§ Based on Dallas Semiconductor’s single-chip
transceiver (SCT) family
§ Two HDLC controllers with 64-byte buffers that
can be used for the FDL or DS0 channels
§ Supports NPRMs and SPRMs as per ANSI
T1.403-1998
§ Can be combined with a short/long-haul LIU or a
HDSL modem chipset to create a low-cost office
repeater/NIU/CSU, or a HDSL1/HDSL2 terminal
unit with enhanced monitoring and data link
control
§ Supports fractional T1
§ Can convert from D4 to ESF framing and ESF to
D4 framing
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Can generate and detect repeating in-band
patterns from 1 to 8 bits or 16 bits in length
§ Detects and generates RAI-CI and AIS-CI
§ Generates DS1 idle codes
§ On-chip programmable BERT generator and
detector
§ All key signals are routed to pins to support
numerous hardware configurations
§ Supports both NRZ and bipolar interfaces
§ Can create errors in the F-bit position and BERT
interface data paths
§ 8-bit parallel control port that can be used
directly on either multiplexed or nonmultiplexed
buses (Intel or Motorola)
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V supply with 5V tolerant inputs and outputs
§ 100-pin LQFP (14 mm x 14 mm) package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2196L 0ºC to +70ºC 100 LQFP
DS2196LN -40ºC to +85ºC 100 LQFP
DS2196
T1 Dual Framer LIUDS2196
DS2196
TABLE OF CONTENTSINTRODUCTION................................................................................................................................61.1 FEATURE HIGHLIGHTS..................................................................................................................6
1.2 TYPICAL APPLICATIONS.............................................................................................................10
1.3 FUNCTIONAL DESCRIPTION.......................................................................................................10
PIN DESCRIPTION..........................................................................................................................10PIN FUNCTION DESCRIPTION....................................................................................................13REGISTER MAP...............................................................................................................................21PARALLEL PORT............................................................................................................................27CONTROL, ID, AND TEST REGISTERS.....................................................................................27
7 STATUS AND INFORMATION REGISTERS............................................................................51
8 ERROR COUNT REGISTERS.......................................................................................................64SIGNALING OPERATION..............................................................................................................68
10 DS0 MONITORING FUNCTION..................................................................................................70
11 PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.....................................7211.1TRANSMIT SIDE CODE GENERATION..................................................................................72
11.2RECEIVE SIDE CODE GENERATION......................................................................................73
12 PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION.........................74
13 CLOCK BLOCKING REGISTERS..............................................................................................83
14 TRANSMIT TRANSPARENCY....................................................................................................85
15 BERT FUNCTION..........................................................................................................................8615.1BERT REGISTER DESCRIPTION..............................................................................................88
16 ERROR INSERTION FUNCTION...............................................................................................96
17 HDLC CONTROLLER..................................................................................................................9917.1HDLC FOR DS0S.........................................................................................................................100
18 FDL/FS EXTRACTION AND INSERTION..............................................................................10118.1HDLC AND BOC CONTROLLER FOR THE FDL..................................................................101
18.1.1General Overview.................................................................................................................101
18.1.2Status Register for the HDLC...............................................................................................103
18.1.3Basic Operation Details........................................................................................................103
18.1.4HDLC/BOC Register Description........................................................................................105
DS2196
18.2LEGACY FDL SUPPORT..........................................................................................................115
18.2.1Overview...............................................................................................................................115
18.2.2Receive Section.....................................................................................................................115
18.2.3Transmit Section...................................................................................................................116
18.3D4/SLC–96 OPERATION..........................................................................................................117
LINE INTERFACE FUNCTION................................................................................................11819.1RECEIVE CLOCK AND DATA RECOVERY.........................................................................118
19.2TRANSMIT WAVESHAPING AND LINE DRIVING.............................................................119
19.3 JITTER ATTENUATOR..........................................................................................................120
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT......................12420.1DESCRIPTION................................................................................................................................124
20.2TAP CONTROLLER STATE MACHINE............................................................................................125
20.3INSTRUCTION REGISTER AND INSTRUCTIONS................................................................................127
TIMING DIAGRAMS..................................................................................................................133OPERATING PARAMETERS...................................................................................................141100-PIN LQFP PACKAGE SPECIFICATIONS......................................................................157
DS2196
LIST OF FIGURES
Figure 1-1: T1 Dual Framer LIU..............................................................................................................9
Figure 15-1: BERT Mux Diagram..........................................................................................................87
Figure 19-1: External Analog Connections..........................................................................................121
Figure 19-2: Jitter Tolerance.................................................................................................................122
Figure 19-3: Transmit Waveform Template........................................................................................122
Figure 19-4: Jitter Attenuation..............................................................................................................123
Figure 20-1: Boundary Scan Architecture...........................................................................................124
Figure 20-2: TAP Controller State Machine........................................................................................127
Figure 21-1: Receive Side D4 Timing....................................................................................................133
Figure 21-2: Receive Side ESF Timing.................................................................................................134
Figure 21-3: Receive Side Boundary Timing.......................................................................................135
Figure 21-4: Transmit Side D4 Timing.................................................................................................136
Figure 21-5: Transmit Side ESF Timing..............................................................................................137
Figure 21-6: Transmit Side Boundary Timing....................................................................................138
Figure 21-7: Transmit Data Flow..........................................................................................................139
Figure 21-8: Receive Data Flow.............................................................................................................140
Figure 22-1: Intel Bus Read AC Timing (BTS=0 / MUX = 1)............................................................146
Figure 22-2: Intel Bus Write Timing (BTS=0 / MUX=1)....................................................................147
Figure 22-3: Motorola Bus AC Timing (BTS = 1 / MUX = 1)............................................................148
Figure 22-4: Intel Bus Read AC Timing (BTS=0 / MUX=0)..............................................................149
Figure 22-5: Intel Bus Write AC Timing (BTS=0 / MUX=0).............................................................150
Figure 22-6: Motorola Bus Read AC Timing (BTS=1 / MUX=0)......................................................151
Figure 22-7: Motorola Bus Write AC Timing (BTS=1 / MUX=0).....................................................152
Figure 22-8: Receive Side AC Timing...................................................................................................153
Figure 22-9: Receive Line Interface AC Timing..................................................................................154
Figure 22-10: Transmit Side AC Timing..............................................................................................155
Figure 22-11: Transmit Line Interface Side AC Timing.....................................................................156
DS2196
LIST OF TABLES
Table 2-1: Pin Description Sorted by Pin Number................................................................................10
Table 4-1: Register Map Sorted by Address..........................................................................................21
Table 6-1: Output Pin Test Modes..........................................................................................................36
Table 6-2: Receive Data Source Mux Modes.........................................................................................37
Table 6-3: TPOSB/TNEGB Data Source Select.....................................................................................38
Table 7-1: Receive T1 Level Indication..................................................................................................57
Table 7-2: Alarm Criteria........................................................................................................................59
Table 8-1: Line Code Violation Counting Arrangements.....................................................................66
Table 8-2: Path Code Violation Counting Arrangements.....................................................................67
Table 8-3: Multiframes Out Of Sync Counting Arrangements............................................................67
Table 12-1: Transmit Code Length.........................................................................................................75
Table 12-2: Receive Code Length ...........................................................................................................75
Table 15-1: Bert Pattern Select Options.................................................................................................89
Table 15-2: Repetitive Pattern Length Options.....................................................................................90
Table 15-3: Bert Rate Insertion Select....................................................................................................91
Table 16-1: Error Rate Options..............................................................................................................98
Table 16-2: Error Insertion examples.....................................................................................................99
Table 17-1: Transmit HDLC Configuration..........................................................................................99
Table 18-1: HDLC/BOC Controller Register List...............................................................................102
Table 19-1: Line Build Out Select In LICR.........................................................................................119
Table 19-2: Transformer Specifications...............................................................................................120
Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture............................128
Table 20-2: ID Code Structure..............................................................................................................128
Table 20-3: Device ID Codes..................................................................................................................129
Table 20-4: Boundary Scan Register Description................................................................................130
