DS2188S ,T1/CEPT Jitter AttenuatorDS2188T1/CEPT Jitter Attenuatorwww.dalsemi.com
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DS2188S-DS2188S+
T1/CEPT Jitter Attenuator
FEATURESAttenuates clock and data jitter present in T1
or CEPT linesMeets the jitter attenuation templatesoutlined in TR62411, TR-TSY-000170,
G.735, and G.742Only one external component required; either6.176 MHz (T1) or 8.192 MHz (CEPT)
crystalSelectable buffer size of 128 or 32 bitsJitter attenuation is easily disabledSingle +5V supply; low-power CMOS
technologyAvailable in 16-pin DIP and 16-pin SOIC(DS2188S)Companion to the DS2186 Transmit Line
and DS2187 Receive Line Interface
PIN ASSIGNMENT
ORDERING INFORMATIONDS218816 Pin dip (0ºC-F70ºC)
DS2188S16 Pin SOIC (0º-+70ºC)
DS2188N16 Pin dip (-40ºC-+85ºC)
DS2188SN16 Pin SOIC (-40ºC-+85-ºC)
DESCRIPTIONThe DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with anexternal 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181ACEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network
Interface Unit.
OVERVIEWThe RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequencyof the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.
If the incoming jitter has excursions greater than 120 UIpp, then the crystal is adjusted to track the short-
term frequency variations of the incoming signal so that there is no loss of data. This adjustment is
DS2188
DS2188
greater than 120 UIpp, the BL pin will transition high. When the incoming jitter returns to less than
120 UIpp, the BL pin will return low.
The jitter attenuator in the DS2188 can be disabled by tying the DJA pin high. When the jitter attenuatoris disabled, the FIFO is bypassed and jitter received at RCLK, RPOS and RNEG is passed through the
DS2188 to RRCLK, RRPOS, and RRNEG. In this situation, the BL pin has no significance and XTAL
OUT will not be coherent with RRCLK.
How to use the DS2188 with Dallas Semiconductor’s other T1 and CEPT line interface parts is illustratedin Figures 3 through 5. Figure 3 illustrates how to use the DS2188 in the receive path along with a
DS2187 Receive Line Interface. Figure 4 illustrates how to use the DS2188 in the transmit path with the
DS2186 Transmit Line Interface.
BUFFER DEPTH SELECTThe buffer size on the DS2188 can be configured to either 128 or 32 bits via the BDS pin. If BDS is tied
low, then the buffer depth will be 128 bits and hence can handle input jitter up to 120 UIpp without losingits full attenuation capabilities as is described above in the Over-view. If BDS is tied high, then the
buffer depth is shortened to 32 bits. In this configuration, the DS2188 can handle input jitter up to
28 UIpp without losing its full jitter attenuation capabilities. The user may wish to limit the buffer size to
32 bits in applications where through-put delay is critical or into existing applications that al-ready have
32 bits of buffer space.
RESETThe buffer on the DS2188 is automatically centered on power-up. The user can recenter the 128-bit (or
32-bit) buffer on demand via the RST pin. The RST pin on the DS2188 is negative-edge triggered. When
this pin transitions from high-to-low, the buffer is recentered. The RST pin can be held either high or low
during operation of the DS2188; only a negative going signal will initiate a recentering. In most cases, a
reset of the DS2188 will corrupt data that is currently passing through the buffer.
DS2188 TI JITTER ATTENUATION PERFORMANCE Figure 1
DS2188
DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure 2
DS2188 IN THE RECEIVE PATH Figure 3
DS2188 IN THE TRANSMIT PATH Figure 4
DS2188
PIN DESCRIPTION Table 1
CRYSTAL REQUIREMENTSThe DS2188 must have a crystal connected to the XTAL1 and XTAL2 pins. For T1 environments, the
frequency of this crystal should be 6.176 MHz. For CEPT environments, the frequency of this crystal
should be 8.192 MHz. Table 2 lists some suggested crystal manufacturers that are recommended for use
with the DS2188. Also, see DS2188 Application Note, “Operation at Speeds Greater than E1” foradditional information.
CRYSTAL MANUFACTURERS Table 2
DS2188
CRYSTAL SELECTION GUIDELINES FOR THE DS2188
DS2188
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.1V to +7.0V
Operating Temperature0° to 70°C
Storage Temperature-55°C to +125°C
Soldering TemperatureSee J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS Commercial (0°C to 70°C) Industrial (-40ºC to 85ºC)
NOTE:1. Does not apply to XTAL1.
CAPACITANCE (tA=25°C)
DC ELECTRICAL CHARACTERISTICSCommercial (0°C to 70°C; VDD = 5.0V ± 10%)
Industrial (-40ºC to 85ºC)
NOTES:1. RCLK = 1.544 MHz; VDD = 5.50; outputs open.
2. VSS < VIN < VDD: XTAL1 = XTAL2 = VDD.
3. Does not apply to XTAL1 or XTAL2.
