DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2187+ ,Receive Line Interfaceapplications utilize a 18.528 MHz clock divided by either11, 12, or 13 to match the phase of the in ..
DS2187S ,Receive Line Interfaceapplications. Special internal circuitry of the RTIP and RRINGinputs permits negative signal excurs ..
DS2187S ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2188 ,T1/CEPT Jitter AttenuatorFEATURES PIN ASSIGNMENT Attenuates clock and data jitter present in T1 DJA 1 16 VDDo ..
DS2188S ,T1/CEPT Jitter AttenuatorDS2188T1/CEPT Jitter Attenuatorwww.dalsemi.com
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2187
Receive Line Interface
FEATURESLine interface for T1 (1.544 MHz) and CEPT
(2.048 MHz) primary rate networksExtracts clock and data from twisted pair or
coaxMeets requirements of PUB 43801, TR
62411, and applicable CCITT G.823Precision on-chip PLL eliminates externalcrystal or LC tank - no tuning requiredDecodes AMI, B8ZS, and HDB3 coded
signalsDesigned for short loop applications such as
terminal equipment to DSX-1Reports alarm and error eventsCompatible with the DS2180A T1/ISDN
Primary Rate and DS2181A CEPT
Transceivers, as well as DS2141A T1 and
DS2143 E1 ControllersCompanion to the DS2186 T1/CEPT
Transmit Line Interface and DS2188
T1/CEPT Jitter AttenuatorSingle 5V supply; low-power CMOStechnology
PIN ASSIGNMENT
DESCRIPTIONThe DS2187 T1/CEPT Receive Line Interface chip interfaces user equipment to North American (T1
1.544 MHz) and European (CEPT 2.048 MHz) primary rate communication networks. The device
extracts clock and data from twisted pair or coax transmission media and eliminates expensive discrete
components and/or manual tuning required in existing T1 and CEPT line termination electronics.
Application areas include DACS, CSU, CPE, channel banks, and PABX-to-computer interfaces such as
DMI and CPI.
DS2187
Receive Line Interface
DS2187
DS2187 BLOCK DIAGRAM Figure 1
LINE INPUTInput signals are coupled to the DS2187 via a 1:2 center-tapped transformer as shown in Figure 2. For T1
applications, R1 and R2 must be 200 ohms in order to properly terminate the line at 100 ohms. R1 and R2are set at 150 or 240 ohms for CEPT applications. Special internal circuitry of the RTIP and RRING
inputs permits negative signal excursions below VSS, which will occur in the circuit in Figure 2.
PEAK DETECTOR AND SLICERSSignal pulses present at RTIP and RRING are sampled by an internal peak detect circuit. The clock and
data slicer threshold are set for 50% of the sampled peak voltage.
Peak input levels at RRIP and RRING must exceed 0.6 volts to establish minimum slicer thresholds.
Signals below this level will cause RCL to transition high after 192 bit times.
CLOCK EXTRACTIONThe DS2187 utilizes both frequency locked (FLL) and digital phase locked (DPLL) loops to recover data
and clock from the incoming AMI signal. T1 applications utilize a 18.528 MHz clock divided by either
11, 12, or 13 to match the phase of the incoming jittered line signal. This technique affords exceptional
jitter tracking which enables the DS2187 to meet the latest AT&T TR 62411 and ECSA jitterspecifications. A 24.576 MHz clock divided by 11, 12, or 13 provides jitter tracking in the CEPT mode.
The DPLL output is buffered and presented at RCLK. An on-chip, laser-trimmed, voltage-controlled
oscillator (VCO) provides the precision 18.528 MHz and 24.576 MHz frequency sources utilized in the
FLL. The FLL is a high-Q circuit which tracks the average frequency of the incoming signal, minimizing
the effect of the DPLL on output jitter.
During the acquisition time or if RCL goes high, the LOCK pin will go low to indicate a loss of
synchronization to the line signal. Once this pin goes high, the FLL has achieved frequency lock and
valid data is present at the RPOS and RNEG outputs.
DS2187
PIN DESCRIPTION Table 1
DS2187
SYSTEM LEVEL INTERCONNECT Figure 2
OUTPUT TIMING Figure 3
DS2187
0 CODE SUPPRESSIONThe device will decode incoming B8ZS (RCLKSEL=0) or HDB3 (RCLKSEL=1) code words and replace
them with an all-0 code when ZCSEN=1. When ZCSEN=0, code words will pass through the device
without being altered. This feature can be disabled when the DS2187 is used with transceiver devices
such as the DS2180A DS2181A, DS2141A, or DS2143.
ALARM DETECTIONThe extracted data is monitored for network alarm and error conditions. RCL is set when 192 consecutive0s occur; it is cleared on the next one occurrence. AIS is set when less than three 0s have appeared at
RPOS and RNEG during the last two periods of the RAISsignal; once set, AIS will remain high for the
next two periods of RAIS. AIS will return low when more than two 0s appear. BPV reports bipolar
violations as they occur at RPOS and RNEG; B8ZS code words will not be flagged by BPV when
ZCSEN=1.
BYPASSING AND
LAYOUT CONSIDERATIONSThe DS2187 contains both precision analog and high-speed digital circuitry on the same chip. The power
supplies of these circuits (AVDD, AVSS, DVDD and DVSS) should be connected to system analog and
digital supplies. If separate system supplies do not exist, the appropriate supply pins can be tied together.Tying the analog and digital supplies together on the DS2187 will not degrade its performance, provided
the power supply is sufficiently decoupled.
To assure optimum performance, the length of LCAP, RTIP and RRING printed circuit board traces
should be minimized and isolated from neighboring interconnect.
DS2187
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.1V to +7.0V
Operating Temperature0° to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
** Inputs other than RTIP and RRING
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C)
NOTES:1. All inputs except RTIP and RRING.
2. Outputs open.
3. 0.0V < VIN
4. All outputs.
