DS2186+ ,Transmit Line InterfacePIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 TAIS I Transmit Alarm Indication Signal. When ..
DS2186S ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DS2186S ,Transmit Line InterfaceBLOCK DIAGRAM Figure 1VSSLNEGLPOSTTIPLCLKINPUT ZERO CODELINEWAVESHAPPINGDATA SUPPRESSIONDRIVERSTNEG ..
DS2186S+ ,Transmit Line Interfaceapplications are supported. Appropriate CCITT recom-communications networks. The device is compatib ..
DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2187+ ,Receive Line Interfaceapplications utilize a 18.528 MHz clock divided by either11, 12, or 13 to match the phase of the in ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2186+-DS2186S-DS2186S+
Transmit Line Interface
DS2186Transmit Line Interface
DS2186
022798 1/11
FEATURESLine interface for T1 (1.544 MHz) and CEPT (2.048
MHz) primary rate networksOn–chip transmit LBO (line build out) and line drivers
eliminate external componentsProgrammable output pulse shape supports short–
and long–loop applicationsSupports bipolar and unipolar input data formatsTransparent B8ZS and HDB3 zero code suppression
modesCompatible with DS2180A T1 and DS2181A CEPT
Transceivers DS2141A T1 and DS2143 E1 Control-
lersCompanion to the DS2187 Receive Line Interface
and DS2188 T1/CEPT Jitter AttenuatorSingle 5V supply; low–power CMOS technology
PIN ASSIGNMENTVSSLF
20–PIN DIP (300 MIL)
TAIS
ZCSEN
TCLKSEL
LEN0
LEN1
LEN2
TTIP
TRING
LCLK
LPOS
LNEG
TNEG
MTIP
MRING
ZCSEN
20–PIN SOIC (300 Mil)
LCLK
LPOS
LNEG
TCLK
TPOS
TNEG
MTIP
MRING
TAIS
TCLKSEL
LEN0
LEN1
LEN2
VDD
TTIP
TRING
VSS
DESCRIPTIONThe DS2186 T1/CEPT Transmit Line Interface Chip in-
terfaces user equipment to North American (T1–1.544
MHz) and European (CEPT–2.048 MHz) primary rate
communications networks. The device is compatible
with all types of twisted pair and coax cable found in
such networks.
Key on–chip components include: programmable wave
shaping circuitry, line drivers, remote loopback, and
zero suppression logic. A line–coupling transformer is
the only external component required.
Short loop (DSX–1, 0 to 655 feet) and long loop (CSU; 0
dB, –7.5 dB and –15 dB) pulse templates found in T1
applications are supported. Appropriate CCITT recom-
mendations are met in the CEPT mode.
Application areas include DACS, CSU, CPE, channel
banks, and PABX–to–computer interfaces such as DMI
and CPI. The DS2186 supports ISDN–PRI (Primary
Rate Interface) specifications.
RECEIVE
PAIR
TRANSMIT
PAIR
DS2186
022798 2/11
DS2186 BLOCK DIAGRAM Figure 1TTIP
TRING
MTIP
MRING
VDD
VSS
LNEG
LPOS
LCLK
TNEG
TPOS
TCLK
TAIS
TCLKSEL
SYSTEM LEVEL INTERCONNECT Figure 2
DS2186
022798 3/11
PIN DESCRIPTION Table 1
INPUT DATA MODESInput data is sampled on the falling edge of TCLK or
LCLK and can be bipolar (dual rail) or unipolar (single
rail, NRZ). TPOS, TNEG and TCLK are the data and
clock inputs when LB=0, LPOS, LNEG and LCLK when
LB=1. TPOS and TNEG (LPOS and LNEG) must be tied
together in NRZ applications.
ZERO CODE SUPPRESSION MODESTransmitted data is treated transparently (no zero code
suppression) when ZCSEN=0. HDB3 code words re-
place any all–zero nibble when ZCSEN=1 and
TCLKSEL=1. B8ZS code words replace any incoming
all–zero byte when ZCSEN=1 and TCLKSEL=0.
ALARM INDICATION SIGNALWhen TAIS is set, an all ones code is continuously
transmitted at the TCLK rate (LB=0) or the LCLK rate
(LB=1).
WAVE SHAPINGThe device supports T1 short loop (DSX–1; 0 to 655
feet), T1 long loop (CSU; 0 dB, –7.5 dB and –15 dB) and
CEPT (CCITT G.703) pulse template requirements.
On–chip laser trimmed delay lines clocked by either
TCLK or LCLK control a precision digital–to–analog
converter to build the desired waveforms, which are
buffered differentially by the line drivers.
DS2186
022798 4/11
The shape of the “pre–emphasized” T1 waveform is
controlled by inputs LEN0, LEN1, and LEN2
(TCLKSEL=0). These control inputs allow the user to
select the appropriate output pulse shape to meet
DSX–1 or CSU templates over a wide variety of cable
types and lengths. Those cable types include ABAM,
PIC, and PULP.
The CEPT mode is enabled when TCLKSEL=1. Only
one output pulse shape is available in the CEPT mode;
inputs LEN0, LEN1 and LEN2 can be any state except
all zeros.
The line coupling transformer also contributes to the
pulse shape seen at the cross–connect point. Trans-
formers for both T1 and CEPT applications must be
1:1.35.
The wave shaping circuitry does not contribute signifi-
cantly to output jitter (less than 0.01 UIpp broadband).
Output jitter will be dominated by the jitter on TCLK or
LCLK. TCLK and LCLK need only be accurate in fre-
quency, not duty cycle.
LINE DRIVERSThe on–chip differential line drivers interface directly to
the output transformer. To optimize device perform-
ance, length of the TTIP and TRING traces should be
minimized and isolated from neighboring interconnect.
FAULT PROTECTIONThe line drivers are fault–protected and will withstand a
shorted transformer secondary (or primary) without
damage. Inputs MTIP and MRING are normally tied to
TTIP and TRING to provide fault monitoring capability.
Output LF will transition low if 192 TCLK cycles occur
without a one occurring at MTIP or MRING. LF will tri–
state on the next one occurrence or two TCLK periods
later, whichever is greater.
The threshold of MTIP and MRING varies with the line
type selected at LEN0, LEN1 and LEN2. This insures
detection of the lowest level zero to one transition (–15
dB buildout) as it occurs on TTIP and TRING.
NOTE:The LEN0, LEN1 and LEN2 inputs control T1 output waveshapes when TCLKSEL=0. The G.703 (CEPT) template
is selected when TCLKSEL=1 and LEN0, LEN1, and LEN2 are at any state except all zeros.
DS2186
022798 5/11
DSX–1 ISOLATED PULSE TEMPLATE Figure 3NANOSECONDS
NORMALIZED
ALITITUDE
NOTES:Template shown is measured at the cross–connect point.The corner points shown below are joined by straight lines to form the template.
MAXIMUM CURVEMINIMUM CURVE
(0, 0.05)(0, –0.05)
(250, 0.05)(350, –0.05)
(325, 0.80)(350, 0.5)
(325, 1.15)(400, 0.95)
(425, 1.15)(500, 0.95)
(500, 1.05)(600, 0.9)
(675, 1.05)(650, 0.5)
(725, –0.07)(650, –0.45)
(875, 0.05)(800, –0.45)
(1250, 0.05)(925, –0.2)
(1100, –0.05)
(1250, –0.05)
DS2186
022798 6/11
OUTPUT PULSE TEMPLATE AT 2.048 MHz Figure 4NORMALIZED
AMPLITUDE
NOTES:Unlike the DSX–1 template, which is specified at the cross–connect point, the CEPT (2.048 MHz) template is spe-
cified at the transmit line output.The template shown above is normalized. The actual pulse height is cable dependent and is specified in
Table 3.
MAXIMUM CURVEMINIMUM CURVE
(0, 0.1)(0, –0.1)
(109.5, 0.5)(134.5, –0.2)
(109.5, 1.2)(134.5, 0.5)
(244, 1.1)(147, 0.8)
(378.5, 1.2)(244, 0.9)
(378.5, 0.5)(341, 0.8)
(488, 0.1)(353.5, 0.5)
(353.5, –0.2)
(488, –0.1)
