DS2182 Fast Delivery |IC PHOENIX CO.,LIMITED

DS2182 ,T1 Line MonitorFEATURESchanges from the original DS2182:§ Performs framing and monitoring functions§ Ability to co ..
DS2186 ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DS2186+ ,Transmit Line InterfacePIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 TAIS I Transmit Alarm Indication Signal. When ..
DS2186S ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DS2186S ,Transmit Line InterfaceBLOCK DIAGRAM Figure 1VSSLNEGLPOSTTIPLCLKINPUT ZERO CODELINEWAVESHAPPINGDATA SUPPRESSIONDRIVERSTNEG ..
DS2186S+ ,Transmit Line Interfaceapplications are supported. Appropriate CCITT recom-communications networks. The device is compatib ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS2182
T1 Line Monitor
FEATURESPerforms framing and monitoring functions
Supports Superframe and Extended Super-frame formatsFour onboard error counters
– 16-bit bipolar violation
– 8-bit CRC
– 8-bit OOF– 8-bit frame bit errorIndication of the following
– yellow and blue alarms
– incoming B8ZS code words
– 8 and 16 zero strings– change of frame alignment
– loss of sync
– carrier lossSimple serial interface used for config-
uration, control and status monitoring§ Burst mode allows quick access to counters
for status updatesAutomatic counter reset featureSingle 5V supply; low-power CMOS tech-nologyAvailable in 28-pin DIP and 28-pin PLCCThe DS2182A is upward-compatible from
the original DS2182
The updated DS2182A includes the followingchanges from the original DS2182:Ability to count excessive zerosSeverely Errored Framing Event indicationUpdated AIS detectionUpdated RCL detection§ AIS and RCL alarm clear indications
PIN ASSIGNMENT
DESCRIPTION
The DS2182A T1 Line Monitor Chip is a monolithic CMOS device designed to monitor real-timeperformance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
DS2182A
DS2182A
DS2182A BLOCK DIAGRAM Figure 1
DS2182A
PIN DESCRIPTION Table 1
DS2182A
PIN DESCRIPTION Table 2
POWER AND TEST PIN DESCRIPTION Table 3
REGISTER SUMMARY Table 4
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/ microcontroller-compatible serial port. Eleven
on-board registers allow the user to update operational characteristics and monitor device status via a host
controller, minimizing hardware interfaces. The port on the DS2182A can be read from or written to at
any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, andRNEG. However, RCLK is needed in order to clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
DS2182A
register read or write. The following 4 bits identify the register address. The next 2 bits are reserved and
must be set to 0 for proper operation. The last bit of the address/ command word enables burst mode
when set; the burst mode causes all registers to be consecutively read or written to. Data is read and
written to the DS2182A LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge ofSCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into
the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLKcycles. The SDO pin is tri-stated during device write and can be tied to SDI in applications where the host
processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively written to or read by the host processor.
A burst read is used to poll all registers; RSR1 and RSR2 contents will be unaffected. This featureminimizes device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is
set and the address is 0000. A burst is terminated by a low-high transition on CS.
ACB: ADDRESS COMMAND BYTE Figure 2
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTIONACB.7
write is enabled.ACB.6Reserved, must be 0 for operation.ACB.5Reserved, must be 0 for operation.
ADD3ACB.4MSB of register address.
ADD0ACB.1LSB of register address.
R/WACB.0Read/Write Select.0 = write addressed register
1 = read addressed register
DS2182A
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI is sampled on rising edge of SCLK.
2. SDO is updated on falling edge of SCLK.
OPERATION OF THE COUNTERS
All four of the counters in the DS2182A can be preset by the user to establish an event count interrupt
threshold. The counters count up from the preset value until they reach saturation. At saturation, each
additional event occurrence sets the appropriate bit in RSR2 and generates an interrupt if enabled by
RIMR2.
The DS2182A contains an auto counter reset feature in the burst read mode. If RCR1.4 is set, then the
user can burst read the four counters (five registers), and all four counters will be automatically reset to 0
after the read takes place. Since the burst mode can be terminated at any time by taking CS high, the user
has the option of reading all of the registers or only the counters. If RCR1.4 is set, then any read of the
registers, burst mode or not, will clear the count in all four counters. If the user wishes to read the port
and not clear the counters, then RCR1.4 must be cleared first.
The counter registers can be read or written to at any time with the serial port, which operates totally
asynchronously with the monitoring of the T1 line. Reading a register will not affect the count as long as
RCR1.4 is cleared. The dual buffer architecture of the DS2182A insures that no error events will be
missed while the serial port is being accessed for reads.
BVCR1: BIPOLAR VIOLATION COUNT REGISTER 1;
BVCR2: BIPOLAR VIOLATION COUNTER REGISTER 2 Figure 4
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
BV7BVCR.7MSB of bipolar violation count
BV0BVCR.0LSB of bipolar violation count
Bipolar Violation Count Register 1 (BVCR1) is the most significant word and BVCR2 is the least
DS2182A
occurrences of 8 consecutive zeros when B8ZS is enabled or 16 consecutive zeros when B8Z5 is
disabled. This counter increments at all times and is not disabled by a loss of sync condition (RLOS = 1).
The counter saturates at 65,535 and generates an interrupt for each occurrence after saturation if RIMR2.0
is set.
NOTE:
1. In order to properly preset the Bipolar Violation Count Register, BVCR2 must be written to before
BVCR1 is written to.
CRCCR: CRC COUNT REGISTER 2 Figure 5
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
CRC7CRCCR.7MSB of CRC6 word error count
CRC0CRCCR.0LSB of CRC6 word error count
The CRC Count Register (CRCCR) is an 8-bit presettable counter that records word errors in the Cyclic
Redundancy Check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each
occurrence after saturation if RIMR2.1 is set. The count in this register is only valid in the 193E framing
mode (RCR2.4 = 1) and is reset and disabled in the 193S framing mode (RCR2.4 = 0). The count is
disabled during a loss of sync condition (RLOS = 1).
OOFCR: OOF COUNT REGISTER Figure 6
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
OOF7OOFCR.7MSB of OOF event count
OFF0OOFCR.0LSB of OOF of event count
The OOF Count Register (OOFCR) is an 8-bit presettable counter that records Out Of Frame (OOF)
events. OOF events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 andgenerates an interrupt for each occurrence after saturation if RIMR2.2 is set. The count is disabled during
a loss of sync condition (RLOS = 1).
DS2182A
FECR: FRAME ERROR COUNT REGISTER Figure 7
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
FE7FECR.7MSB of frame error count
FFE0FECR.0LSB of frame error count
The Frame Error Count Register (FECR) is an 8-bit pre-settable counter that records individual frame bit
errors. In the 193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern(001011). In the 193S mode (RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS
(001110) framing patterns if RCR1.3 is set. If RCR1.3 is cleared, then the FECR only records bit errors in
the FT pattern. This 8-bit counter saturates at 255 and generates an interrupt for each occurrence after
saturation if RIMR2.3 is set. The count is disabled during a loss of sync condition (RLOS = 1).
RSR1: RECEIVE STATUS REGISTER 1 Figure 8
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
8ZDRSR1.78 Zero Detect. Set when a string of eight consecutive 0s has
been received at RPOS and RNEG.
16ZDRSR1.616 Zero Detect. Set when a string of 16 consecutive 0s has
been received at RPOS and RNEG.
RCLRSR1.5Receive Carrier Loss. Set when a string of 192 consecutive 0s has
been received at RPOS and RNEG. Cleared when 14 or more ones
out of 112 possible bit positions are received.
RYELRSR1.4format of yellow alarm is determined by RCR2.3 and RCR2.4.
RLOSRSR1.3Receive Loss of Sync. Set when resync is in progress.
B8ZSDRSR1.2
received at RPOS and RNEG independent of whether the B8ZS
mode is enabled or not (RCR2.2).
RBLRSR1.1zeros are received. Cleared when over a 3 ms window, 6 or more
zeros are received.
COFARSR1.0
a change of frame or multiframe alignment.
DS2182A
RECEIVE STATUS REGISTERS
The receive status registers (RSR1 and RSR2) can be used in either a polled or an interrupt configuration.
In a polled configuration, the user reads the RSR at regular intervals to check for alarms. In an interrupt
configuration, the user monitors the INT pin. When the INT pin goes low, an alarm condition has
occurred and has been reported in one of the RSRs. The processor can then read the RSRs to find which
bits have been set. All of the bits in the RSRs operate in a latched fashion. That is, once set, they remain
set until read. The bits in the RSR are cleared when read unless the read was performed in the burst modeor the alarm condition still exists.
YELLOW ALARM
193S BIT 2. If RCR2.4 = 0 and RCR2.3 = 0, then the DS2182A examines bit 2 of all incoming channels
for the presence of a yellow alarm. If bit 2 is set to 0 in 256 consecutive channels, then the reception of a
yellow alarm is declared. The alarm is considered cleared when the first channel with bit 2 set to a 1 is
received.
193S S-BIT. If RCR2.4 = 0 and RCR2.3 = 1, then the DS2182A examines the S-bit position of frame 12
for the presence of a yellow alarm. The DS2182A declares the presence of a yellow alarm on the first
occurrence of the S-bit in frame 12 being set to 1. The alarm is considered cleared when this S-bit returns
to 0.
193E FDL. If RCR2.4 = 1, then the DS2182A examines the FDL for a repeating 00FF pattern. If this
pattern is received in the FDL 16 consecutive times without error, then a yellow alarm is declared. The
alarm is considered cleared as soon as any pattern other than 00FF is received.
DS2182A
RIMR1: RECEIVE INTERRUPT MASK REGISTER 1 Figure 9
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
8ZDRIMR1.78 Zero Detect Mask.
1 = interrupt enabled.
0 = interrupt masked.
16ZDRIMR1.616 Zero Detect Mask.
1 = interrupt enabled.0 = interrupt masked.
RCLRIMR1.5Receive Carrier Loss Mask.1 = interrupt enabled.
0 = interrupt masked.
RYELRIMR1.4Receive Yellow Alarm Mask.
1 = interrupt enabled.
0 = interrupt masked.
RLOSRIMR1.3Receive Loss of Sync Mask.1 = interrupt enabled.
0 = interrupt masked.
B8ZSDRIMR1.2B8ZS Code Word Detect Mask.
1 = interrupt enabled.
0 = interrupt masked.
RBLRIMR1.1Receive Blue Alarm Mask.
1 = interrupt enabled.0 = interrupt masked.
COFARIMR1.0Change of Frame Alignment Mask.1 = interrupt enabled.
0 = interrupt masked.
DS2182A
RSR2: RECEIVE STATUS REGISTER 2 Figure 10
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
SEFERSR2.7
bits (Ft or FPS) are received in error.
RCLCRSR2.6restored; will remain set until read.
RBLCRSR2.5
longer detected; will remain set until read.
FERRRSR2.4
occur.
FECSRSR2.3Frame Error Count Saturation. Set on the next frame error event
after the 8-bit Frame Error Count Register (FECR) saturates at 255.
OOFCSRSR2.2
after the 8-bit OOF Count Register (OOFCR) saturates at 255.
CRCCSRSR2.1
8-bit CRC Count Register (CRCCR) saturates at 255.
BPVCSRSR2.0
event after the 16-bit Bipolar Violation Count Register (BVCR)
saturates at 65,535.
RIMR2: RECEIVE INTERRUPT MASK REGISTER 2 Figure 11
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
SEFERIMR2.7Severely Errored Framing Event Mask.0 = interrupt masked
1 = interrupt enabled
RCLCRIMR2.6Receive Carrier Loss Clear Mask.
0 = interrupt masked1 = interrupt enabled
RBLCRIMR2.5Receive Blue Alarm Clear Mask.0 = interrupt masked
1 = interrupt enabled
DS2182A
SYMBOLPOSITIONNAME AND DESCRIPTION
FERRRIMR2.4Frame Bit Error Mask.1 = interrupt enabled
0 = interrupt masked
FECSRIMR2.3Frame Error Count Saturation Mask.
1 = interrupt enabled
0 = interrupt masked
OOFCSRIMR2.2Out Of Frame Count Saturation Mask.
1 = interrupt enabled0 = interrupt masked
CRCCSRIMR2.1CRC Count Saturation Mask.
1 = interrupt enabled
0 = interrupt masked
BPVCSRIMR2.0Bipolar Violation Count Saturation Mask.
1 = interrupt enabled0 = interrupt masked
RCR1: RECEIVE CONTROL REGISTER 1 Figure 12
MSB LSB
SYMBOLPOSITIONNAME AND DESCRIPTION
ARCRCR1.7Auto Resync Criteria.
1 = resync on OOF event only0 = resync on OOF event or Receive Carrier Loss (RCL)
OOF1RCR1.6Out Of Frame 1. OOF event description. Valid when RCR1.5 is
cleared
1 = 2 out of 5 frame bits (FT or FPS) in error
0 = 2 out of 4 frame bits (FT or FPS) in error
OOF2RCR1.5Out Of Frame 2. OOF event description.
1 = 2 out of 6 frame bits (FT or FPS) in error0 = follow OOF event described in RCR1.6
ACRRCR1.4Auto Counter Reset. When set, all four of the counters will be reset
to 0 when read.
DS2182A
SYMBOLPOSITIONNAME AND DESCRIPTION
SYNCCRCR1.3
receive synchronizer; differs for each frame mode.
193S Framing (RCR2.4 = 0)
0 = synchronize to frame boundaries using FT pattern, then search
for multiframe by using FS.1 = cross couple FT and FS patterns in sync algorithm.
193E Framing (RCR2.4 = 1)
0 = normal sync (utilizes FPS only).
1 = validate new alignment with CRC before declaring sync.
SYNCTRCR1.2Sync Time.
1 = validate 24 consecutive F-bits before declaring sync.0 = validate 10 consecutive F-bits before declaring sync.
SYNCERCR1.1if the conditions described in RCR1.7 are met. If set, no auto
resync occurs.
RESYNCRCR1.0Resync. When toggled low to high, the DS2182A initiates a resync
immediately.
The bit must be cleared and set again for subsequent resyncs.
SYNCHRONIZER
The heart of the monitor is the receive synchronizer. This circuit serves two purposes: 1) monitors the
incoming data stream for loss of frame or multiframe alignment, and 2) searches for new frame alignment
pattern when sync loss is detected. When sync loss is detected, the synchronizer begins an off-line searchfor the new alignment; all output timing signals remain at the old alignment with the exception of
RSIGFR, which is forced low during resync. When one and only one candidate is qualified, the output
timing moves to the new alignment at the beginning of the next multiframe. One frame later, RLOS will
transition low, indicating valid sync and the resumption of the normal sync monitoring mode. Several bits
in the RCR1 allow tailoring of the resync algorithm by the user. These bits are described below.
SYNC CRITERIA (RCR1.3)
193E. Bit RCR1.3 determines which sync algorithm is utilized when resync is in progress (RLOS = 1).In 193E framing, when RCR1.3 = 0, the synchronizer will lock only to the FPS pattern and will move to
the new frame and multiframe alignment after the framing candidate is qualified. RLOS will go low one
frame after the move to the new alignment. When RCR1.3 = 1, the new alignment is further tested by a
CRC6 code match. RLOS will transition low after a CRC6 match occurs. If no CRC6 match occurs inthree attempts (three multiframes), the algorithm resets and a new search for the FPS pattern begins. It
takes 9 ms for the synchronizer to check the first CRC6 code after the new FPS alignment has been
loaded. Each additional CRC6 test takes 3 ms. Regardless of the state of RCR1.3, if more than one
candidate exists after 24 ms, the synchronizer begins eliminating emulators by testing their CRC6 codes
in order to find the true framing candidate.
193S. In 193S framing, when RCR1.3 = 1, the synchronizer cross-checks the FT pattern with the FS
pattern to help eliminate false framing candidates such as digital milliwatts. The FS patterns are

Partno	Mfg	Dc	Qty	Available	Descript
DS2182	DALLAS	N/a	39	avai	T1 Line Monitor