DS2181A Fast Delivery |IC PHOENIX CO.,LIMITED

DS2181A ,CEPT Primary Rate TransceiverFEATURES PIN ASSIGNMENT Single chip primary rate transceiver meets TMSYNC 1 40 VDDCCITT stand ..
DS2181A ,CEPT Primary Rate Transceiverfeatures such as error logging, per-channel code manipulation, and alteration ofthe receive synchro ..
DS2181A+ ,CEPT Primary Rate TransceiverBLOCK DIAGRAM Figure 1 2 of 32DS2181ATRANSMIT
DS2181AQ ,CEPT Primary Rate Transceiverfeatures such as error logging, per-channel code manipulation, and alteration ofthe receive synchro ..
DS2182 ,T1 Line MonitorFEATURESchanges from the original DS2182:§ Performs framing and monitoring functions§ Ability to co ..
DS2186 ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS2181A
CEPT Primary Rate Transceiver
FEATURESSingle chip primary rate transceiver meets
CCITT standards G.704, G.706 and G.732Supports new CRC4-based framing
standards and CAS and CCS signaling
standardsSimple serial interface used for deviceconfiguration and control in processor modeHardware mode requires no host processor;
intended for stand-alone applicationsComprehensive, on-chip alarm generation,
alarm detection, and error logging logicShares footprint with DS2180A T1
TransceiverComparison to DS2175 T1/CEPT Elastic
Store, DS2186 Transmit Line Interface,
DS2187 Receive Line Interface, and DS2188Jitter Attenuator5V supply; low-power CMOS technology
PIN ASSIGNMENT
DS2181A
TMO
TXD
TSTS
TSD
TIND
TAF
TPOS
INT
RPOS
RST
TEST
RCSYNC
RSTS
RSD
RMSYNC
RFSYNC
SDO
SPS
VSS
DS2181A
DESCRIPTION
The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red
Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns andCRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when
enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4
multiframe alignments. Once synchronized, the device extracts channel, signaling, and alarm data.
A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode,a host processor controls features such as error logging, per-channel code manipulation, and alteration of
the receive synchronizer algorithm.
The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing
systems. This mode requires no host processor and disables special features available in the processormode.
DS2180A BLOCK DIAGRAM Figure 1
DS2181A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
SYCHRONIZER STATUS PIN (44-PIN PLCC ONLY) Table 2A
DS2181A
NOTES:
1. These output status pins are only available on the DS2181AQ.
2. If the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 2B
DS2181A
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
DS2181A
REGISTER SUMMARY Table 5
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations must be programmed to 0.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port.Fourteen on-chip registers allow the user to update operational characteristics and monitor device status
via a host controller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads
and/ or writes by the host. The timing set is identical to that of 8051-type microcontrollers operating in
serial port mode 0. For proper operation of the port and the transmit and receive registers, the user shouldprovide TCLK and RCLK as well as SCLK.
DS2181A
ADDRESS/COMMAND
An address/command byte write must precede any read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or write. The following nibble identifies register
address. The next 2 bits are reserved and must be set to 0 for proper operation. The last bit of the
address/command word enables the burst mode when set; the burst mode allows consecutive reading or
writing of all register data. Data is written to and read from the port LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Data is sampled on the rising edge of SCLK.
Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are
terminated and SDO tri-stated when CS returns to high.
CLOCKS
To access the serial port registers both TCLK and RCLK are required along with the SCLK. The TCLK
and RCLK are used to internally access the transmit and receive registers, respectively. The CCR is
considered a receive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/ command byte, data at SDI is strobed into theaddressed register on the next eight SCLK cycles (register write) or data is presented at SDO on the next
eight SCLK cycles (register read). SDO is tri-stated during writes and may be tied to SDI in applications
where the host processor has bi-directional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This
feature minimizes device initialization time on system power-up or reset. Burst mode is initiated when
ACB.7 is set and the address nibble is 0000. All registers must be read or written during the burst mode.
If CS transitions high before the burst is complete, data validity is not guaranteed.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONACB.7Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.ACB.6Reserved, must be 0 for proper operation.ACB.5Reserved, must be 0 for proper operation.
ADD3ACB.4MSB of register address.
ADD2ACB.3
ADD1ACB.2
ADD0ACB.1LSB of register address.
R/WACB.0Read/Write Select.0 = write addressed register.
1 = read addressed register.
DS2181A
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
TCR: TRANSMIT CONTROL REGISTER Figure 4
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
TUA1TCR.7Transmit Unframed All 1’s.0 = Normal operation.
1 = Replace outgoing data at TPOS and TNEG with unframed all
1’s code.
TSSTCR.6Transmit Signaling Select1
0 = Signaling data embedded in the serial bit stream is sampled at
TSER during timeslot 16.= Signaling data is channel associated and sampled at TSD as
shown in Table 6.
TSMTCR.5Transmit Signaling Mode1
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
INBSTCR.4International Bit Select
0 = Sample international bit at TIND.
1 = Outgoing international bit = TINR.7.NBSTCR.3National Bit Select0 = Sample national bits at TIND.
1 = Source outgoing national bits from TINR.4 through TINR.0.
XBSTCR.2Extra Bit Select
0 = Sample extra bits at TXD.1 = Source extra bits from TXR.0 through TXR.1 and TXR.3.
TSA1TCR.1Transmit Signaling All 1’s
0 = Normal operation.
1 = Force contents of timeslot 16 in all frames to all 1’s.
ODMTCR.0Output Data Mode0 = TPOS and TNEG outputs are 100% duty cycle.
DS2181A
NOTE:
1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled
internally; all timeslot 16 data is sampled at TSER.
CCR: COMMON CONTROL REGISTER Figure 5
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR.7Reserved; must be 0 for proper operation.
TAFPCCR.6Transmit Align Frame Position1
When clear, the CAS multiframe begins with a frame containing
the frame alignment signal. When set, the CAS multiframe begins
with a frame not containing the frame alignment signal.THDECCR.5Transmit HDB3 Enable0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
RHDECCR.4Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.1 = Incoming data is RPOS and RNEG is HDB3 coded.
TCECCR.3Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through
12 and 14 are replaced by CRC4 multiframe alignment and
checksum words.RCECCR.2Receive CRC4 Enable0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe
alignment once frame alignment complete.
SASCCR.1Sync Algorithm Select0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
LLBCCR.0Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG,and RCLK.
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not
affect CCS framing (RCR.5 = 1).
2. CCR is considered a receive register and operates from RCLK and SCLK.
DS2181A
RCR: RECEIVE CONTROL REGISTER Figure 6
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONRCR.7Reserved; must be 0 for proper operation.RCR.6Reserved; must be 0 for proper operation.
RSMRCR.5Received Signaling Mode0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
CMSCRCR.4CAS Multiframe Sync Criteria
0 = Declare sync when fixed sync criteria met.
1 = Declare sync when fixed criteria are met and two additionalconsecutive valid multiframe alignment signals are detected.
CMRCRCR.3CAS Multiframe Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if two consecutive timeslot
16 words have values of 0 in the first four MSB positions(0000xxxx).
FRCRCR.2Frame Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if bit 2 in timeslot 0 of non-
align frames is received in error on three consecutive occasions.SYNCERCR.1Sync EnableIf clear, the synchronizer will automatically begin resync if error
criteria are met. If high, no auto resync occurs.
RESYNCRCR.0Resync
When toggled low to high, the receive synchronizer will initiateimmediately. The bit must be cleared, then set again for
subsequent resyncs.
CEPT FRAME STRUCTURE
The CEPT frame is made up of 32 8-bit channels (time-slots) numbered from 0 to 31. The frame
alignment signal in bit positions 2 through 8 of timeslot 0 of every other frame is independent of thevarious multiframe modes described below. Outputs TAF and RAF indicate frames which contain the
alignment signal. Timeslot 0 of frames not containing the frame alignment signal is used for alarm and
national data. See the separate DS2181A CEPT Transceiver Application Note for more details.
CAS SIGNALLING
CEPT networks support Channel Associated Signaling (CAS) or Common Channel Signaling (CCS).These signaling modes are independently selectable for transmit and receive sides.
CAS (selected when TCR.5 = 0 and/or when RCR.5 = 0) is a bit-oriented signaling technique which
utilizes a 16-frame multiframe. The multiframe alignment signal (0-hex), extra and alarm bits occupy
timeslot 16 of frame 0. Timeslot 16 of the remaining 15 frames is reserved for channel signaling data.Four signaling bits (A, B, C and D) are transmitted once per multiframe as shown in Figure 7. Input
TMSYNC establishes the transmitted CAS multiframe position. Signaling data can be sourced from input
DS2181A
CCS SIGNALLING
CCS (selected when TCR.5 = 1 and/or when RCR.1 = 1) utilizes all bit positions of timeslot 16 in every
frame for message-oriented signaling data transmission. In CCS mode one can use either timeslot 16 or
any one of the other 30 data channels for message-oriented signaling. The CCS mode has no multiframe
structure and the insertion of CAS multiframe alignment, distant multiframe alarm and/or extra bits into
timeslot 16 is disabled. TSER is the source of timeslot 16 data.
CRC4 CODING
The need for enhanced error monitoring capability and additional protection against emulators of the
frame alignment word has led to the development of a cyclic redundancy check (CRC) procedure. When
enabled via CCR.2 and/or CCR.3, CRC4 coding replaces the international bit positions in frames 0
through 12 and 14 with a CRC4 multiframe alignment pattern and associated checksum words. The
CRC4 multiframe must begin with a frame containing the frame alignment signal (CCR.6 = 0). A risingedge at TMSYNC establishes the CRC4 multiframe alignment (TMSYNC will also establish outgoing
CAS multiframe alignment if enabled via TCR.5).
Incoming CRC4 multiframe alignment is indicated by RCSYNC. Detected CRC4 checksum errors are re-ported at output RFER and logged in the CECR.
RECEIVE SYNCHRONIZER
The fixed characteristics of the receive synchronizer may be modified by use of programmable
characteristics resident in the RCR and CCR. Sync criteria must be met before synchronization is
declared. Resync criteria establish error occurrences which will cause an auto-resync event when enabled
(RCR.1 = 0).
The receive synchronizer searches for the frame alignment pattern first. Once identified, the output timing
set associated with the framing pattern (all outputs except RCSYNC and RMSYNC) is updated to that
new alignment. If enabled, the synchronizer then begins CAS and/or CRC4 multiframe search; outputs
RMSYNC and/or RCSYNC are then updated. Output RLOS is held high during the entire resync process,then transitions low after the last output timing update indicating resync is complete. For more details
about the receive synchronizer, see the separate DS2181A CEPT Transceiver Application Note.
FIXED FRAME SYNC CRITERIA
Valid frame sync is assumed when the correct frame alignment signal is present in frame N and frame N
+ 2 and not present in frame N + 1 (bit 2 of timeslot 0 of Frame N + 1 is also checked for 1). CAS and/orCRC4 multiframe alignment search is initiated when the frame search is complete if enabled via RCR.5
and/or CCR.2.
FIXED CAS MULTIFRAME SYNC CRITERIA
CAS multiframe sync is declared when the multiframe alignment pattern is properly detected and timeslot
16 of the previous frame contains code other than zeros. If no valid pattern can be found in 12 to 14
milliseconds (no time-out period exists if CCR.1=1 or TEST=1), frame search is restarted.
FIXED CRC4 MULTIFRAME SYNC CRITERIA
CRC4 multiframe sync is declared if at least two valid CRC4 multiframe alignment signals are found
within 12 to 14 milliseconds (8 ms if CCR.1=1 or TEST=1) after frame alignment is completed. If not
found within 12 to 14 milliseconds (8 ms if CCR.1=1 or TEST=1), frame search is restarted. The search
DS2181A
FIXED FRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically initiate frame search whenever the frame
alignment word is received in error three consecutive times.
FIXED CAS MULTIFRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically initiate frame search whenever two consecutive
CAS multiframe alignment words are received in error.
FIXED CRC4 RESYNC CRITERIA
If CCR.1=1 or if the TEST pin is tied high, then the DS2181A will initiate the resync at the FAS level if
915 or more CRC4 words out of 1000 are received in error.
CAS SIGNALLING SOURCE
CAS applications sample signaling data at TSER when TCR.6 = 0; an on-chip data multiplexer accepts
channel-associated data input at TSD when TCR.6 = 1. The data multiplexer must be disabled (TCR.6 =0) when the CCS mode is enabled (TCR.5 = 1).
TSD INPUT TIMING (TCR.6 = 1; TCR.5 = 0) Table 6
NOTE:
1. A, B, C and D data is sampled on falling edges of TCLK during bit times 5, 6, 7 and 8 of timeslots
indicated.
DS2181A
TSD INPUT TIMING Figure 7
CAS OUTPUT FORMAT IN TIMESLOT 16 Figure 8FRAME 1FRAME 15ABCD forTimeslot 1ABCD fortimeslot 17ABCD forTimeslot 15
NOTE:
1. Timeslot 16 of frame 0 is reserved for the multiframe alignment word (0000), distant multiframe
alarm (Y) and extra bits (X-XX).
TINR: TRANSMIT INTERNATIONAL AND NATIONAL REGISTER Figure 9
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
INBTINR.7International Bit. Inserted into the outgoing data stream when
TCR.4 = 1.TINR.6Reserved; must be 0 for proper operation.TRATINR.5Transmit Remote Alarm0 = Normal operation; bit 3 of timeslot 0 in non-alignment frame
clear.
1 = Alarm condition; bit 3 of timeslot 0 in non-align frames set.
NB4TINR.4Transmit National Bits. Inserted into the outgoing data stream atTPOS and TNEG when TCR.3 = 1.
NB5TINR.3
NB6TINR.2
NB7TINR.1
NB8TINR.0
TRANSMIT INTERNATIONAL AND NATIONAL DATA
Bit 1 of timeslot 0 in all frames is known as the international bit. When TCR.4 = 1, the transmitted
international bit is sourced from TINR.7. When TCR.4 = 0, the transmitted international bit is sampled at
DS2181A
Bits 4 through 8 of timeslot 0 in non-align frames are reserved for national use. When TCR.3 = 1, the
transmitted national bits are sourced from register locations TINR.4 through TINR.0. If TCR.3 = 0, the
national bits are sampled at TIND during bit times 4 through 8 of timeslot 0 in non-align frames.
Reserved bit positions in the TINR must be set to 0 when written; those bits can be 0 or 1 when read.
TXR: TRANSMIT EXTRA REGISTER Figure 10
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONTXR.7Reserved; must be 0 for proper operation.TXR.6Reserved; must be 0 for proper operation.TXR.5Reserved; must be 0 for proper operation.TXR.4Reserved; must be 0 for proper operation.
XB1TXR.3Extra Bit 1TDMATXR.2Transmit Distant Multiframe Alarm0 = Normal operation; bit 6 of timeslot 16 in frame 0 clear.
1 = Alarm condition; bit 6 of timeslot 16 in frame 0 set.
XB2TXR.1Extra Bit 2
XB3TXR.0Extra Bit 3
TRANSMIT EXTRA DATA
In the CAS mode, timeslot 16 of frame 0 contains the multiframe alignment pattern, extra bits and the
distant multiframe alarm. When CAS is enabled (TCR.5 = 0), the extra bits are sourced from TXR.0,
TXR.1 and TXR.3 (TCR.2 = 1) or the extra bits are sampled externally at TXD during the extra bit time
(TCR.2 = 0). The extra bits, alignment pattern and alarm signal are not utilized in the CCS mode (TCR.5= 1); input TSER overwrites all timeslot 16 bit positions.
Reserved bit positions in the TXR must be set to 0 when written; those bits can be 0 or 1 when read.
TIR1 - TIR4: TRANSMIT IDLE REGISTERS Figure 11
(MSB) (LSB)TIR1TIR2TIR3TIR4
SYMBOLPOSITIONNAME AND DESCRIPTION
TS31TIR4.7Transmit Idle Registers
TS0TIR1.0Each of these bit positions represents a timeslot in the outgoing
stream at TPOS and TNEG; when set, the contents of that timeslot
are forced to idle code (11010101).
NOTE:
DS2181A
TRANSMIT TIMING
A low-high transition at TMSYNC once per multiframe (every 2 milliseconds) or at a multiple of the
multiframe rate establishes outgoing CAS and/or CRC4 multiframe alignment. Output TMO indicates
that alignment. A low-high transition at TFSYNC at the frame rate (125 us) or at a multiple of the frame
rate establishes the outgoing frame position. Output TAF indicates that alignment. TMSYNC and/or
TFSYNC can be tied low by the user, in which case the arbitrary frame and multiframe alignmentestablished by the device will be indicated at TMO and TAF.
Output TAF also indicates frames containing the frame alignment signal. Those frames can be even or
odd numbering frames of the outgoing CAS multiframe (CCR.6).
TRANSMIT MULTIFRAME TIMING Figure 12
NOTES:
1. Alignment frames are even frames of the CAS and/or CRC4 multiframes (CCR.6 = 0).
2. Alignment frames are odd frames of the CAS multiframe (CCR.6 = 1).
DS2181A
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13
NOTES:1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect
to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC.
2. TAF transitions on true frame boundaries.
3. Delay from TSER to TPOS, TNEG is five TCLK periods.
TRANSMIT SIGNALING TIMESLOT TIMING Figure 14
RECEIVE SIGNALING
Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in
timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD duringthe timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design.

Partno	Mfg	Dc	Qty	Available	Descript
DS2181A	DALLAS	N/a	125	avai	CEPT Primary Rate Transceiver
DS2181A	DALCAS	N/a	520	avai	CEPT Primary Rate Transceiver