DS2180A+-DS2180AQ-DS2180AQ+-DS2180AQN+ Fast Delivery |IC PHOENIX CO.,LIMITED

DS2180A+ ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AN ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AQ ,T1 TransceiverBLOCK DIAGRAM Figure 1 2 of 35DS2180ATRANSMIT
DS2180AQ+ ,T1 TransceiverFEATURES PIN ASSIGNMENT Single chip DS1 rate transceiver TMSYNC 1 40 VDD Supports common fra ..
DS2180AQN ,T1 Transceiverapplications (12frames/superframe). The 193E framing mode supports the extended superframe format ..
DS2180AQN+ ,T1 TransceiverFeatures such as selection “clear” DS0 channels, insertion of idle code and alterationof sync algor ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..

DS2180A+-DS2180AQ-DS2180AQ+-DS2180AQN+
T1 Transceiver
FEATURESSingle chip DS1 rate transceiverSupports common framing standards12 frames/superframe “193S”– 24 frames/superframe “193E”Three zero suppression modesB7 stuffingB8ZSTransparentSimple serial interface used for config-
uration, control and status monitoring in
“processor” mode
=“Hardware” mode requires no hostprocessor; intended for stand-alone app-
licationsSelectable 0, 2, 4, 16 state robbed bit
signaling modesAllows mix of “clear” and “non-clear” DS0channels on same DS1 linkAlarm generation and detectionReceive error detection and counting for
transmission performance monitoring5V supply, low-power CMOS technologySurface-mount package available, designated
DS2180AQIndustrial temperature range of -40°C to
+85°C available, designated DS2180AN orDS2180AQNCompatible to DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2175 T1/CEPT
Elastic Store, DS2290 T1 Isolation Stik, andDS2291 T1 Long Loop Stik
PIN ASSIGNMENT
DS2180A
RPOS
RST
TEST
RABCD
RMSYNC
RFSYNC
SDO
SPS
VSS
DS1386/DS1386P
DESCRIPTION
The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier
transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12frames/superframe). The 193E framing mode supports the extended superframe format (24
frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression
and signaling modes.
Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriateframing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides
output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and
multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and
transmission errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero
suppression, alarm and signaling formats. User access to the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port
which can be used for device configuration, control and status monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into “hard-
wired” select pins. Features such as selection “clear” DS0 channels, insertion of idle code and alteration
of sync algorithm are unavailable in the hardware mode.
DS2180A BLOCK DIAGRAM Figure 1
DS2180A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
DS2180A
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
DS2180A
REGISTER SUMMARY Table 5
NOTES:
1. Transmit or receive side register.2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address commandbyte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge ofSCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
DS2180A
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into
the addressed register on the rising edges of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where thehost processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively read and written by the host processor. A
burst read is used to poll all registers; RSR contents will be unaffected. This feature minimizes device
initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address
nibble is 0000. Burst is terminated by a low-high transition on CS.
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONACB.7Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.ACB.6Reserved, must be 0 for proper operation.ACB.5Reserved, must be 0 for proper operation.
ADD3ACB.4MSB of register address.
ADD0ACB.1LSB of register address.WACB.0Read/Write Select.
0 = write addressed register.
1 = read addressed register.
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
DS2180A
ACB: ADDRESS COMMAND BYTE Figure 4
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONCCR.7Reserved, must be 0 for proper operation.
FRSR2CCR.6Function of REC Status Register 2.
0 = Detected B8ZS code words reported at RSR.2.
1 = COFA (Change-of-Frame Alignment) reported at RSR.2 whenlast resync resulted in change of frame or multiframe alignment.
EYELMDCCR.5193E Yellow Mode Select.
0 = Yellow alarm is a repeating pattern set of 00 hex and FF hex.
1 = Yellow alarm is a 0 in the bit 2 position of all channels.CCR.4Frame Mode Select.0 = D4 (193S, 12 frames/superframe).
1 = Extended (193E, 24 frames/superframe).
SYELMDCCR.3193S Yellow Mode Select. Determines yellow alarm type to be
transmitted and detected while in 193S framing. If set, yellow
alarms are a 1 in the S-bit position of frame 12; if cleared, yellowalarm is a 0 in bit 2 of all channels. Does not affect 193E yellow
alarm operation.
B8ZSCCR.2Bipolar eight zero substitution.
0 = No B8ZS.
1 = B8ZS enabled.
(Note: This bit must be set to 0 when CCR.1=1)CCR.1Bit seven zero suppression. If CCR.1=1, channels with an all zero
content will be transmitted with bit 7 forced to 1. If CCR.1=0, no
bit 7 stuffing occurs.
(Note: This bit must be set to 0 when CCR.2=1)LPBKCCR.0Loopback. When set, the device internally loops output transmit
data into the incoming receive data buffers and TCLK is internally
substituted for RCLK.
LOOPBACK (Refer to Figure 4)
Enabling loopback will typically induce an out-of-frame (OOF) condition. If appropriate bits are set in
the receive control register, the receiver will resync to the looped transmit frame alignment. During thelooped condition, the transmit outputs (TPOS, TNEG) will transmit unframed all 1's. All operating modes
(B8ZS, alarm, signaling, etc.) except for blue alarm transmission are available in loopback.
BIT SEVEN STUFFING
Existing systems meet 1's density requirements by forcing bit 7 of all zero channels to 1. Bit 7 stuffing is
globally enabled by asserting bit CCR.1 and may be disabled on an individual channel basis by setting
appropriate bits in TTR1–TTR3. Bit 7 stuffing and B8ZS modes should not be enabled simultaneously.
Enabling both results in LOS.
DS2180A
B8ZS
The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding
maintains system 1’s density requirements without disturbing data integrity as required in emerging clear
channel applications. B8ZS coding replaces eight consecutive outgoing 0's with a B8ZS code word. Any
received B8ZS code word is replaced with all 0’s. B8ZS and bit 7 stuffing modes should not be enabled
simultaneously. Enabling both results in LOS.
TCR: TRANSMIT CONTROL REGISTER Figure 5
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
ODFTCR.7Output Data Format.
0 = Bipolar data at TPOS and TNEG.1 = NRZ data at TPOS; TNEG=0.
TFPTTCR.6Transmit Framing Pass-through.
0 = FT/FPS sourced internally.
1 = FT/FPS sampled at TSER during F-bit time.
TCPTCR.5Transmit CRC Pass-through.0 = Transmit CRC code internally generated.
1 = TSER sampled at CRC F-bit time for external CRC insertion.
RBSETCR.4Robbed Bit Signaling Enable.
1 = Signaling inserted in all channels during signaling frames.
0 = No signaling inserted. (The TTR registers allow the user todisable signaling insertion on selected DS0 channels.)
TISTCR.3Transmit Idle Code Select. Determines idle code format to be
inserted into channels marked by the TIR registers.
0 = Insert 7F (Hex) into marked channels.
1 = Insert FF (Hex) into marked channels.193SITCR.2193S S-bit Insertion. Determines source of transmitted S-bit.
0 = Internal S-bit generator.
1 = External (sampled at TLINK input).
TBLTCR.1Transmit Blue Alarm.
0 = Disabled.1 = Enabled.
TYELTCR.0TYEL TCR.0 Transmit Yellow Alarm.
0 = Disabled.
1 = Enabled.
TRANSMIT BLUE ALARM
The blue alarm (also known as the AIS, Alarm Indication Signal) is an unframed, all 1’s sequenceenabled by asserting TCR.1. Blue alarm overrides all other transmit data patterns and is disabled by
clearing TCR.1. Use of the TIR registers allows a framed, all 1’s alarm transmission if required by the
network.
TRANSMIT YELLOW ALARM
DS2180A
TRANSMIT SIGNALING
When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S) or in frames 6, 12, 18
and 24 (193E) in the 8th bit position of every channel word. Signaling data is sampled at TABCD on the
falling edge of TCLK during bit 8 of each input word during signaling frames. Logical combination of
clocks TMO, TSIGFR and TSIGSEL allows external multiplexing of separate serial links for A, B or A,
B, C, D signaling sources.
TTR1–TTR3: TRANSMIT TRANSPARENCY REGISTERS Figure 6
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
CH24TTR3.7
CH1TTR1.0
Transmit Transparent Registers. Each of these bit positionsrepresents a DS0 channel in the outgoing frame. When set, the
corresponding channel is transparent.
TIR1–TIR3: TRANSMIT IDLE REGISTERS Figure 7
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
CH24TIR3.7
CH1TIR1.0
Transmit Idle Registers. Each of these bit positions represents a
DS0 channel in the outgoing frame. When set, the corresponding
channel will output an idle code format determined by TCR.2.
TRANSMIT CHANNEL TRANSPARENCY
Individual DS0 channels in the T1 frame may be programmed clear (no inserted robbed bit signaling and
no bit 7 zero suppression) by setting the appropriate bits in the transmit transparency registers. Channel
transparency is required in mixed voice/data or data-only environments such as ISDN, where dataintegrity must be maintained.
TRANSMIT IDLE CODE INSERTIONIndividual outgoing channels in the frame can be programmed with idle code by asserting the appropriate
bits in the transmit idle registers. One of two idle code formats, 7F (Hex) and FF (Hex) may be selected
by the user via TCR.3. If enabled, robbed bit signaling data is inserted into the idle channel, unless the
appropriate TTR bit is set for that channel. This feature eliminates external hardware currently required to
intercept and stuff unoccupied channels in the DS1 bit stream.
DS2180A
TRANSMIT INSERTION HIERARCHY Figure 8
DS2180A
193S TRANSMIT MULTIFRAME TIMING Figure 9
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish
multiframe boundaries, allowing internal counters to determine frame timing.b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe
boundaries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and
superframe timing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establishan arbitrary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in
frames indicated.
3. When external S-bit insertion is enabled, TLINK will be sampled during the F-bit time of even frames
and inserted into the outgoing data stream.
DS2180A
193E TRANSMIT MULTIFRAME TIMING Figure 10
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish
multiframe boundaries, allowing internal counters to determine frame timing.b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe
boundaries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and
superframe timing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establishan arbitrary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in
frames indicated.
3. TLINK is sampled during the F-bit time of odd frames and inserted into the outgoing data stream
(FDL data).
DS2180A
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11
NOTES:
1. TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated forinsertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is
sampled during even frames.
2. If TCR.5=1, TSER is sampled during the F-bit time of CRC frames for insertion into the outgoing
data stream (193E framing only).
DS2180A
RECEIVE CONTROL REGISTER Figure 12
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
ARCRCR.7Auto Resync Criteria.
0 = Resync on OOF or RCL event.
1 = Resync on OOF only.
OOFRCR.6Out-of-frame (OOF) Condition Detection.
0 = 2 of 4 framing bits in error.
1 = 2 of 5 framing bits in error.
RCIRCR.5Receive Code Insert. When set, the receive code selected by
RCR.4 is inserted into channels marked by RMR registers. If clear,no code is inserted.
RCSRCR.4Receive Code Select.
0 = Idle code (7F Hex).
1 = Digital milliwatt.
SYNCCRCR.3Sync Criteria. Determines the type of algorithm utilized by thereceive synchronizer and differs for each frame mode.
193S Framing (CCR.4=0).
0 = Synchronize to frame boundaries using FT pattern, then search
for multiframe by using FS.
1 = Cross couple FT and FS patterns in sync algorithm.193E Framing (CCR.4=1).
0 = Normal sync (utilizes FPS only).
1 = Validate new alignment with CRC before declaring sync.
SYNCTRCR.2Sync Time. If set, 24 consecutive F-bits of the framing pattern
must be qualified before sync is declared. If clear, 10 bits arequalified.
SYNCERCR.1Sync Enable. If clear, the transceiver will automatically begin a
resync if two of the previous four or five framing bits were in error
or if carrier loss is detected. If set, no auto resync occurs.
RESYNCRCR.0Resync. When toggled low to high, the transceiver will initiateresync immediately. The bit must be cleared, then set again for
subsequent resyncs.
RECEIVE CODE INSERTION
Incoming receive channels can be replaced with idle (7F Hex) or digital milliwatt (μ-LAW format) codes.
The receive mark registers indicate which channels are inserted. When set, bit RCR.5 serves as a“global” enable for marked channels and bit RCR.4 selects inserted code format: 0 = idle code, 1 = digital
milliwatt.
RECEIVE SYNCHRONIZER
Bits RCR.0 through RCR.3 allow the user to control operational characteristics of the synchronizer. Sync
algorithm, candidate qualify testing, auto resync, and command resync modes may be altered at any time
in response to changing span conditions.
DS2180A
RECEIVE SIGNALING
Robbed bit signaling data is presented at RABCD during each channel time in signaling frames for all 24
incoming channels. Logical combination of clocks RMSYNC, RSIGFR and RSIGSEL allow the user to
identify and extract AB or ABCD signaling data.
RMR1–RMR3: RECEIVE MARK REGISTERS Figure 13
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
CH24
CH1
RMR3.7
RMR1.0
Receive Mark Registers. Each of these bit positions represents a
DS0 channel in the incoming T1 frame. When set, the
corresponding channel will output codes determined by RCR.4 and
RCR.5.193S RECEIVE MULTIFRAME TIMING Figure 14
NOTES:
1. Signaling data is updated during signaling frames on channel boundaries. RABCD is the LSB of each
channel word in non-signaling frames
2. RLINK data (S-bit) is updated one bit time prior to S-bit frames and held for two frames.
DS2180A
193E RECEIVE MULTIFRAME TIMING Figure 15
NOTES:1. Signaling data is updated during signaling frames on channel boundaries. RABCD outputs the LSB of
each channel word in non-signaling frames.
2. RLINK data (FDL-bit) is updated one bit time prior to odd frames and held for two frames.
DS2180A
RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16
NOTES:
1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is heldacross multiframe edges.
2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
DS2180A
RSR: RECEIVE STATUS REGISTER Figure 17
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
BVCSRSR.7Bipolar Violation Count Saturation. Set when the 8-bit counter
at BVCR saturates.
ECSRSR.6Error Count Saturation. Set when either of the 4-bit counters atECR saturates.
RYELRSR.5Receive Yellow Alarm. Set when yellow alarm detected.
(Detected yellow alarm format determined by CCR.4 and CCR.3.)
RCLRSR.4Receive Carrier Loss. Set when 32 consecutive 0’s appear at
RPOS and RNEG.
FERRRSR.3Frame Bit Error. Set when FT (193S) or FPS (193E) bit error
occurs.
B8ZSDRSR.2Bipolar Eight Zero Substitution Detect. Set when B8ZS code
word detected.
RBLRSR.1Receive Blue Alarm. Set when two consecutive frames have lessthan three 0’s (total) in the data stream (F-bit positions not tested).
RLOSRSR.0Receive Loss of Sync. Set when resync is in process; if RCR.1=0,
RLOS transitions high on an OOF event or carrier loss indicating
auto resync.
RECEIVE ALARM REPORTING
Incoming serial data is monitored by the transceiver for alarm occurrences. Alarm conditions are reported
in two ways: via transitions on the alarm output pins and registered interrupt, in which the host controller
reads the RSR in response to an alarm-driven interrupt. Interrupts may be direct, in which the transceiver
demands service for a real-time alarm, or count-overflow triggered, in which an onboard alarm event
counter exceeds a user-programmed threshold. The user may mask individual alarm conditions byclearing the appropriate bits in the receive interrupt mask register (RIMR).
ALARM SERVICINGThe host controller must service the transceiver in order to clear an interrupt condition. Clearing
appropriate bits in the RIMR will unconditionally clear an interrupt. Direct interrupt (those driven from
real-time alarms) will be cleared when the RSR is directly read unless the alarm condition still exists.
Count-overflow interrupts (BVCS, ECS) are not cleared by a direct read of the RSR. They will be cleared
only when the user presets the appropriate count register to a value other than all 1’s. A burst read of theRSR will not clear an interrupt condition.

Partno	Mfg	Dc	Qty	Available	Descript
DS2180A+	MAIXM	N/a	1500	avai	T1 Transceiver
DS2180AQ	DALLAS ?	N/a	50	avai	T1 Transceiver
DS2180AQ+	MAIXM	N/a	1500	avai	T1 Transceiver
DS2180AQN+	MAIXM	N/a	1500	avai	T1 Transceiver