DS2176Q+ ,T1 Receive BufferFEATURES PIN ASSIGNMENT§ Synchronizes loop–timed and system–timedT1 data streamsSIGH 1 24 VDDRMSYN2 ..
DS2176QN ,T1 Receive Bufferapplications with one “skinny” 24–lead package.Application areas include digital trunks, drop and i ..
DS2180A ,T1 TransceiverFEATURES PIN ASSIGNMENT Single chip DS1 rate transceiver TMSYNC 1 40 VDD Supports common fra ..
DS2180A+ ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AN ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AQ ,T1 TransceiverBLOCK DIAGRAM Figure 1 2 of 35DS2180ATRANSMIT
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2176Q-DS2176Q+-DS2176QN
T1 Receive Buffer
FEATURESSynchronizes loop–timed and system–timed
T1 data streamsTwo–frame buffer depth; slips occur on frameboundariesOutput indicates when slip occursBuffer may be recentered externallyIdeal for 1.544 to 2.048 MHz rate conversionInterfaces to parallel or serial backplanes§ Extracts and buffers robbed–bit signalingInhibits signaling updates during alarm or slip
conditionsIntegration feature “debounces” signalingSlip–compensated output indicates whensignaling updates occurCompatible with DS2180A T1 TransceiverSurface mount package available, designated
DS2176QIndustrial temperature range of –40°C to+85°C available, designated DS2176N
PIN ASSIGNMENT
DESCRIPTIONThe DS2176 is a low–power CMOS device specifically designed for synchronizing receive side loop–timed T–carrier data streams with system side timing. The device has several flexible operating modes
which simplify interfacing incoming data to parallel and serial TDM backplanes. The device extracts,
buffers and integrates ABCD signaling; signaling updates are prohibited during alarm or slip conditions.
The buffer replaces extensive hardware in existing applications with one “skinny” 24–lead package.
SCKLSEL
24-PIN 300 MIL DIP
28-PIN PLCC
SSER
SLIP
SBIT8
SMSYNC
SCHCLKSIGFRZ
4 3 2 1 28 27 26
12 13 14 15 16 17 18
DS2176
DS2176 BLOCK DIAGRAM Figure 1
DS2176
PIN DESCRIPTION Table 1DS2176
OVERVIEWThe DS2176 performs two primary functions: 1) synchronization of received T1 PCM data (looped
timed) to host backplane frequencies; 2) supervision of robbed–bit signaling data embedded in the data
stream. The buffer, while optimized for use with the DS2180A T1 Transceiver, is also compatible with
other transceiver devices. The DS2180A data sheet should serve as a valuable reference when designing
with the DS2176.
RECEIVE SIDE TIMING FIGURE 2
DATA SYNCHRONIZATION
PCM BUFFERThe DS2176 utilizes a 2–frame buffer (386 bits) to synchronize incoming PCM data to the system
backplane clock. The buffer samples data at RSER on the falling edge of RCLK. Output data appears atSSER and is up-dated on the rising edge of SYSCLK. A rising edge at RMSYNC establishes receive side
frame and multi-frame alignment. A rising edge at SFSYNC establishes system side frame alignment.
The buffer depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is
completely emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always
occur on frame boundaries.
SLIP CORRECTION CAPABILITYThe 2–frame buffer depth is adequate for most T–carrier applications where short–term jitter
synchronization, rather than correction of significant frequency differences, is required. The DS2176
provides an ideal balance between total delay and slip correction capability.
BUFFER RECENTERINGMany applications require that the buffer be recentered during system power–up and/or initialization.
Forcing ALN low recenters the buffer on the occurrence of the next frame sync boundary. A slip willoccur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, no
adjustment (slip) occurs. SLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active–
low, open collector output.
BUFFER DEPTH MONITORINGSMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance
between rising edges at RMSYNC and SMSYNC indicates the current buffer depth. Slip direction and/or
an impending slip condition may be determined by monitoring RMSYNC and SMSYNC real time.SMSYNC is held high for 65 SYSCLK cycles.
CLOCK SELECT
DS2176
passed through the receive buffer and presented at SSER immediately after the rising edge of the system
side frame sync. The F–bit is dropped in 2.048 MHz applications and the MSB of channel 1 appears at
SSER one bit period after a rising edge at SFSYNC. SSER is forced to 1 in all channels greater than 24.
See Figures 3 and 4.
In 2.048 MHz applications (SCLKSEL=1), the PCM buffer control logic establishes slip criteria different
from that used in 1.544 MHz applications to compensate for the faster system-side read frequency.
PARALLEL COMPATIBILITYThe DS2176 is compatible with parallel and serial back-planes. Channel 1 data appears at SSER after a
rising edge at SFSYNC as shown in Figures 3 and 4 (serial applications, S/
look–ahead circuit in parallel applications (S/
convert parallel data eternally.
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 3
DS2176
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 2.048 MHz) Figure 4
193S SYSTEM MULTIFRAME TIMING Figure 5
193E SYSTEM MULTIFRAME TIMING Figure 6
DS2176
SIGNALING SUPERVISION
EXTRACTIONIn digital channel banks, robbed–bit signaling data is inserted into the LSB position of each channel
during signaling frames. In 193S framing (FMS=0) applications, A signaling data is inserted into frame 6
and B signaling data is inserted into frame 12. 193E framing (FMS=1) includes two additional signaling
bits: C signaling is inserted into frame 18 and D signaling is inserted into frame 24. This embedded
signaling data is synchronized to system side timing (via the PCM buffer) before being extracted andpresented at outputs A, B, C, and D. Outputs A, B, C, and D are valid for each individual channel time
and are repeated per channel for all frames of the multiframe. In 193S applications, outputs C and D
contain the previous multiframe’s A and B data. Signaling updates occur once per multiframe at the ris-
ing edge of SMSYNC unless prohibited by a freeze.
FREEZEThe signaling buffer allows the DS2176 to “freeze” (pre-vent update of) signaling information during
alarm or slip conditions. A slip condition or forcing SIGH low freezes signaling; duration of the freeze is
dependent on SM0 and SM1. Updates will be unconditionally prohibited when SIGH is held low. Duringfreezing conditions “old” data is recirculated in the output registers and appears at A, B, C and D.
SIGFRZ is held high during the freeze condition, and returns low on the next signaling update. Input to
output delay of signaling data is equal to 1 multiframe (the depth of the signaling buffer) the current
depth of the PCM buffer (1 frame ± approximately 1 frame).
INTEGRATIONSignaling integration is another feature of the DS2176; when selected, it minimizes the impact of random
noise hits on the span and resultant robbed–bit signaling corruption. Integration requires that per–channel
signaling data be in the same state for two or more multiframes before appearing at A, B, C and D. SM0
and SM1 are used to select the degree of integration or to totally by-pass the feature. Integration is limited
to two multi-frames during slip or alarm conditions to minimize up-date delay.
CLEAR CHANNEL CONSIDERATIONSThe DS2176 does not merge the “processed” signaling information with outgoing PCM data at SSER;
this assures integrity of data in clear channel applications. SBIT8 indicates the LSB position of each
channel; when combined with off–chip support logic, it allows the user to selectively re–insert robbed–bit
signaling data into the outgoing data stream.
DS2176
SIGNALING SUPERVISION MODES Table 2
NOTE:1. During slip or alarm conditions, integration is limited to two multiframes to minimize signaling delay.
SLIP AND SIGNALING SUPERVISION LOGIC TIMING Figure 7
NOTES:1. Integration feature disabled (SM0=SM1=0) in timing set shown.
2. Depending on present buffer depth, forcing ALN low may or may not cause a slip condition.
