DS2174Q ,EBERTFEATURES PIN ASSIGNMENT § Generates and detects digital patterns for analyzing and trouble-shootin ..
DS2174Q+ ,EBERTAPPLICATIONS Software-programmable bit error insertion Routers Fully independent transmit and re ..
DS2174QN ,EBERTfeatures bit-serial, nibble-parallel, and byte-parallel data interfaces, and ngenerates and uniquel ..
DS2174QN+ ,EBERTPIN DESCRIPTION .82. PARALLEL CONTROL INTERFACE.......103. CONTROL REGISTERS ...113.1 MODE SELECT . ..
DS2175 ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2175S ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2174Q-DS2174QN
EBERT
FEATURES § Generates and detects digital patterns for analyzing and trouble-shooting digital
communications systems § Programmable polynomial length and
feedback taps for generation of any
pseudorandom patterns up to 232 - 1; up to 32 taps can be used in the feedback path
§ Programmable, user-defined pattern registers for long repetitive patterns up to 512 bytes in
length
§ Large 48-bit count and bit error count registers § Software-programmable bit error insertion
§ Fully independent transmit and receive paths § 8-bit parallel-control port
§ Detects polynomial test patterns in the
presence of bit error rates up to 10-2 § Programmable for serial, 4-bit parallel, or 8-bit
parallel data interfaces § Serial mode clock rate is 155MHz; byte mode
is 80MHz for a net 622Mbps; OC-3 Available in 44-pin PLCC
ORDERING INFORMATION DS2174Q 44-Pin PLCC 0°C to +70°C
DS2174QN 44-Pin PLCC -40°C to +85°C
PIN ASSIGNMENT APPLICATIONS § Routers § Channel Service Units (CSUs)
§ Data Service Units (DSUs)
§ Muxes § Switches
§ Digital-to-Analog Converters (DACs) § CPE Equipment
§ Bridges
§ Smart Jack
DESCRIPTION The DS2174 enhanced bit error rate tester (EBERT) is a software-programmable test-pattern generator,
receiver, and analyzer capable of meeting the most stringent error-performance requirements of digital transmission facilities. It features bit-serial, nibble-parallel, and byte-parallel data interfaces, and
generates and uniquely synchronizes to pseudorandom patterns of the form 2n - 1, where n can take on
values from 1 to 32, and user-defined repetitive patterns of any length up to 512 octets. D1D0TDAT7
TDAT6
GNDTDAT5
TDAT4TDAT3TDAT2
GND
RDAT3RDAT4RDAT5
RDAT6RDAT7
GNDA1A2A3
RDAT2RDAT1RDAT0RCLKVDDD7D6D5D4D3WR
TESTTEST
GNDVDD
TCLK
TCLK_EN
TCLKO
TDAT0TDAT1
DS2174
TABLE OF CONTENTS
1. GENERAL OPERATION................................................................................................................4 1.1 PATTERN GENERATION...........................................................................................................4
1.2 PATTERN SYNCHRONIZATION...............................................................................................5
1.3 BIT ERROR RATE (BER) CALCULATION...............................................................................5
1.4 GENERATING ERRORS..............................................................................................................5
1.5 CLOCK DISCUSSION..................................................................................................................6
1.6 POWER-UP SEQUENCE..............................................................................................................6
1.7 DETAILED PIN DESCRIPTION..................................................................................................8
2. PARALLEL CONTROL INTERFACE........................................................................................10
3. CONTROL REGISTERS...............................................................................................................11 3.1 STATUS REGISTER...................................................................................................................15
3.2 PSEUDORANDOM PATTERN REGISTERS...........................................................................15
3.3 TEST REGISTER........................................................................................................................17
3.4 COUNT REGISTERS..................................................................................................................17
4. RAM ACCESS.................................................................................................................................18 4.1 INDIRECT ADDRESSING.........................................................................................................18
5. DC OPERATION............................................................................................................................19
6. AC TIMING CHARACTERISTICS.............................................................................................20 6.1 PARALLEL PORT......................................................................................................................20
6.2 DATA INTERFACE....................................................................................................................22
7. MECHANICAL DIMENSIONS....................................................................................................24
DS2174
LIST OF FIGURES Figure 1-1: BLOCK DIAGRAM.............................................................................................................6
Figure 6-1: READ TIMING..................................................................................................................20
Figure 6-2: WRITE TIMING................................................................................................................21
Figure 6-3: TRANSMIT INTERFACE TIMING..................................................................................22
Figure 6-4: RECEIVE INTERFACE TIMING.....................................................................................23
LIST OF TABLES Table 1-1: PIN ASSIGNMENT...............................................................................................................7
Table 2-1: REGISTER MAP.................................................................................................................10
Table 3-1: MODE SELECT..................................................................................................................13
Table 3-2: ERROR BIT INSERTION...................................................................................................13
Table 3-3: PSEUDORANDOM PATTERN GENERATION...............................................................16
Table 5-1: RECOMMENDED DC OPERATING CONDITIONS.......................................................19
Table 5-2: DC CHARACTERISTICS...................................................................................................19
Table 6-1: PARALLEL PORT READ TIMING...................................................................................20
Table 6-2: PARALLEL PORT WRITE TIMING.................................................................................21
Table 6-3: TRANSMIT DATA TIMING..............................................................................................22
Table 6-4: RECEIVE DATA TIMING.................................................................................................23
DS2174
1. GENERAL OPERATION
1.1 Pattern Generation Polynomial Generation
The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path of the polynomial generator. It also features a seed register that can be used to preload the polynomial
generator with a seed value. This is done on the rising edge of TL in Control Register 1.
The DS2174 generates polynomial patterns of any length up to and including 232 - 1. All of the industry-
standard polynomials can be programmed using the control registers. The polynomial is generated using a shift register of programmable length and programmable feedback tap positions. The user has access to
all combinations of pattern length and pattern tap location to generate industry-standard polynomials or other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the
polynomial 220 - 1. This pattern has the additional requirement that “an output bit is forced to a ONE
whenever the next 14 bits are ZERO.” Setting the QRSS bit in Control Register 1 causes the pattern generator to enforce this rule. Repetitive Pattern Generation
In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The
programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through
PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is
addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in the memory.
Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to
store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8
bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is
used in serial mode: a 5-bit pattern is written to memory 5 times. For example,
To generate a 00001 pattern at the serial output, write these bytes to memory:
DS2174
1.2 Pattern Synchronization
Synchronization
The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free
when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to declare loss of pattern sync, set the RLOS bit, and the synchronizer comes back online. Polynomial Synchronization
Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte
mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit that does not match the polynomial is counted as a bit error. Repetitive Pattern Synchronization
Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The
actual sync time depends on the nature of the pattern and the location of the synchronization pointer. Errors that occur during synchronization could affect the sync time; at least one complete error-free
repetition must be received before synchronization is declared. Once synchronized, any bit that does not match the pattern that is programmed in the on-board RAM is counted as a bit error.
1.3 Bit Error Rate (BER) Calculation Counters
The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has
large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,
and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but
at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours. To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the
contents into the count registers. At T = 0, these results should be ignored. At this point, the device is
counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and
reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit
counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cycles
have to be accumulated in software. 1.4 Generating Errors
Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted data stream. Injecting errors allows users to stress communication links and to check the functionality of
error monitoring equipment along the path.
DS2174
1.5 Clock Discussion
There are two methods for moving test patterns through a telecom network.
1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn
outputs remain active during clock gaps. 2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the
TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.
TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at the level of the last bit transmitted (output high for a 1, output low for a 0). 1.6 Power-Up Sequence
On power-up, the registers in the DS2174 are in a random state. The user must program all the internal registers to a known state before proper operation can be ensured.
Figure 1-1. BLOCK DIAGRAM
D[7:0] CS RD WR A[3:0]
RDAT[7:0]
TCLK0
TDAT[7:0]
TCLK
TCLK_EN
RCLK_EN
RCLK SYNC
DS2174
Table 1-1. PIN ASSIGNMENT
DS2174
1.7 Detailed Pin Description
Signal Name: RCLK Signal Description: Receive Clock
Signal Type: Input
Receive Clock Input. Up to a 155MHz clock to operate the receive circuit. Input data at RDATn is sampled on the rising edge of RCLK. Signal Name: RCLK_EN
Signal Description: Receive Clock Enable
Signal Type: Input Gaps the RCLK input to the receive circuit. Signal Name: RDAT0 to RDAT7
Signal Description: Receive Data Inputs
Signal Type: Input RDAT0. Receive serial data/receive data bit 0 in nibble and byte mode
RDAT1. Receive data bit 1 in nibble and byte mode RDAT2. Receive data bit 2 in nibble and byte mode
RDAT3. Receive data bit 3 in nibble and byte mode
RDAT4. Receive data bit 4 in byte mode RDAT5. Receive data bit 5 in byte mode
RDAT6. Receive data bit 6 in byte mode RDAT7. Receive data bit 7 in byte mode
Signal Name: A0 to A3 Signal Description: Address Inputs
Signal Type: Input Address bus for addressing the control registers.
Signal Name: CS Signal Description: Chip Select
Signal Type: Input Active-low signal. Must be low to read or write to the part.
Signal Name: RD Signal Description: Read Strobe
Signal Type: Input Active-low signal. Must be low to read from the part.
Signal Name: WR Signal Description: Write Strobe
Signal Type: Input Active-low signal. Must be low to write to the part.
Signal Name: TEST Signal Description: TEST Input
DS2174
Signal Name: TEST
Signal Description: TEST Input Signal Type: Input (with internal 10k pullup)
Test Input. Should be left floating or held high.
Signal Name: TCLK
Signal Description: Transmit Clock Signal Type: Input
Transmit Clock Input. Up to a 155MHz clock to operate the transmit circuit. Data is output at TDATn and is updated on the rising edge of TCLK.
Signal Name: TCLK_EN Signal Description: Transmit Clock Enable
Signal Type: Input Gaps the TCLK input to the transmit circuit.
Signal Name: TCLKO Signal Description: TCLK Output
Signal Type: Output Output of the TCLK gapping circuit. Gapped by TCLK_EN.
Signal Name: TDAT0 to TDAT7 Signal Description: Transmit Data Outputs
Signal Type: Output
TDAT0. Transmit serial data/receive data bit 0 in nibble and byte mode
TDAT1.Transmit data bit 1 in nibble and byte mode
TDAT2. Transmit data bit 2 in nibble and byte mode TDAT3. Transmit data bit 3 in nibble and byte mode
TDAT4. Transmit data bit 4 in byte mode
TDAT5. Transmit data bit 5 in byte mode
TDAT6. Transmit data bit 6 in byte mode
TDAT7. Transmit data bit 7 in byte mode
Signal Name: D0 to D7
Signal Description: Data I/O
Signal Type: I/O
Parallel data pins.
DS2174
2. PARALLEL CONTROL INTERFACE
Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the
address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is accessed indirectly. RCLK and TCLK are used to update counters and for all rising edge bits in the
register map (RSYNC, LC, TL, SBE). At slow clock rates, sufficient time must be allowed for these port operations.
Table 2-1. REGISTER MAP
DS2174
3. CONTROL REGISTERS Control Register 1 (Address = 0h)
(MSB) (LSB)
DS2174 Control Register 2 (Address = 1h) (MSB) (LSB)
