DS2174Q+ ,EBERTAPPLICATIONS Software-programmable bit error insertion Routers Fully independent transmit and re ..
DS2174QN ,EBERTfeatures bit-serial, nibble-parallel, and byte-parallel data interfaces, and ngenerates and uniquel ..
DS2174QN+ ,EBERTPIN DESCRIPTION .82. PARALLEL CONTROL INTERFACE.......103. CONTROL REGISTERS ...113.1 MODE SELECT . ..
DS2175 ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
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DS2176 ,T1 Receive BufferPIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 I Signaling Inhibit. When low, ABCD signaling u ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
DS2174Q+-DS2174QN+
EBERT
GENERAL DESCRIPTIONThe DS2174 enhanced bit error-rate tester
(EBERT) is a software-programmable test-pattern
generator, receiver, and analyzer capable of
meeting the most stringent error-performance
requirements of digital transmission facilities. It
features bit-serial, nibble-parallel, and byte-
parallel data interfaces, and generates and
uniquely synchronizes to pseudorandom patterns
of the form 2n - 1, where n can take on values from
1 to 32, and user-defined repetitive patterns of any
length up to 512 octets.
APPLICATIONSRoutersChannel Service Units (CSUs)Data Service Units (DSUs)MuxesSwitchesDigital-to-Analog Converters (DACs)CPE EquipmentBridgesSmart Jack
PIN CONFIGURATION
FEATURESGenerates and detects digital patterns for
analyzing and trouble-shooting digital
communications systemsProgrammable polynomial length and
feedback taps for generation of any
pseudorandom patterns up to 232 - 1; up to
32 taps can be used in the feedback pathProgrammable, user-defined pattern
registers for long repetitive patterns up to
512 bytes in lengthLarge 48-bit count and bit error count
registersSoftware-programmable bit error insertionFully independent transmit and receive
paths8-bit parallel-control portDetects polynomial test patterns in the
presence of bit error rates up to 10-2Programmable for serial, 4-bit parallel, or
8-bit parallel data interfacesSerial mode clock rate is 155MHz; byte
mode is 80MHz for a net 622Mbps; OC-3Available in 44-pin PLCC
ORDERING INFORMATION
PARTTEMP
RANGE
PIN-
PACKAGEDS2174Q0°C to +70°C44 PLCC
DS2174QN-40°C to +85°C44 PLCC
DS2174
EBERT192021222324252627285432143424140
TDAT7
TDAT6
GND
TDAT5
TDAT4
TDAT3
TDAT2
GND
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
GND
VDDD7D6D5D4D3
GNDVDD
DAT
DAT
DS2174TOP VIEW
DS2174
TABLE OF CONTENTSGENERAL OPERATION................................................................................................................41.1PATTERN GENERATION......................................................................................................................4
1.1.1Polynomial Generation..........................................................................................4
1.1.2Repetitive Pattern Generation...............................................................................4
1.2PATTERN SYNCHRONIZATION............................................................................................................5
1.2.1Synchronization......................................................................................................5
1.2.2Polynomial Synchronization..................................................................................5
1.2.3Repetitive Pattern Synchronization.......................................................................5
1.3BIT ERROR RATE (BER) CALCULATION............................................................................................5
1.3.1Counters.................................................................................................................5
1.4GENERATING ERRORS.......................................................................................................................5
1.5CLOCK DISCUSSION...........................................................................................................................6
1.6POWER-UP SEQUENCE.......................................................................................................................6
1.7DETAILED PIN DESCRIPTION.............................................................................................................8
PARALLEL CONTROL INTERFACE........................................................................................10CONTROL REGISTERS...............................................................................................................113.1MODE SELECT.................................................................................................................................13
3.1.1Error Insertion.....................................................................................................13
3.2STATUS REGISTER...........................................................................................................................15
3.3PSEUDORANDOM PATTERN REGISTERS...........................................................................................15
3.4TEST REGISTER................................................................................................................................17
3.5COUNT REGISTERS..........................................................................................................................17
RAM ACCESS.................................................................................................................................184.1INDIRECT ADDRESSING....................................................................................................................18
DC OPERATION............................................................................................................................19AC TIMING CHARACTERISTICS.............................................................................................206.1PARALLEL PORT..............................................................................................................................20
6.2DATA INTERFACE............................................................................................................................22
MECHANICAL DIMENSIONS....................................................................................................24
DS2174
LIST OF FIGURES
FIGURE 1-1. BLOCK DIAGRAM..............................................................................................................6
FIGURE 6-1. READ TIMING...................................................................................................................20
FIGURE 6-2. WRITE TIMING..................................................................................................................21
FIGURE 6-3. TRANSMIT INTERFACE TIMING...................................................................................22
FIGURE 6-4. RECEIVE INTERFACE TIMING......................................................................................23
LIST OF TABLES
TABLE 1-A. PIN ASSIGNMENT...............................................................................................................7
TABLE 2-A. REGISTER MAP.................................................................................................................10
TABLE 3-A. MODE SELECT...................................................................................................................13
TABLE 3-B. ERROR BIT INSERTION....................................................................................................13
TABLE 3-C. PSEUDORANDOM PATTERN GENERATION...............................................................16
TABLE 5-A. RECOMMENDED DC OPERATING CONDITIONS.......................................................19
TABLE 5-B. DC CHARACTERISTICS...................................................................................................19
TABLE 6-A. PARALLEL PORT READ TIMING...................................................................................20
TABLE 6-B. PARALLEL PORT WRITE TIMING..................................................................................21
TABLE 6-C. TRANSMIT DATA TIMING...............................................................................................22
TABLE 6-D. RECEIVE DATA TIMING..................................................................................................23
DS2174
1. GENERAL OPERATION
1.1 Pattern Generation
1.1.1 Polynomial Generation
The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path
of the polynomial generator. It also features a seed register that can be used to preload the polynomial
generator with a seed value. This is done on the rising edge of TL in Control Register 1.
The DS2174 generates polynomial patterns of any length up to and including 232 - 1. All of the industry-
standard polynomials can be programmed using the control registers. The polynomial is generated using a
shift register of programmable length and programmable feedback tap positions. The user has access to
all combinations of pattern length and pattern tap location to generate industry-standard polynomials or
other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the
polynomial 220 – 1. This pattern has the additional requirement that “an output bit is forced to a 1
whenever the next 14 bits are 0.” Setting the QRSS bit in Control Register 1 causes the pattern generator
to enforce this rule.
1.1.2 Repetitive Pattern Generation
In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The
programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through
PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is
addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in
the memory.
Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to
store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8
bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that
the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is
used in serial mode: a 5-bit pattern is written to memory 5 times. For example,
To generate a 00001 pattern at the serial output, write these bytes to memory:
RAM ADDRESSBINARY CODEHEX CODE
00h0001000010h
01h0100001042h
02h0000100008h
03h0010000121h
04h1000010084h
DS2174
1.2 Pattern Synchronization
1.2.1 Synchronization
The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free
when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to
declare loss-of-pattern sync, set the RLOS bit, and the synchronizer comes back online.
1.2.2 Polynomial Synchronization
Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte
mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit
that does not match the polynomial is counted as a bit error.
1.2.3 Repetitive Pattern Synchronization
Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The
actual sync time depends on the nature of the pattern and the location of the synchronization pointer.
Errors that occur during synchronization could affect the sync time; at least one complete error-free
repetition must be received before synchronization is declared. Once synchronized, any bit that does not
match the pattern that is programmed in the on-board RAM is counted as a bit error.
1.3 Bit Error Rate (BER) Calculation
1.3.1 Counters
The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has
large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,
and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but
at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.
To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the
contents into the count registers. At T = 0, these results should be ignored. At this point, the device is
counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and
reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit
counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied
by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cycles
have to be accumulated in software.
1.4 Generating Errors
Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted
data stream. Injecting errors allows users to stress communication links and to check the functionality of
error monitoring equipment along the path.
DS2174
1.5 Clock Discussion
There are two methods for moving test patterns through a telecom network.
1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The
gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn
outputs remain active during clock gaps.
2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the
TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.
TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at
the level of the last bit transmitted (output high for a 1, output low for a 0).
1.6 Power-Up Sequence
On power-up, the registers in the DS2174 are in a random state. The user must program all the internal
registers to a known state before proper operation can be ensured.
Figure 1-1. Block Diagram
BIT COUNTER
ERROR COUNTER
PATTERN DETECTOR
ERROR INSERTION
PBACK M
REPETITIVE PATTERN
GENERATORn - 1
PARALLEL CONTROL PORT
RECEIVE
RATE
CONTROL
TRANSMIT
RATE
CONTROL
D[7:0]CSRDWRA[3:0]
RDAT[7:0]
TCLK0
TDAT[7:0]
TCLK
TCLK_EN
RCLK_EN
RCLKSYNC
CR1.5
CR1.0
DS2174
Table 1-A. Pin Assignment
PINSYMBOLI/OFUNCTION
1, 23VDD—SupplyRCLKIReceive ClockRCLK_ENIReceive Clock EnableRDAT0IReceive Serial Data or LSB of Receive Nibble or Byte DataRDAT1IReceive Data Nibble or ByteRDAT2IReceive Data Nibble or ByteRDAT3IReceive Data Nibble or ByteRDAT4IReceive Data ByteRDAT5IReceive Data ByteRDAT6IReceive Data ByteRDAT7IReceive Data Byte
12, 22, 29,GND—GroundA0IAddress 0A1IAddress 1A2IAddress 2A3IAddress 3CSIChip SelectRDIReadWRIWrite
20, 21TESTITest InputTCLKITransmit Clock InputTCLK_ENITransmit Clock EnableTCLKOO
Transmit Clock Output. This is active only when data is being transmitted.
This clock has gapped periods corresponding to the times when the
transmit enable signal is low.TDAT0OTransmit Serial Data or LSB of Transmit Nibble or Byte DataTDAT1OTransmit Data Nibble or ByteTDAT2OTransmit Data Nibble or ByteTDAT3OTransmit Data Nibble or ByteTDAT4OTransmit Data ByteTDAT5OTransmit Data ByteTDAT6OTransmit Data ByteTDAT7OTransmit Data ByteD0I/OData I/OD1I/OData I/OD2I/OData I/OD3I/OData I/OD4I/OData I/OD5I/OData I/OD6I/OData I/OD7I/OData I/O
DS2174
1.7 Detailed Pin Description
Signal Name:RCLK
Signal Description:Receive Clock
Signal Type:Input
Receive clock input. Up to a 155MHz clock to operate the receive circuit. Input data at RDATn is
sampled on the rising edge of RCLK.
Signal Name:RCLK_EN
Signal Description:Receive Clock Enable
Signal Type:Input
Gaps the RCLK input to the receive circuit.
Signal Name:RDAT0 to RDAT7
Signal Description:Receive Data Inputs
Signal Type:Input
RDAT0. Receive serial data/receive data bit 0 in nibble and byte mode
RDAT1. Receive data bit 1 in nibble and byte mode
RDAT2. Receive data bit 2 in nibble and byte mode
RDAT3. Receive data bit 3 in nibble and byte mode
RDAT4. Receive data bit 4 in byte mode
RDAT5. Receive data bit 5 in byte mode
RDAT6. Receive data bit 6 in byte mode
RDAT7. Receive data bit 7 in byte mode
Signal Name:A0 to A3
Signal Description:Address Inputs
Signal Type:Input
Address bus for addressing the control registers.
Signal Name:CS
Signal Description:Chip Select
Signal Type:Input
Active-low signal. Must be low to read or write to the part.
Signal Name:RD
Signal Description:Read Strobe
Signal Type:Input
Active-low signal. Must be low to read from the part.
Signal Name:WR
Signal Description:Write Strobe
Signal Type:Input
Active-low signal. Must be low to write to the part.
Signal Name:TEST
Signal Description:TEST Input
DS2174
Signal Name:TEST
Signal Description:TEST Input
Signal Type:Input (with internal 10kΩ pullup)
Test Input. Should be left floating or held high.
Signal Name:TCLK
Signal Description:Transmit Clock
Signal Type:Input
Transmit Clock Input. Up to a 155MHz clock to operate the transmit circuit. Data is output at TDATn
and is updated on the rising edge of TCLK.
Signal Name:TCLK_EN
Signal Description:Transmit Clock Enable
Signal Type:Input
Gaps the TCLK input to the transmit circuit.
Signal Name:TCLKO
Signal Description:TCLK Output
Signal Type:Output
Output of the TCLK gapping circuit. Gapped by TCLK_EN.
Signal Name:TDAT0 to TDAT7
Signal Description:Transmit Data Outputs
Signal Type:Output
TDAT0. Transmit serial data/receive data bit 0 in nibble and byte mode
TDAT1.Transmit data bit 1 in nibble and byte mode
TDAT2. Transmit data bit 2 in nibble and byte mode
TDAT3. Transmit data bit 3 in nibble and byte mode
TDAT4. Transmit data bit 4 in byte mode
TDAT5. Transmit data bit 5 in byte mode
TDAT6. Transmit data bit 6 in byte mode
TDAT7. Transmit data bit 7 in byte mode
Signal Name:D0 to D7
Signal Description:Data I/O
Signal Type:I/O
Parallel data pins.
DS2174
2. PARALLEL CONTROL INTERFACE
Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the
address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is
accessed indirectly. RCLK and TCLK are used to update counters and for all rising edge bits in the
register map (RSYNC, LC, TL, SBE). At slow clock rates, sufficient time must be allowed for these port
operations.
Table 2-A. Register Map
ADDRESSR/WREGISTER NAMER/WControl Register 1R/WControl Register 2R/WControl Register 3R/WControl Register 4RStatus RegisterR/WTap/Seed Register 0R/WTap/Seed Register 1R/WTap/Seed Register 2R/WTap/Seed Register 3R/WTEST RegisterRCount Register 0RCount Register 1RCount Register 2RCount Register 3RCount Register 4RCount Register 5
DS2174
3. CONTROL REGISTERS
Control Register 1 (Address = 0h)
(MSB)(LSB)
SYNCERSYNCLCLPBKQRSSPSLSBTL
SYMBOLFUNCTION
SYNCE
SYNC Enable
0 = Auto resync enabled
1 = Auto resync disabled
RSYNCInitiate Manual Resync Process. A rising edge causes the device to go
out of sync and begin resynchronization process.
Latch Count Registers. A rising edge copies the bit count and bit error
count accumulators to the appropriate registers. The accumulators are
then cleared.
LPBK
Transmit/Receive Loopback Select
0 = Loopback disabled
1 = Loopback enabled
QRSS
Zero Suppression Select. Forces a 1 into the pattern whenever the next
14 bit positions are all 0’s. Should only be set when using the QRSS
pattern.
0 = Disable 14 zero suppression
1 = Enable 14 zero suppression per T1.403
Pattern Select
0 = Pseudorandom pattern
1 = Repetitive pattern
LSB
LSB/MSB
0 = Repetitive pattern data is transmitted/received MSB first
1 = Repetitive pattern data is transmitted/received LSB firstTransmit Load. A rising edge causes the transmit shift register to be
loaded with the seed value.
DS2174
Control Register 2 (Address = 1h)
(MSB)(LSB)
MODE1MODE0TINVRINVSBEEIR2EIR1EIR0
SYMBOLFUNCTION
MODE1Mode Select Bit 1 (Table 3-A)
MODE0Mode Select Bit 0 (Table 3-A)
TINV
Transmit Data Inversion Select
0 = Do not invert outbound data
1 = Invert outbound data
RINV
Receive Data Inversion Select
0 = Do not invert inbound data
1 = Invert inbound data
SBESingle Bit Error Insert. A rising edge causes the device to insert a single error in
the outbound data. Must be cleared by the user.
EIR2Error Insert Bit 2 (Table 3-B)
EIR1Error Insert Bit 1 (Table 3-B)
EIR0
Error Insert Bit 0 (Table 3-B)
