DS2172TN Fast Delivery |IC PHOENIX CO.,LIMITED

DS2172TN ,Bit Error Rate Tester (BERT)applications requiring gap clocking such as Fractional-T1,Switched-56, DDS, normal framing requirem ..
DS2172TN+ ,Bit Error Rate Tester (BERT)FEATURES PIN ASSIGNMENT Generates/Detects digital bit patterns foranalyzing, evaluating and troubl ..
DS2174Q ,EBERTFEATURES PIN ASSIGNMENT § Generates and detects digital patterns for analyzing and trouble-shootin ..
DS2174Q+ ,EBERTAPPLICATIONS Software-programmable bit error insertion Routers Fully independent transmit and re ..
DS2174QN ,EBERTfeatures bit-serial, nibble-parallel, and byte-parallel data interfaces, and ngenerates and uniquel ..
DS2174QN+ ,EBERTPIN DESCRIPTION .82. PARALLEL CONTROL INTERFACE.......103. CONTROL REGISTERS ...113.1 MODE SELECT . ..

DS2172TN
Bit Error Rate Tester (BERT)
FEATURESGenerates/Detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systemsOperates at speeds from DC to 52 MHzProgrammable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 26-1, 29-1, 211-1, 215-1, 220-1, 223-1,
and 232-1Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in lengthLarge 32-bit error count and bit count
registersSoftware programmable bit error insertionFully independent transmit and receive
sections8-bit parallel control portDetects test patterns with bit error rates up to10-2
PIN ASSIGNMENT
ORDERING INFORMATION
DS2172T(00 C to 700 C) DS2172TN(-400 C to + 850 C)
DESCRIPTION
The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates
ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns
required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the
loopback, run the test, check for errors, and finally deactivate the loopback.
The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, andcontrol interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up
to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,
Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the-1-7
DS2172
Bit Error Rate Tester (BERT)
AD0
AD1
TEST
VSS
AD2
AD3
AD4
RLOS
VSS
VDD
INT
WR(R/W)
BTS
RD(DS
ATA
RCLKRDI
RDA
DS2172
32-Pin TQFP
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
DS2172
1.0 GENERAL OPERATION
1.1 PATTERN GENERATION
The DS2172 is programmed to generate a particular test pattern by programming the following registers:Pattern Set Registers (PSR)Pattern Length Register (PLR)Polynomial Tap Register (PTR)- Pattern Control Register (PCR)Error Insertion Register (EIR)
Please see Tables 4 and 5 for examples of how to program these registers in order to generate some
standard test patterns. Once these registers are programmed, the user will then toggle the TL (TransmitLoad) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin
appearing at the TDATA pin.
1.2 PATTERN SYNCHRONIZATION
The DS2172 expects to receive the same pattern that it transmitted. The synchronizer examines the data at
RDATA and looks for characteristics of the transmitted pattern. The user can control the onboardsynchronizer with the Sync Enable and Resync bits in the Pattern Control Register.
In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined
in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all
0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified byusing the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are
received without error, where n is the exponent in the polynomial from table 4. Once in synchronization
(SR0. = 1) any deviation from this pattern will be counted by the Bit Error Count Register.
In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in
the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an
explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this
pattern will be counted by the Bit Error Count Register.
1.3 BER CALCULATIONUsers can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the
bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count
Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over
the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration
period.
1.4 GENERATING ERRORS
Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the
transmitted data stream. Injecting errors allows users to stress communication links and to check the
functionality of error monitoring equipment along the path.
1.5 POWER-UP SEQUENCE
DS2172
DS2172 FUNCTIONAL BLOCK DIAGRAM Figure 1
DS2172 PATTERN GENERATION BLOCK DIAGRAM Figure 2
NOTES:
1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern.
2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation.
DS2172
DETAILED PIN DESCRIPTION Table 1
DS2172
DS2172 REGISTER MAP Table 2
NOTE:
1. The Test Register must be set to 00 hex to insure proper operation of the DS2172.
DS2172
2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical
Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the addressinformation and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or WR pulses. In a read cycle, the DS2172 outputs a byte of data during the latter
portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can
also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update counters andload transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these
port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that isto be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB) (LSB)PSR3 (addr.=00 Hex)PSR2 (addr.=01 Hex)PSR1 (addr.=02 Hex)PSR0 (addr.=03 Hex)
4.0 PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
DS2172
PLR: PATTERN LENGTH REGISTER (Address=04 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONPLR1.7Not Assigned. Should be set to 0 when written to.PLR1.6Not Assigned. Should be set to 0 when written to.PLR1.5Not Assigned. Should be set to 0 when written to.
LB4PLR1.4Length Bit 4.
LB3PLR1.3Length Bit 3.
LB2PLR1.2Length Bit 2.
LB1PLR1.1Length Bit 1.
LB0PLR1.0Length Bit 0.
5.0 POLYNOMIAL TAP REGISTER
Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input of
the pattern generator. Feedback Tap B provides one of two feedback paths within the pattern generator.
Please refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for registerprogramming examples.
PTR: POLYNOMIAL TAP REGISTER (Address=05 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
-PTR.7Not Assigned. Should be set to 0 when written to.
-PTR.6Not Assigned. Should be set to 0 when written to.
-PTR.5Not Assigned. Should be set to 0 when written to.
PT4PTR.4Polynomial Tap Bit 4.
PT3PTR.3Polynomial Tap Bit 3.
PT2PTR.2Polynomial Tap Bit 2.
PT1PTR.1Polynomial Tap Bit 1.
DS2172
6.0 PATTERN CONTROL REGISTER
The Pattern Control Register (PCR) is used to configure the operating parameters of the DS2172 and to
control the patterns being generated and received. Also the PCR is used to control the pattern
synchronizer and the error and bit counters.
PCR: PATTERN CONTROL REGISTER (Address=06 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTIONPCR.7Transmit Load. A low to high transition loads the pattern
generator with the contents of the Pattern Set Registers. PCR.7 islogically ORed with the input pin TL. Must be cleared and set
again for subsequent loads.
QRSSPCR.6Zero Suppression Select. Forces a 1 into the pattern whenever
the next 14 bit positions are all 0s. Should only be set whenusing the QRSS pattern.
0 = Zero suppression disabled
1 = Zero suppression enabledPCR.5Pattern Select.0 = Repetitive Pattern
1 = Pseudorandom PatternPCR.4Latch Count Registers. A low to high transition latches the bit
and error counts into the user accessible registers BCR andBECR and clears the internal register count. PCR.4 is logically
OR’ed with input pin LC. Must be cleared and set again for
subsequent loads.PCR.3Receive Data Load. A transition from low to high loads theprevious 32 bits of data received at RDATA into the Pattern
Receive Registers (PRR). PCR.3 is logically OR’ed with input
pin RL. Must be cleared and set again for subsequent latches.
SYNCEPCR.2SYNC Enable.0 = auto resync is enabled.
1 = auto resync is disabled.
RESYNCPCR.1Initiate Manual Resync Process. A low to high transition will
force the DS2172 to resynchronize to the incoming pattern atRDATA. Must be cleared and set again for a subsequent resync.
LPBKPCR.0Transmit/Receive Loopback Select. When enabled, the
RDATA input is disabled; TDATA continues to output data as
normal. See Figure 1.
DS2172
7.0 ERROR INSERT REGISTER
The Error Insertion Register (EIR) controls circuitry within the DS2172 that allows the generated pattern
to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly
programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under microcontroller
control) via the EIR.3 bit.
EIR: ERROR INSERT REGISTER (Address=07 Hex)
(MSB) (LSB)
SYMBOLPOSITIONNAME AND DESCRIPTION
-EIR.7Not Assigned. Should be set to 0 when written to.
-EIR.6Not Assigned. Should be set to 0 when written to.
TINVEIR.5Transmit Data Inversion Select.
0 = do not invert data to be transmitted at TDATA
1 = invert data to be transmitted at TDATA
RINVEIR.4Receive Data Inversion Select.0 = do not invert data received at RDATA
1 = invert data received at RDATA
SBEEIR.3Single Bit Error Insert. A low to high transition will create a
single bit error. Must be cleared and set again for a subsequent
bit error to be inserted. Can be used to accomplish rates not
addressed in Table 3 (e.g., BER of less than 10-7).
EIB2EIR.2Error Insert Bit 2. See Table 3.
EIB1EIR.1Error Insert Bit 1. See Table 3.
EIB0EIR.0Error Insert Bit 0. See Table 3.
ERROR BIT INSERTION Table 3
DS2172
PSEUDORANDOM PATTERN GENERATION (PCR.5=1) Table 4
REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5
DS2172
NOTES FOR TABLES 4 AND 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 232 -1 pattern, the random pattern actually repeats every (4093 x 220) + 1046529 bits instead of32 - 1.
8.0 BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear theBCR by either toggling the LC bit or pin. The DS2172 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
BIT COUNT REGISTERS
(MSB) (LSB)BCR3 (addr.=08 Hex)BCR2 (addr.=09 Hex)BCR1 (addr.=0A Hex)BCR0 (addr.=0B Hex)
9.0 BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,the user must clear the BECR by either toggling the LC bit or pin. The DS2172 latches the bit error count
into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input
pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by an
external processor to compute the BER performance on a loop or channel basis.

Partno	Mfg	Dc	Qty	Available	Descript
DS2172TN	MAIXM	N/a	1500	avai	Bit Error Rate Tester (BERT)