DS2165QN ,16/24/32kbps ADPCM ProcessorFEATURES PIN ASSIGNMENT (Top View) Compresses/expands 64kbps PCM voiceto/from either 32kbps, 24kbp ..
DS2165QN+ ,16/24/32kbps ADPCM Processorapplications Single +5V supply; low-power CMOStechnology Available in 28-pin PLCC 3V operation v ..
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DS2165QN-DS2165QN+
16/24/32kbps ADPCM Processor
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
FEATURESCompresses/expands 64kbps PCM voice
to/from either 32kbps, 24kbps, or 16kbpsDual fully independent channel architecture;
device can be programmed to perform either:two expansionstwo compressionsone expansion and one compressionInterconnects directly to combo-codec
devicesInput to output delay is less than 375sSimple serial port used to configure the
deviceOn-board time-slot assigner-circuit (TSAC)
function allows data to be input/output at
various time slotsSupports Channel Associated SignalingEach channel can be independently idled or
placed into bypassAvailable hardware mode requires no host
processor; ideal for voice storage
applicationsSingle +5V supply; low-power CMOS
technologyAvailable in 28-pin PLCC3V operation version is available
(DS2165QL)
PIN ASSIGNMENT (Top View)
DESCRIPTIONThe DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been
optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three
different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)
either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT
Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression to
24kbps follows ANSI document T1.303. The compression to 16kbps follows a proprietary algorithm
developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on-the-fly. This
allows the user to make maximum use of the available bandwidth on a dynamic basis.
28-Pin PLCC
FSY
YOUT
SDI
SCLK
XOUTNC
TM1TM0RSVD
YINCLK
XIN
CLK
4 3 2 1 28 27 26
12 13 14 15 16 17 18
DS2165Q
16/24/32kbps ADPCM Processor
DS2165Q
DS2165Q
OVERVIEWThe DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two
independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)
backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz
master clock is required by the DSP engine. The DS2165Q can be configured to perform either two
expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces
support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for -law and
2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream
during a user-programmed input time slot, processes the data and outputs the result during a user-
programmed output time slot.
Each PCM interface has a control register that specifies functional characteristics (compress, expand,
bypass, and idle), data format (-law or A-law), and algorithm reset control. With the SPS pin strapped
high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a
novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying
system-level interconnect.
With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control
register bits to some of the address and serial port pins. Under the hardware mode, no external host
controller is required and all PCM/ADPCM input and output time slots default to time slot 0.
HARDWARE RESETRST allows the user to reset both channel algorithms and the contents of the internal registers. This pin
must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the
device has initialized properly. RST should also be asserted when changing to or from the hardware
mode. RST clears all bits of the control register for both channels except the IPD bits; the IPD bits for
both channels are set to 1.
SOFTWARE MODEConnecting SPS high enables the software mode. In this mode, an external host controller writes
configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and CS (Figure 2). Each
write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the
address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X
or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1
byte to set the input time slot and another byte to set the output time slot.
ADDRESS/COMMAND BYTEIn the software mode, the address/command byte is the first byte written to the serial port; it identifies
which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must
match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If
an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.
Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs
are tri-stated during register updates.
DS2165Q
CONTROL REGISTERThe control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PINSYMBOLTYPEFUNCTIONRSTI
Reset. A high-low-high transition resets the algorithm. The device should bereset on power-up and when changing to or from the hardware mode.
TM0
TM1I
Test Modes 0 and 1. Connect to VSS for normal operation.Address Select. A0 = LSB, A5 = MSB. Must match address/command wordto enable the serial port.SPSI
Serial Port Select. Connect to VDD to select the serial port; connect to VSS toselect the hardware mode.MCLKI
Master Clock. 10MHz clock for the ADPCM processing engine; may beasynchronous to SCLK, CLKX, and CLKY.VSS—
Signal Ground. 0VXINI
X Data In. Sampled on falling edge of CLKX during selected time slots.CLKXI
X Data Clock. Data clock for the X-side PCM interface; must besynchronous with FSX.FSXI
X Frame Sync. 8kHz frame sync for the X-side PCM interface.XOUTO
X Data Output. Updated on rising edge of CLKX during selected time slots.SCLKI
Serial Data Clock. Used to write to the serial port registers.SDII
Serial Data In. Data for on-board control registers; sampled on the risingedge of SCLK. LSB sent first.CSI
Chip Select. Must be low to write to the serial port.YOUTO
Y Data Output. Updated on rising edge of CLKY during selected time slots.FSYI
Y Frame Sync. 8kHz frame sync for the Y-side PCM interface.CLKYI
Y Data Clock. Data clock for the Y-side PCM interface; must besynchronous with FSY.YINI
Y Data In. Sampled on falling edge of CLKY during selected time slots.VDD—
Positive Supply. 5.0V (3.0V for DS2165QL)
DS2165Q
Figure 1. BLOCK DIAGRAM
Figure 2. SERIAL PORT WRITE
Note: A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or
compression occurs. Bypass operates on bytewide (8 bits) slots when CP/EX is set and on nibble-wide
(4 bits) slots when CP/EX is cleared.
A-law (U/A = 0) and -law (U/A = 1) PCM coding is independently selected for the X and Y channels
by CR.2. If BYP and IPD are cleared, then CP/EX determines if the input data is to be compressed or
expanded.
DS2165Q
Figure 3. ADDRESS/COMMAND BYTE
(MSB) (LSB)X/YA5A4A3A2A1A0
SYMBOLPOSITIONFUNCTIONACB.7Reserved. Must be 0 for proper operationYACB.6
X/Y Channel Select
0 = update channel Y characteristics
1 = update channel X characteristicsACB.5MSB of device addressACB.4—ACB.3—ACB.2—ACB.1—ACB.0LSB of device address
Figure 4. CONTROL REGISTER
(MSB) (LSB)
AS0AS1IPDALRSTBYPU/AAS2CP/EX
SYMBOLPOSITIONFUNCTION
AS0CR.7Algorithm Select 0 (Table 2)
AS1CR.6Algorithm Select 1 (Table 2)
IPDCR.5
Idle and Power-Down
0 = channel enabled
1 = channel disabled (output tri-stated)
ALRSTCR.4
Algorithm Reset
0 = normal operation
1 = reset algorithm for selected channel
BYPCR.3
Bypass
0 = normal operation
1 = bypass selected channelACR.2
Data Format
0 = A-law
1 = -law
AS2CR.1Algorithm Select 2 (Table 2)
CP/EXCR.0
Channel Coding
0 = expand (decode) selected channel
DS2165Q
Table 2. ALGORITHM SELECT BITS
ALGORITHM SELECTEDAS2AS1AS0
64kbps to/from 32kbps000
64kbps to/from 24kbps111
64kbps to/from 16kbps101
Figure 5. INPUT TIME SLOT REGISTER
(MSB) (LSB)—-D5D4D3D2D1D0
SYMBOLPOSITIONFUNCTIONITR.7Reserved. Must be 0 for proper operationITR.6Reserved. Must be 0 for proper operationITR.5MSB of input time slot registerITR.4—ITR.3—ITR.2—ITR.1—ITR.0LSB of input time slot register
Figure 6. OUTPUT TIME SLOT REGISTER
(MSB) (LSB)—D5D4D3D2D1D0
SYMBOLPOSITIONFUNCTIONOTR.7Reserved. Must be 0 for proper operationOTR.6Reserved. Must be 0 for proper operationOTR.5MSB of output time slot registerOTR.4—OTR.3—OTR.2—OTR.1—
DS2165Q
TIME SLOT ASSIGNMENT/ORGANIZATION
On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the
time slot registers. Time slot size (number of bits wide) is determined by the state of CP/EX. The number
of time slots available is determined by the state of both CP/EX and U/A (Figures 7 through 10). For
example, if the X channel is set to compress (CP/EX = 1) and it is set to expect -law data
(U/A = 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up
for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected.
Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.
Figure 7. -LAW PCM INTERFACE
Figure 8. -LAW ADPCM INTERFACE
DS2165Q
Figure 9. A-LAW PCM INTERFACE
Figure 10. A-LAW ADPCM INTERFACE
DS2165Q
HARDWARE MODE
The hardware mode is intended for applications that do not have an external controller available or do not
require the extended features offered by the serial port. Connecting the SPS pin to VSS disables the serial
port, clears all internal register bits, and maps the IPD, U/A, and CP/EX bits for both channels to external
bits (Table 3). In the hardware mode, both the input and output time slots default to time slot 0.
Table 3. HARDWARE MODE
PINNAMEREGISTER LOCATIONFUNCTION
6A0CP/EX
(Channel X)
Channel X Coding Configuration
0 = Expand
1 = Compress
7A1AS0/AS1/AS2
(Channel X and Y)Algorithm Select (Table 4)
8A2U/A
(Channel X)
Channel X Data Format
0 = A-law
1 = -law
9A3CP/EX
(Channel Y)
Channel Y Coding Configuration
0 = Expand
1 = CompressA4AS0/AS1/AS2
(Channel X and Y)Algorithm Select (Table 4)A5U/A
(Channel Y)
Channel Y Data Format
0 = A-law
1 = -lawSDIIPD
(Channel Y)
Channel Y Idle Select
0 = Channel Active
1 = Channel IdleCSIPD
(Channel X)
Channel X Idle Select
0 = Channel Active
1 = Channel Idle
NOTES:
1) SCLK must be connected to VSS when the hardware mode is selected.
2) When both channels are idled, power consumption is significantly reduced.
3) The NIL powers up within 800ms after either channel is returned to active from an idle state.
