DS2156LN+ ,T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II InterfaceFEATURES The DS2156 is a software-selectable T1, E1, or J1 Complete T1/DS1/ISDN-PRI/J1 Transceiver ..
DS21600 ,Clock Rate AdapterFEATURES The DS21600/DS21602/DS21604 are multiple-rate Direct Drop-In Replacement for LXP600ASE, ..
DS21600N ,3.3 V/5 V clock rate adapterPin Description PIN NAME TYPE FUNCTION DIP SO 1, 3, 6, 8, 10, N.C. No Connect 11, 13, 15 Synchr ..
DS21600N ,3.3 V/5 V clock rate adapterFEATURES The DS21600/DS21602/DS21604 are multiple-rate Direct Drop-In Replacement for LXP600ASE, ..
DS21600N+ ,3.3V/5V Clock Rate AdapterPin Description...3 Table 1-B. Pin Name Cross-Reference to LXP60x..3 Table 2-A. Frequency Conversio ..
DS21600SN ,3.3 V/5 V clock rate adapterBlock Diagram........3 Figure 3-1. Nominal Jitter Transer for 2.048MHz to 1.544MHz Conversion ..... ..
DS2156L+-DS2156LN+
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
GENERAL DESCRIPTION The DS2156 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The backplane is user-
configurable for a TDM or UTOPIA II bus interface.
The DS2156 is composed of a line interface unit
(LIU), framer, HDLC controllers, and a
UTOPIA/TDM backplane interface, and is controlled
by an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS2156 is pin and
software compatible with the DS2155.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω
coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS Inverse Mux ATM (IMA)
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
FEATURES � Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality � Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality � User-Selectable TDM or UTOPIA II Bus
Interface � Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping � CMI Coder/Decoder for Optical I/F � Crystal-Less Jitter Attenuator � Fully Independent Transmit and Receive
Functionality � Dual HDLC Controllers � Programmable BERT Generator and Detector � Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75Ω/100Ω/120Ω T1 and E1 Interfaces � Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz � 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued in Section 1.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2156L 0°C to +70°C 100 LQFP
DS2156L+ 0°C to +70°C 100 LQFP
DS2156LN -40°C to +85°C 100 LQFP
DS2156LN+ -40°C to +85°C 100 LQFP
DS2156G 0°C to +70°C 100 CSBGA
DS2156G+ 0°C to +70°C 100 CSBGA
DS2156GN -40°C to +85°C 100 CSBGA
DS2156GN+-40°C to +85°C 100 CSBGA
+Denotes lead-free/RoHS-compliant package.
DS2156
T1/E1/J1 Single-Chip Transceiver
TDM/UTOPIA II Interface
DS2156
T1/E1/J1
TDM/UTOPIA T1/E1/J1
NETWORK
BACKPLANE
UTOPIA
TDM
DS2156
TABLE OF CONTENTS
1. MAIN FEATURES............................................................................................................9
2. DETAILED DESCRIPTION............................................................................................12 2.1 BLOCK DIAGRAM........................................................................................................................14
3. PIN FUNCTION DESCRIPTION....................................................................................20 3.1 TDM BACKPLANE......................................................................................................................20
3.1.1 Transmit Side.......................................................................................................................................20
3.1.2 Receive Side........................................................................................................................................23
3.2 UTOPIA BUS............................................................................................................................26
3.2.1 Receive Side........................................................................................................................................26
3.2.2 Transmit Side.......................................................................................................................................27
3.3 PARALLEL CONTROL PORT PINS................................................................................................28
3.4 EXTENDED SYSTEM INFORMATION BUS......................................................................................29
3.5 USER OUTPUT PORT PINS.........................................................................................................30
3.6 JTAG TEST ACCESS PORT PINS................................................................................................31
3.7 LINE INTERFACE PINS................................................................................................................32
3.8 SUPPLY PINS.............................................................................................................................33
3.9 L AND G PACKAGE PINOUT........................................................................................................34
3.10 10MM CSBGA PIN CONFIGURATION..........................................................................................38
4. PARALLEL PORT.........................................................................................................39 4.1 REGISTER MAP..........................................................................................................................39
4.2 UTOPIA BUS REGISTERS..........................................................................................................45
5. SPECIAL PER-CHANNEL REGISTER OPERATION...................................................46
6. PROGRAMMING MODEL.............................................................................................48 6.1 POWER-UP SEQUENCE..............................................................................................................49
6.1.1 Master Mode Register..........................................................................................................................49
6.2 INTERRUPT HANDLING...............................................................................................................50
6.3 STATUS REGISTERS...................................................................................................................50
6.4 INFORMATION REGISTERS..........................................................................................................51
6.5 INTERRUPT INFORMATION REGISTERS........................................................................................51
7. CLOCK MAP..................................................................................................................52
8. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS...........................53 8.1 T1 CONTROL REGISTERS...........................................................................................................53
8.2 T1 TRANSMIT TRANSPARENCY...................................................................................................58
8.3 AIS-CI AND RAI-CI GENERATION AND DETECTION.....................................................................58
8.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.........................................................59
9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS...........................62 9.1 E1 CONTROL REGISTERS..........................................................................................................62
9.2 AUTOMATIC ALARM GENERATION...............................................................................................66
9.3 E1 INFORMATION REGISTERS....................................................................................................67
10. COMMON CONTROL AND STATUS REGISTERS......................................................69 10.1 T1/E1 STATUS REGISTERS........................................................................................................70
11. I/O PIN CONFIGURATION OPTIONS...........................................................................76
12. LOOPBACK CONFIGURATION....................................................................................78 12.1 PER-CHANNEL LOOPBACK.........................................................................................................80
13. ERROR COUNT REGISTERS.......................................................................................82 13.1 LINE-CODE VIOLATION COUNT REGISTER (LCVCR)...................................................................83
13.1.1 T1 Operation........................................................................................................................................83
DS2156
13.2.1 T1 Operation........................................................................................................................................85
13.2.2 E1 Operation........................................................................................................................................85
13.3 FRAMES OUT-OF-SYNC COUNT REGISTER (FOSCR)..................................................................86
13.3.1 T1 Operation........................................................................................................................................86
13.3.2 E1 Operation........................................................................................................................................86
13.4 E-BIT COUNTER (EBCR)...........................................................................................................87
14. DS0 MONITORING FUNCTION.....................................................................................88
15. SIGNALING OPERATION.............................................................................................90 15.1 RECEIVE SIGNALING..................................................................................................................90
15.1.1 Processor-Based Signaling..................................................................................................................90
15.1.2 Hardware-Based Receive Signaling....................................................................................................91
15.2 TRANSMIT SIGNALING................................................................................................................96
15.2.1 Processor-Based Mode.......................................................................................................................96
15.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode........................................................100
15.2.3 Software Signaling Insertion-Enable Registers, T1 Mode.................................................................102
15.2.4 Hardware-Based Mode......................................................................................................................102
16. PER-CHANNEL IDLE CODE GENERATION..............................................................103 16.1 IDLE-CODE PROGRAMMING EXAMPLES.....................................................................................104
17. CHANNEL BLOCKING REGISTERS..........................................................................108
18. ELASTIC STORES OPERATION................................................................................111 18.1 RECEIVE SIDE.........................................................................................................................114
18.1.1 T1 Mode.............................................................................................................................................114
18.1.2 E1 Mode.............................................................................................................................................114
18.2 TRANSMIT SIDE.......................................................................................................................114
18.2.1 T1 Mode.............................................................................................................................................115
18.2.2 E1 Mode.............................................................................................................................................115
18.3 ELASTIC STORES INITIALIZATION..............................................................................................115
18.4 MINIMUM DELAY MODE............................................................................................................115
19. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)..................................116
20. T1 BIT-ORIENTED CODE (BOC) CONTROLLER......................................................117 20.1 TRANSMIT BOC.......................................................................................................................117
Transmit a BOC................................................................................................................................................117
20.2 RECEIVE BOC.........................................................................................................................117
Receive a BOC.................................................................................................................................................117
21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)..........120 21.1 METHOD 1: HARDWARE SCHEME.............................................................................................120
21.2 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME......................................120
21.3 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................123
22. HDLC CONTROLLERS...............................................................................................133 22.1 BASIC OPERATION DETAILS.....................................................................................................133
22.2 HDLC CONFIGURATION...........................................................................................................133
22.2.1 FIFO Control......................................................................................................................................137
22.3 HDLC MAPPING......................................................................................................................138
22.3.1 Receive..............................................................................................................................................138
22.3.2 Transmit.............................................................................................................................................140
22.3.3 FIFO Information................................................................................................................................145
22.3.4 Receive Packet-Bytes Available........................................................................................................145
22.3.5 HDLC FIFOs......................................................................................................................................146
22.4 RECEIVE HDLC CODE EXAMPLE..............................................................................................147
22.5 LEGACY FDL SUPPORT (T1 MODE)..........................................................................................147
22.5.1 Overview............................................................................................................................................147
DS2156
22.6 D4/SLC-96 OPERATION..........................................................................................................149
23. LINE INTERFACE UNIT (LIU).....................................................................................150 23.1 LIU OPERATION......................................................................................................................150
23.2 RECEIVER...............................................................................................................................150
23.2.1 Receive Level Indicator and Threshold Interrupt...............................................................................151
23.2.2 Receive G.703 Synchronization Signal (E1 Mode)............................................................................151
23.2.3 Monitor Mode.....................................................................................................................................151
23.3 TRANSMITTER..........................................................................................................................152
23.3.1 Transmit Short-Circuit Detector/Limiter..............................................................................................152
23.3.2 Transmit Open-Circuit Detector.........................................................................................................152
23.3.3 Transmit BPV Error Insertion.............................................................................................................152
23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................152
23.4 MCLK PRESCALER..................................................................................................................153
23.5 JITTER ATTENUATOR...............................................................................................................153
23.6 CMI (CODE MARK INVERSION) OPTION....................................................................................153
23.7 LIU CONTROL REGISTERS.......................................................................................................154
23.8 RECOMMENDED CIRCUITS........................................................................................................161
23.9 COMPONENT SPECIFICATIONS..................................................................................................163
24. UTOPIA BACKPLANE INTERFACE...........................................................................168 24.1 DESCRIPTION..........................................................................................................................168
24.1.1 List of Applicable Standards..............................................................................................................168
24.1.2 Acronyms and Definitions..................................................................................................................168
24.2 UTOPIA CLOCK MODES..........................................................................................................169
24.3 FULL T1/E1 MODE AND CLEAR-CHANNEL E1 MODE.................................................................169
24.4 FRACTIONAL T1/E1 MODE........................................................................................................170
24.5 TRANSMIT OPERATION.............................................................................................................171
24.5.1 UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV.......................................................171
24.5.2 UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV)...................................................174
24.5.3 Transmit Processing..........................................................................................................................176
24.6 RECEIVE OPERATION...............................................................................................................177
24.6.1 Receive Processing...........................................................................................................................177
24.6.2 UTOPIA Side Receive: Muxed Mode with One Receive CLAV.........................................................179
24.6.3 UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV).....................................................180
24.7 REGISTER DEFINITIONS...........................................................................................................182
24.8 RECEIVE FIFO OVERRUN........................................................................................................193
24.9 UTOPIA DIAGNOSTIC LOOPBACK............................................................................................193
25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION........194
26. BERT FUNCTION........................................................................................................201 26.1 STATUS...................................................................................................................................201
26.2 MAPPING.................................................................................................................................201
26.3 BERT REGISTER DESCRIPTIONS.............................................................................................203
26.4 BERT REPETITIVE PATTERN SET.............................................................................................207
26.5 BERT BIT COUNTER...............................................................................................................208
26.6 BERT ERROR COUNTER.........................................................................................................209
27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................211 27.1 NUMBER-OF-ERRORS REGISTERS............................................................................................213
27.1.1 Number-of-Errors Left Register..........................................................................................................214
28. INTERLEAVED PCM BUS OPERATION (IBO)...........................................................215 28.1 CHANNEL INTERLEAVE.............................................................................................................215
28.2 FRAME INTERLEAVE.................................................................................................................215
29. EXTENDED SYSTEM INFORMATION BUS (ESIB)....................................................218
DS2156
31.1 TDM BACKPLANE MODE..........................................................................................................222
31.2 UTOPIA BACKPLANE MODE....................................................................................................223
32. USER-PROGRAMMABLE OUTPUT PINS..................................................................224
33. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT................225 33.1 DESCRIPTION..........................................................................................................................225
33.2 INSTRUCTION REGISTER..........................................................................................................228
SAMPLE/PRELOAD.........................................................................................................................................229
BYPASS...........................................................................................................................................................229
EXTEST............................................................................................................................................................229
CLAMP.............................................................................................................................................................229
HIGHZ...............................................................................................................................................................229
IDCODE............................................................................................................................................................229
33.3 TEST REGISTERS.....................................................................................................................230
33.4 BOUNDARY SCAN REGISTER....................................................................................................230
33.5 BYPASS REGISTER..................................................................................................................230
33.6 IDENTIFICATION REGISTER.......................................................................................................230
34. FUNCTIONAL TIMING DIAGRAMS............................................................................234 34.1 T1 MODE................................................................................................................................234
34.2 E1 MODE................................................................................................................................239
35. OPERATING PARAMETERS......................................................................................248
36. AC TIMING PARAMETERS AND DIAGRAMS...........................................................250 36.1 MULTIPLEXED BUS AC CHARACTERISTICS................................................................................250
36.2 NONMULTIPLEXED BUS AC CHARACTERISTICS.........................................................................253
36.3 RECEIVE-SIDE AC CHARACTERISTICS......................................................................................256
36.4 TRANSMIT AC CHARACTERISTICS............................................................................................259
36.5 UTOPIA TRANSMIT AC CHARACTERISTICS..............................................................................262
36.6 UTOPIA RECEIVE AC CHARACTERISTICS................................................................................262
37. REVISION HISTORY...................................................................................................263
38. PACKAGE INFORMATION.........................................................................................264 38.1 100-PIN LQFP (56-G5002-000)..............................................................................................264
38.2 100-BALL CSBGA (56-G6008-001)........................................................................................265
