DS2155GNB+ ,T1/E1/J1 Single-Chip TransceiverFEATURES The DS2155 is a software-selectable T1, E1, or J1 Complete T1/DS1/ISDN-PRI/J1 Transceiver ..
DS2155GNC2 ,T1/E1/J1 Single-Chip TransceiverTABLE OF CONTENTS .......2 1.1 TABLE OF FIGURES .6 1.2 TABLE OF TABLES...7 2. DATA SHEET REVISION H ..
DS2155GNC2+ ,T1/E1/J1 Single-Chip TransceiverFeatures continued in Section 3.
DS2155L ,T1/E1/J1 single-chip transceiverFEATURES The DS2155 is a software-selectable T1, E1, or J1 Complete T1/DS1/ISDN-PRI/J1 Transceiver ..
DS2155L+ ,T1/E1/J1 Single-Chip TransceiverFUNCTIONAL DESCRIPTION ....13 3.2
DS2155LB ,T1/E1/J1 Single-Chip TransceiverFEATURES......10 3.1
DS2155GNB+-DS2155GNC2-DS2155GNC2+-DS2155L-DS2155L+-DS2155LB-DS2155LB+-DS2155LC2-DS2155LC2+-DS2155LNC2+
T1/E1/J1 Single-Chip Transceiver
GENERAL DESCRIPTION The DS2155 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The DS2155 is composed of a
line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled by
an 8-bit parallel port configured for Intel or Motorola
bus operations. The DS2155 is pin and software
compatible with the DS2156.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω
coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
FEATURES � Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality � Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality � Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping � CMI Coder/Decoder for Optical I/F � Crystal-Less Jitter Attenuator � Fully Independent Transmit and Receive
Functionality � Dual HDLC Controllers � Programmable BERT Generator and Detector � Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75Ω/100Ω/120Ω T1 and E1 Interfaces � Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz � 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued in Section 3.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2155L 0°C to +70°C 100 LQFP
DS2155L+ 0°C to +70°C 100 LQFP
DS2155LN -40°C to +85°C 100 LQFP
DS2155LN+ -40°C to +85°C 100 LQFP
DS2155G 0°C to +70°C 100 CSBGA
DS2155G+ 0°C to +70°C 100 CSBGA
DS2155GN -40°C to +85°C 100 CSBGA
DS2155GN -40°C to +85°C 100 CSBGA
+ Denotes a lead-free/RoHS-compliant package.
DS2155
T1/E1/J1 Single-Chip Transceiver
DS2155
T1/E1/J1
SCT T1/E1/J1
NETWORK
BACKPLANE
TDM
DS2155
1. TABLE OF CONTENTS
1. TABLE OF CONTENTS............................................................................................................................2 1.1 TABLE OF FIGURES........................................................................................................................................6
1.2 TABLE OF TABLES..........................................................................................................................................7
2. DATA SHEET REVISION HISTORY.....................................................................................................8
3. MAIN FEATURES....................................................................................................................................10 3.1 FUNCTIONAL DESCRIPTION.........................................................................................................................13
3.2 BLOCK DIAGRAM.........................................................................................................................................15
4. PIN FUNCTION DESCRIPTION...........................................................................................................19 4.1 TRANSMIT SIDE...........................................................................................................................................19
4.2 RECEIVE SIDE..............................................................................................................................................21
4.3 PARALLEL CONTROL PORT PINS.................................................................................................................24
4.4 EXTENDED SYSTEM INFORMATION BUS......................................................................................................25
4.5 USER OUTPUT PORT PINS............................................................................................................................26
4.6 JTAG TEST ACCESS PORT PINS...................................................................................................................27
4.7 LINE INTERFACE PINS..................................................................................................................................28
4.8 SUPPLY PINS................................................................................................................................................29
4.9 L AND G PACKAGE PINOUT.........................................................................................................................30
4.10 10MM CSBGA PIN CONFIGURATION......................................................................................................32
5. PARALLEL PORT...................................................................................................................................33 5.1 REGISTER MAP............................................................................................................................................33
6. PROGRAMMING MODEL.....................................................................................................................39 6.1 POWER-UP SEQUENCE.................................................................................................................................40
6.1.1 Master Mode Register.........................................................................................................................40
6.2 INTERRUPT HANDLING................................................................................................................................41
6.3 STATUS REGISTERS......................................................................................................................................41
6.4 INFORMATION REGISTERS...........................................................................................................................42
6.5 INTERRUPT INFORMATION REGISTERS........................................................................................................42
7. SPECIAL PER-CHANNEL REGISTER OPERATION.......................................................................43
8. CLOCK MAP............................................................................................................................................45
9. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................46 9.1 T1 CONTROL REGISTERS.............................................................................................................................46
9.2 T1 TRANSMIT TRANSPARENCY...................................................................................................................51
9.3 AIS-CI AND RAI-CI GENERATION AND DETECTION..................................................................................51
9.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.....................................................................52
10. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................55 10.1 E1 CONTROL REGISTERS.........................................................................................................................55
10.2 AUTOMATIC ALARM GENERATION.........................................................................................................59
10.3 E1 INFORMATION REGISTERS..................................................................................................................60
11. COMMON CONTROL AND STATUS REGISTERS..........................................................................62
DS2155
12. I/O PIN CONFIGURATION OPTIONS.................................................................................................69
13. LOOPBACK CONFIGURATION..........................................................................................................71 13.1 PER-CHANNEL LOOPBACK......................................................................................................................73
14. ERROR COUNT REGISTERS...............................................................................................................75 14.1 LINE-CODE VIOLATION COUNT REGISTER (LCVCR).............................................................................76
14.1.1 T1 Operation.......................................................................................................................................76
14.1.2 E1 Operation.......................................................................................................................................76
14.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR)............................................................................78
14.2.1 T1 Operation.......................................................................................................................................78
14.2.2 E1 Operation.......................................................................................................................................78
14.3 FRAMES OUT-OF-SYNC COUNT REGISTER (FOSCR)..............................................................................79
14.3.1 T1 Operation.......................................................................................................................................79
14.3.2 E1 Operation.......................................................................................................................................79
14.4 E-BIT COUNTER (EBCR).........................................................................................................................80
15. DS0 MONITORING FUNCTION...........................................................................................................81
16. SIGNALING OPERATION.....................................................................................................................83 16.1 RECEIVE SIGNALING...............................................................................................................................83
16.1.1 Processor-Based Signaling.................................................................................................................83
16.1.2 Hardware-Based Receive Signaling...................................................................................................84
16.2 TRANSMIT SIGNALING.............................................................................................................................89
16.2.1 Processor-Based Mode.......................................................................................................................89
16.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode..........................................................93
16.2.3 Software Signaling Insertion-Enable Registers, T1 Mode..................................................................95
16.2.4 Hardware-Based Mode.......................................................................................................................95
17. PER-CHANNEL IDLE CODE GENERATION....................................................................................96 17.1 IDLE-CODE PROGRAMMING EXAMPLES..................................................................................................97
18. CHANNEL BLOCKING REGISTERS................................................................................................101
19. ELASTIC STORES OPERATION........................................................................................................104 19.1 RECEIVE SIDE........................................................................................................................................107
19.1.1 T1 Mode............................................................................................................................................107
19.1.2 E1 Mode............................................................................................................................................107
19.2 TRANSMIT SIDE.....................................................................................................................................107
19.2.1 T1 Mode............................................................................................................................................108
19.2.2 E1 Mode............................................................................................................................................108
19.3 ELASTIC STORES INITIALIZATION.........................................................................................................108
19.4 MINIMUM DELAY MODE.......................................................................................................................108
20. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)...................................................109
21. T1 BIT-ORIENTED CODE (BOC) CONTROLLER..........................................................................110 21.1 TRANSMIT BOC.....................................................................................................................................110
Transmit a BOC..............................................................................................................................................110
21.2 RECEIVE BOC.......................................................................................................................................110
Receive a BOC.................................................................................................................................................110
DS2155
22.1 METHOD 1: HARDWARE SCHEME.........................................................................................................113
22.2 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME..............................................113
22.3 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME........................................116
23. HDLC CONTROLLERS........................................................................................................................126 23.1 BASIC OPERATION DETAILS..................................................................................................................126
23.2 HDLC CONFIGURATION........................................................................................................................126
23.2.1 FIFO Control....................................................................................................................................130
23.3 HDLC MAPPING....................................................................................................................................131
23.3.1 Receive..............................................................................................................................................131
23.3.2 Transmit............................................................................................................................................133
23.3.3 FIFO Information.............................................................................................................................138
23.3.4 Receive Packet-Bytes Available........................................................................................................138
23.3.5 HDLC FIFOs....................................................................................................................................139
23.4 RECEIVE HDLC CODE EXAMPLE..........................................................................................................140
23.5 LEGACY FDL SUPPORT (T1 MODE)......................................................................................................140
23.5.1 Overview...........................................................................................................................................140
23.5.2 Receive Section.................................................................................................................................140
23.5.3 Transmit Section...............................................................................................................................142
23.6 D4/SLC-96 OPERATION........................................................................................................................142
24. LINE INTERFACE UNIT (LIU)...........................................................................................................143 24.1 LIU OPERATION....................................................................................................................................143
24.2 RECEIVER..............................................................................................................................................143
24.2.1 Receive Level Indicator and Threshold Interrupt.............................................................................144
24.2.2 Receive G.703 Synchronization Signal (E1 Mode)...........................................................................144
24.2.3 Monitor Mode...................................................................................................................................144
24.3 TRANSMITTER.......................................................................................................................................145
24.3.1 Transmit Short-Circuit Detector/Limiter..........................................................................................145
24.3.2 Transmit Open-Circuit Detector.......................................................................................................145
24.3.3 Transmit BPV Error Insertion..........................................................................................................145
24.3.4 Transmit G.703 Synchronization Signal (E1 Mode).........................................................................145
24.4 MCLK PRESCALER...............................................................................................................................146
24.5 JITTER ATTENUATOR.............................................................................................................................146
24.6 CMI (CODE MARK INVERSION) OPTION...............................................................................................146
24.7 LIU CONTROL REGISTERS.....................................................................................................................147
24.8 RECOMMENDED CIRCUITS.....................................................................................................................156
24.9 COMPONENT SPECIFICATIONS...............................................................................................................158
25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................163
26. BERT FUNCTION..................................................................................................................................170 26.1 STATUS..................................................................................................................................................170
26.2 MAPPING...............................................................................................................................................170
26.3 BERT REGISTER DESCRIPTIONS...........................................................................................................172
26.4 BERT REPETITIVE PATTERN SET..........................................................................................................176
26.5 BERT BIT COUNTER.............................................................................................................................177
26.6 BERT ERROR COUNTER........................................................................................................................178
27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................................180 27.1 NUMBER-OF-ERRORS REGISTERS..........................................................................................................182
DS2155
28.1 CHANNEL INTERLEAVE.........................................................................................................................184
28.2 FRAME INTERLEAVE..............................................................................................................................184
29. EXTENDED SYSTEM INFORMATION BUS (ESIB).......................................................................187
30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER........................................................191
31. FRACTIONAL T1/E1 SUPPORT.........................................................................................................191
32. USER-PROGRAMMABLE OUTPUT PINS........................................................................................193
33. TRANSMIT FLOW DIAGRAMS.........................................................................................................194
34. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................199 34.1 DESCRIPTION.........................................................................................................................................199
34.2 INSTRUCTION REGISTER........................................................................................................................202
34.3 TEST REGISTERS....................................................................................................................................204
34.4 BOUNDARY SCAN REGISTER.................................................................................................................204
34.5 BYPASS REGISTER.................................................................................................................................204
34.6 IDENTIFICATION REGISTER....................................................................................................................204
35. FUNCTIONAL TIMING DIAGRAMS.................................................................................................208 35.1 T1 MODE...............................................................................................................................................208
35.2 E1 MODE...............................................................................................................................................213
36. OPERATING PARAMETERS..............................................................................................................222
37. AC TIMING PARAMETERS AND DIAGRAMS...............................................................................224 37.1 MULTIPLEXED BUS AC CHARACTERISTICS..........................................................................................224
37.2 NONMULTIPLEXED BUS AC CHARACTERISTICS...................................................................................227
37.3 RECEIVE-SIDE AC CHARACTERISTICS..................................................................................................230
37.4 BACKPLANE CLOCK TIMING: AC CHARACTERISTICS.........................................................................233
37.5 TRANSMIT AC CHARACTERISTICS........................................................................................................234
38. PACKAGE INFORMATION................................................................................................................237 38.1 100-PIN LQFP (56-G5002-000)............................................................................................................237
38.2 100-BALL CSBGA (56-G6008-001).....................................................................................................238
