DS2154L ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS1.0 INTRODUCTION.4New
DS2154L+ ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.6 1.1 INTRODUCTION ........6 1.1.1 New
DS2154LA2 ,Enhanced E1 Single Chip TransceiverApplications Fully Independent Transmit and Receive Functionality ORDERING INFORMATION Full Acce ..
DS2154LA2+ ,Enhanced E1 Single Chip TransceiverFEATURES PIN CONFIGURATION Complete E1 (CEPT) PCM-30/ISDN-PRI TOP VIEW Transceiver Functionali ..
DS2154LN ,Enhanced E1 Single Chip TransceiverBlock Diagram .. 5Pin List ..... 7
DS2154LN ,Enhanced E1 Single Chip TransceiverFEATURES PACKAGE OUTLINE Complete E1(CEPT) PCM-30/ISDN-PRItransceiver functionality Onboard long- ..
DS2154L-DS2154LN
Enhanced E1 Single Chip Transceiver
FEATURESComplete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionalityOnboard long- and short-haul line interface forclock/data recovery and waveshaping32-bit or 128-bit crystal-less jitter attenuatorGenerates line build outs for both 120Ω=and
75Ω=linesFrames to FAS, CAS, and CRC4 formatsDual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed busesExtracts and inserts CAS signalingDetects and generates Remote and AIS alarmsProgrammable output clocks for Fractional E1,H0, and H12 applicationsFully independent transmit and receive
functionalityFull access to both Si and Sa bits aligned with
CRC multiframeFour separate loopbacks for testing functionsLarge counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bitsPin compatible with DS2152 T1 Enhanced Single-Chip Transceiver5V supply; low power CMOS100-pin 14mm2 body LQFP package
PACKAGE OUTLINE
ORDERING INFORMATIONDS2154L (0°C to 70°C)
DS2154LN (-40°C to +85°C)
DESCRIPTIONThe DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 toover 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can accessto control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
DS2154DS2154
TABLE OF CONTENTS
1.0 INTRODUCTION.............................................................................................................4New Features...................................................................................................................................4
Block Diagram................................................................................................................................5
Pin List............................................................................................................................................7
Pin Description..............................................................................................................................10
Register Map.................................................................................................................................15
2.0PARALLEL PORT........................................................................................................20
3.0CONTROL, ID, AND TEST REGISTERS......................................................................20SYNC/RESYNC Criteria..............................................................................................................22Framers Loopback.........................................................................................................................27
Automatic Alarm Generation........................................................................................................28
Power-up Sequence.......................................................................................................................30
Remote Loopback.........................................................................................................................31Local Loopback.............................................................................................................................31
4.0STATUS AND INFORMATION REGISTERS................................................................32CRC 4 SYNC Counter..................................................................................................................35
Alarm Criteria...............................................................................................................................36
5.0ERROR COUNT REGISTERS......................................................................................40BPV or Code Violation Counter...................................................................................................40
CRC4 Error Counter.....................................................................................................................41
E-bit Counter.................................................................................................................................41FAS Error Counter........................................................................................................................42
6.0DSO MONITORING FUNCTION...................................................................................43
7.0SIGNALING OPERATION............................................................................................46Processor Based Signaling............................................................................................................46
Hardware Based Signaling............................................................................................................49
8.0 PER-CHANNEL CODE GENERATION........................................................................51Transmit Side Code Generation....................................................................................................51Receive Side Code Generation.....................................................................................................53
9.0CLOCK BLOCKING REGISTERS................................................................................54
10.0ELASTIC STORES OPERATION.................................................................................56
11.0ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..............................57Hardware Scheme.........................................................................................................................57
Internal Register Scheme Based on Double-Frame......................................................................57
Internal Register Scheme Based on CRC4 Multiframe................................................................60
DS2154
12.0 LINE INTERFACE FUNCTIONS...................................................................................62Receive Clock and Data Recovery................................................................................................62
Transmit Waveshaping and Line Driving.....................................................................................63
Jitter Attenuator.............................................................................................................................64
13.0 TIMING DIAGRAMS......................................................................................................67Synchronization Flowchart...........................................................................................................72
Transmit Data Flow Diagram.......................................................................................................73
14.0 CHARACTERISTICS....................................................................................................74Absolute Maximum Rating...........................................................................................................74DC Parameters..............................................................................................................................74
AC Parameters..............................................................................................................................75
Timing...........................................................................................................................................77
Package Description......................................................................................................................85
DS2154
1.0 INTRODUCTIONThe DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2153 have been retained and software created
for the original devices is transferable into the DS2154.
DS2154
DS2154 ENHANCED E1 SINGLE-CHIP TRANSCEIVER Figure 1-1
