DS2154L+ ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.6 1.1 INTRODUCTION ........6 1.1.1 New
DS2154LA2 ,Enhanced E1 Single Chip TransceiverApplications Fully Independent Transmit and Receive Functionality ORDERING INFORMATION Full Acce ..
DS2154LA2+ ,Enhanced E1 Single Chip TransceiverFEATURES PIN CONFIGURATION Complete E1 (CEPT) PCM-30/ISDN-PRI TOP VIEW Transceiver Functionali ..
DS2154LN ,Enhanced E1 Single Chip TransceiverBlock Diagram .. 5Pin List ..... 7
DS2154LN ,Enhanced E1 Single Chip TransceiverFEATURES PACKAGE OUTLINE Complete E1(CEPT) PCM-30/ISDN-PRItransceiver functionality Onboard long- ..
DS2154LN+ ,Enhanced E1 Single Chip Transceiver100 DS2154 Enhanced E1 Single-Chip Transceiver
DS2154L+-DS2154LA2-DS2154LA2+-DS2154LN+-DS2154LNA2+
Enhanced E1 Single Chip Transceiver
FEATURES � Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality � On-Board Long- and Short-Haul Line
Interface for Clock/Data Recovery and
Waveshaping � 32-Bit or 128-Bit Crystal-Less Jitter
Attenuator � Generates Line Build-Outs for Both 120Ω
and 75Ω Lines � Frames to FAS, CAS, and CRC4 Formats � Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Asynchronous
Backplanes Up to 8.192MHz � 8-Bit Parallel Control Port That can be Used
Directly on Either Multiplexed or
Nonmultiplexed Buses (Intel or Motorola) � Extracts and Inserts CAS Signaling � Detects and Generates Remote and AIS
Alarms � Programmable Output Clocks for Fractional
E1, H0, and H12 Applications � Fully Independent Transmit and Receive
Functionality � Full Access to Both Si and Sa Bits Aligned
with CRC Multiframe � Four Separate Loopbacks for Testing
Functions � Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits � Pin Compatible with DS2152 T1 Enhanced
Single-Chip Transceiver � 5V Supply; Low-Power CMOS � 100-Pin, 14mm2 LQFP Package
PIN CONFIGURATION
ORDERING INFORMATION
PART TEMP
RANGE
PIN-
PACKAGE DS2154L 0°C to +70°C 100 LQFP
DS2154L+ 0°C to +70°C 100 LQFP
DS2154LN -40°C to +85°C 100 LQFP
DS2154LN+-40°C to +85°C 100 LQFP
+Denotes lead-free/RoHS-compliant package.
DS2154
Enhanced E1 Single-Chip Transceiver
DS2154
LQFP
(14mm x 14mm)
TOP VIEW
DS2154
TABLE OF CONTENTS DETAILED DESCRIPTION....................................................................................................6 1.1 INTRODUCTION.............................................................................................................................6
1.1.1 New Features.........................................................................................................................................6
1.2 FUNCTIONAL DESCRIPTION...........................................................................................................7
1.3 READER’S NOTE...........................................................................................................................7
PIN DESCRIPTION................................................................................................................9 2.1 TRANSMIT SIDE DIGITAL PINS......................................................................................................11
2.2 RECEIVE SIDE DIGITAL PINS........................................................................................................12
2.3 PARALLEL CONTROL PORT PINS.................................................................................................13
2.4 LINE INTERFACE PINS.................................................................................................................14
2.5 SUPPLY PINS..............................................................................................................................14
PARALLEL PORT...............................................................................................................20 CONTROL, ID, AND TEST REGISTERS............................................................................20 4.1 FRAMER LOOPBACK....................................................................................................................29
4.2 LOCAL LOOPBACK.......................................................................................................................29
4.3 REMOTE LOOPBACK....................................................................................................................29
4.4 POWER-UP SEQUENCE...............................................................................................................30
4.5 AUTOMATIC ALARM GENERATION................................................................................................30
STATUS AND INFORMATION REGISTERS......................................................................31 5.1 CRC4 SYNC COUNTER...............................................................................................................33
ERROR COUNT REGISTERS.............................................................................................39 6.1 BPV OR CODE VIOLATION COUNTER...........................................................................................39
6.2 CRC4 ERROR COUNTER............................................................................................................40
6.3 E-BIT COUNTER.........................................................................................................................40
6.4 FAS ERROR COUNTER...............................................................................................................41
DS0 MONITORING FUNCTION..........................................................................................42 SIGNALING OPERATION...................................................................................................46 8.1 PROCESSOR-BASED SIGNALING..................................................................................................46
8.2 HARDWARE-BASED SIGNALING...................................................................................................49
8.2.1 Receive Side........................................................................................................................................49
8.2.2 Transmit Side.......................................................................................................................................49
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.....................................51 9.1 TRANSMIT SIDE CODE GENERATION............................................................................................51
9.1.1 Simple Idle Code Insertion and Per-Channel Loopback......................................................................51
9.1.2 Per-Channel Code Insertion................................................................................................................52
9.2 RECEIVE SIDE CODE GENERATION..............................................................................................53
10 CLOCK BLOCKING REGISTERS..................................................................................55
11 ELASTIC STORES OPERATION...................................................................................57 11.1 RECEIVE SIDE............................................................................................................................57
11.2 TRANSMIT SIDE..........................................................................................................................57
12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION................................58 12.1 HARDWARE SCHEME..................................................................................................................58
12.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME...........................................................58
12.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME.....................................................61
DS2154
13 LINE INTERFACE FUNCTION.......................................................................................63 13.1 RECEIVE CLOCK AND DATA RECOVERY.......................................................................................64
13.2 TRANSMIT WAVESHAPING AND LINE DRIVING...............................................................................64
13.3 JITTER ATTENUATOR..................................................................................................................65
14 TIMING DIAGRAMS.......................................................................................................69
15 DC CHARACTERISTICS................................................................................................76
16 AC CHARACTERISTICS................................................................................................77
17 PACKAGE INFORMATION............................................................................................87 17.1 100-PIN LQFP (56-G5002-000).................................................................................................87
DS2154
LIST OF FIGURES Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver......................................................................8
Figure 13-1. External Analog Connections...............................................................................................66
Figure 13-2. Jitter Tolerance....................................................................................................................67
Figure 13-3. Transmit Waveform Template..............................................................................................67
Figure 13-4. Jitter Attenuation..................................................................................................................68
Figure 14-1. Receive Side Timing............................................................................................................69
Figure 14-2. Receive Side Boundary Timing (with Elastic Store Disabled)..............................................69
Figure 14-3. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled).............................70
Figure 14-4. Receive Side 2.048MHz Boundary Timing (with Elastic Store Enabled).............................70
Figure 14-5. Transmit Side Timing...........................................................................................................71
Figure 14-6. Transmit Side Boundary Timing...........................................................................................71
Figure 14-7. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled)............................72
Figure 14-8. Transmit Side 2.048MHz Boundary Timing (with Elastic Store Enabled)............................72
Figure 14-9. G.802 Timing........................................................................................................................73
Figure 14-10. Synchronization Flow Chart...............................................................................................74
Figure 14-11. Transmit Data Flow............................................................................................................75
Figure 16-1. Intel Bus Read AC Timing (BTS = 0/MUX = 1)....................................................................77
Figure 16-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1).....................................................................78
Figure 16-3. Motorola Bus AC Timing (BTS = 1/MUX = 1).......................................................................78
Figure 16-4. Receive Side AC Timing......................................................................................................80
Figure 16-5. Receive System Side AC Timing.........................................................................................81
Figure 16-6. Receive Line Interface AC Timing........................................................................................81
Figure 16-7. Transmit Side AC Timing.....................................................................................................83
Figure 16-8. Transmit System Side AC Timing........................................................................................84
Figure 16-9. Transmit Line Interface Side AC Timing...............................................................................84
Figure 16-10. Intel Bus Read AC Timing (BTS = 0/MUX = 0)..................................................................85
Figure 16-11. Intel Bus Write AC Timing (BTS=0/MUX=0).......................................................................86
Figure 16-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)...........................................................86
Figure 16-13. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)...........................................................86
DS2154
LIST OF TABLES Table 2-1. Register Map...........................................................................................................................15
Table 4-1. Sync/Resync Criteria...............................................................................................................21
Table 5-1. Alarm Criteria..........................................................................................................................35
Table 13-1. Line Build-Out Select in LICR................................................................................................64
Table 13-2. Transformer Specifications....................................................................................................65
Table 15-1. Recommended DC Operating Conditions.............................................................................76
Table 15-2. Capacitance..........................................................................................................................76
Table 15-3. DC Characteristics................................................................................................................76
Table 16-1. AC Characteristics—Multiplexed Parallel Port (MUX = 1).....................................................77
Table 16-2. AC Characteristics—Receive Side........................................................................................79
Table 16-3. AC Characteristics—Transmit Side.......................................................................................82
Table 16-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 0)..............................................85
