DS2153Q ,E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.4 1.1 INTRODUCTION..4 1.2 READER’S NOTE4 2
DS2153Q-A7 ,E1 Single Chip TransceiverApplications ALE(AS) 7 TSER 39 Fully Independent Transmit and Receive 8 38WR (R/W) TCLK Functiona ..
DS2154L ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS1.0 INTRODUCTION.4New
DS2154L+ ,Enhanced E1 Single Chip TransceiverTABLE OF CONTENTS 1 DETAILED DESCRIPTION.6 1.1 INTRODUCTION ........6 1.1.1 New
DS2154LA2 ,Enhanced E1 Single Chip TransceiverApplications Fully Independent Transmit and Receive Functionality ORDERING INFORMATION Full Acce ..
DS2154LA2+ ,Enhanced E1 Single Chip TransceiverFEATURES PIN CONFIGURATION Complete E1 (CEPT) PCM-30/ISDN-PRI TOP VIEW Transceiver Functionali ..
DS2153Q
E1 Single Chip Transceiver
FEATURES � Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality � On-Board Line Interface for Clock/Data
Recovery and Waveshaping � 32-Bit or 128-Bit Jitter Attenuator � Generates Line Build-Outs for Both 120Ω
and 75Ω Lines � Frames to FAS, CAS, and CRC4 Formats � Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Backplanes Up
to 8.192MHz � 8-Bit Parallel Control Port That can be Used
on Either Multiplexed or Nonmultiplexed
Buses � Extracts and Inserts CAS Signaling � Detects and Generates Remote and AIS
Alarms � Programmable Output Clocks for Fractional
E1, H0, and H12 Applications � Fully Independent Transmit and Receive
Functionality � Full Access to Both Si and Sa Bits � Three Separate Loopbacks for Testing � Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits � Pin Compatible with DS2151Q T1 Single-
Chip Transceiver � 5V Supply; Low-Power CMOS
PIN CONFIGURATION
ORDERING INFORMATION
PART TEMP
RANGE
PIN-
PACKAGE DS2153Q 0°C to +70°C 44 PLCC
DS2153Q+ 0°C to +70°C 44 PLCC
DS2153QN -40°C to +85°C 44 PLCC
DS2153QN+ -40°C to +85°C 44 PLCC
+Denotes lead-free/RoHS-compliant package.
DS2153Q
E1 Single-Chip Transceiver
Dallas
DS2153Q
T1SCT
ELASTIC STORES
FRAMER
& SH
UL LI
NE
INT
PARALLEL CONTROL
PORT
ACTUAL SIZE OF 44-PIN PLCC
FUNCTIONAL BLOCKS
ALE(AS)
WR (R/W)
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
CHB
ACLK
BTS
RVSS
XTAL1XTAL2
INT
INT
D7
D6
D5
D4
D3
D2
D1
D0
LK 2 3456
44 43 42 41 40 7
18
19 20 21 22 23 24 25 26 27 28
DS2153Q
PLCC
DS2153Q
TABLE OF CONTENTS DETAILED DESCRIPTION....................................................................................................4 1.1 INTRODUCTION................................................................................................................................4
1.2 READER’S NOTE..............................................................................................................................4
PIN DESCRIPTION................................................................................................................6 2.1 DS2153Q REGISTER MAP...............................................................................................................8
PARALLEL PORT.................................................................................................................9 CONTROL AND TEST REGISTERS...................................................................................10 4.1 LOCAL LOOPBACK.........................................................................................................................17
4.2 REMOTE LOOPBACK......................................................................................................................17
4.3 FRAMER LOOPBACK......................................................................................................................17
4.4 AUTOMATIC ALARM GENERATION...................................................................................................17
4.5 POWER-UP SEQUENCE.................................................................................................................17
STATUS AND INFORMATION REGISTERS......................................................................18 5.1 CRC4 SYNC COUNTER.................................................................................................................20
ERROR COUNT REGISTERS.............................................................................................26 6.1 BPV OR CODE VIOLATION COUNTER.............................................................................................26
6.2 CRC4 ERROR COUNTER...............................................................................................................27
6.3 E-BIT COUNTER............................................................................................................................27
6.4 FAS BIT ERROR COUNTER............................................................................................................28
SA DATA LINK CONTROL AND OPERATION..................................................................29 SIGNALING OPERATION...................................................................................................30 TRANSMIT IDLE REGISTERS............................................................................................32
10 CLOCK BLOCKING REGISTERS....................................................................................33
11 ELASTIC STORES OPERATION.....................................................................................35
12 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION.................................36
13 LINE INTERFACE FUNCTIONS.......................................................................................39 13.1 RECEIVE CLOCK AND DATA RECOVERY.......................................................................................40
13.2 TRANSMIT WAVESHAPING AND LINE DRIVING..............................................................................41
13.3 JITTER ATTENUATOR..................................................................................................................42
14 TIMING DIAGRAMS.........................................................................................................46
15 DC CHARACTERISTICS..................................................................................................52
16 AC CHARACTERISTICS..................................................................................................53
17 PACKAGE INFORMATION..............................................................................................60 17.1 44-PIN PLCC (56-G4003-001)..................................................................................................60
DS2153Q
LIST OF FIGURES Figure 1-1. DS2153Q Block Diagram.........................................................................................................5
Figure 13-1. External Analog Connections...............................................................................................43
Figure 13-2. Jitter Tolerance....................................................................................................................44
Figure 13-3. Transmit Waveform Template..............................................................................................44
Figure 13-4. Jitter Attenuation..................................................................................................................45
Figure 14-1. Receive Side Timing............................................................................................................46
Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled)............................................46
Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled.................................................47
Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled..................................................47
Figure 14-5. Transmit Side Timing...........................................................................................................48
Figure 14-6. Transmit Side Boundary Timing...........................................................................................48
Figure 14-7. G.802 Timing........................................................................................................................49
Figure 14-8. Synchronization Flowchart...................................................................................................50
Figure 14-9. Transmit Data Flow..............................................................................................................51
Figure 16-1. Intel Bus Read AC Timing....................................................................................................54
Figure 16-2. Intel Bus Write AC Timing....................................................................................................54
Figure 16-3. Motorola Bus AC Timing......................................................................................................55
Figure 16-4. Receive Side AC Timing......................................................................................................57
Figure 16-5. Transmit Side AC Timing.....................................................................................................59
LIST OF TABLES Table 4-1. Sync/Resync Criteria...............................................................................................................11
Table 5-1. Alarm Set and Clear Criteria...................................................................................................22
Table 13-1. Source of RCLK Upon RCL...................................................................................................40
Table 13-2. LBO Select in LICR...............................................................................................................41
Table 13-3. Transformer Specifications....................................................................................................41
Table 13-4. Crystal Selection Guidelines.................................................................................................42
Table 15-1. Recommended DC Characteristics.......................................................................................52
Table 15-2. Capacitance..........................................................................................................................52
Table 15-3. DC Characteristics................................................................................................................52
Table 16-1. AC Characteristics—Parallel Port.........................................................................................53
Table 16-2. AC Characteristics—Receive Side........................................................................................56
Table 16-3. AC Characteristics—Transmit Side.......................................................................................58
DS2153Q
1 DETAILED DESCRIPTION The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1
lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial
stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.
The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board
jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a
set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access
via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the
latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,
300 233, TBR 12 and TBR 13.
1.1 Introduction The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of
the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2153Q is totally independent from the receive side in both the clock
requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1
transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation
mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP
and TRING pins via a coupling transformer.
1.2 Reader’s Note This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.
These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is
identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made
up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB
and is transmitted last. Throughout this data sheet, the following abbreviations are used:
FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International Bits
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
Sa Additional bits
E-bit CRC4 Error bits
DS2153Q
Figure 1-1. DS2153Q Block Diagram DS2153Q
2 PIN DESCRIPTION
PIN NAME TYPE FUNCTION 1–4,
41–44
AD4–AD7,
AD0–AD3 I/O
Address/Data Bus. An 8-bit multiplexed address/data bus. RD(DS) I
Active-Low Read Input (Data Strobe) CS I
Active-Low Chip Select. Must be low to read or write the port. 7 ALE(AS) I
Address Latch Enable (Address Strobe). A positive going edge serves to demultiplex the bus. WR(R/W) I
Active-Low Write Input (Read/Write) 9 RLINK O
Receive Link Data. Outputs the full receive data stream including the Sa bits. See Section 14 for timing details.
10 RLCLK O
Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK output. Controlled by RCR2. See Section 14 for timing details.
11 DVSS —
Digital Signal Ground. 0.0V. Should be tied to local ground plane. 12 RCLK O
Receive Clock. Recovered 2.048MHz clock. 13 RCHCLK O
Receive Channel Clock. 256kHz clock that pulses high during the LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 14 for timing details.
14 RSER O
Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK or SYSCLK.
15 RSYNC I/O
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which identifies either frame (RCR1.6 = 0) or multiframe
boundaries (RCR1.6 = 1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 14 for timing
details.
16 RLOS/LOTC O
Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If TCR2.0 = 0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle
high if the TCLK pin has not toggled for 5µs.
17 SYSCLK I
System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic store functions are enabled via either RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100µs, will force all output pins (including the parallel port) to
tri-state.
18 RCHBLK O
Receive Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14 for
timing details.
19 ACLKI I
Alternate Clock Input. Upon a receive carrier loss, the clock applied at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS via a 1kΩ
resistor.
DS2153Q
PIN NAME TYPE FUNCTION 20 BTS I
Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD(DS),
ALE(AS), and WR(R/W) pins. If BTS = 1, then these pins assume the
function listed in parentheses ().
21, 22 RTIP,
RRING —
Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects to a 1:1 transformer (see Section 13 for details).
23 RVDD —
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and TVDD pins.
24 RVSS —
Receive Signal Ground. 0V. Should be tied to local ground plane. 25, 26 XTAL1,
XTAL2 —
Crystal Connections. A pullable 8.192MHz crystal must be applied to these pins. See Section 13 for crystal specifications.
27 INT1 O
Receive Alarm Interrupt 1. Flags host controller during alarm conditions defined in Status Register 1. Active low, open drain output.
28 INT2 O
Receive Alarm Interrupt 2. Flags host controller during conditions defined in Status Register 2. Active low, open drain output.
29 TTIP —
Transmit Tip. Analog line driver output; connects to a step-up transformer (see Section 13 for details).
30 TVSS —
Transmit Signal Ground. 0V. Should be tied to local ground plane. 31 TVDD —
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and RVDD pins.
32 TRING —
Transmit Ring. Analog line driver outputs; connects to a step-up transformer (see Section 13 for details).
33 TCHBLK O
Transmit Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14 for
timing details.
34 TLCLK O
Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK input. Controlled by TCR2. See Section 14 for timing details.
35 TLINK I
Transmit Link Data. If enabled, this pin will be sampled on the falling edge of TCLK to insert the Sa bits. See Section 14 for timing details.
36 TSYNC I/O
Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q
can be programmed to output either a frame or multiframe pulse at this
pin. See Section 14 for timing details.
37 DVDD —
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD pins.
38 TCLK I
Transmit Clock. 2.048MHz primary clock. 39 TSER I
Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge of TCLK.
40 TCHCLK O
Transmit Channel Clock. 256kHz clock that pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel
data. See Section 14 for timing details.
DS2153Q
2.1 DS2153Q Register Map
ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME 00 R BPV or Code Violation Count 1 20 R/W Transmit Align Frame
01 R BPV or Code Violation Count 2 21 R/W Transmit Non-Align Frame
02 R CRC4 Count 1/FAS Error Count 1 22 R/W Transmit Channel Blocking 1
03 R CRC4 Error Count 2 23 R/W Transmit Channel Blocking 2
04 R E-Bit Count 1/FAS Error Count 2 24 R/W Transmit Channel Blocking 3
05 R E-Bit Count 2 25 R/W Transmit Channel Blocking 4
06 R Status 1 26 R/W Transmit Idle 1
07 R Status 2 27 R/W Transmit Idle 2
08 R/W Receive Information 28 R/W Transmit Idle 3
10 R/W Receive Control 1 29 R/W Transmit Idle 4
11 R/W Receive Control 2 2A R/W Transmit Idle Definition
12 R/W Transmit Control 1 2B R/W Receive Channel Blocking 1
13 R/W Transmit Control 2 2C R/W Receive Channel Blocking 2
14 R/W Common Control 1 2E R/W Receive Channel Blocking 3
15 R/W Test 1 2E R/W Receive Channel Blocking 4
16 R/W Interrupt Mask 1 2F R Receive Align Frame
17 R/W Interrupt Mask 2 30 R Receive Signaling 1
18 R/W Line Interface Control 31 R Receive Signaling 2
19 R/W Test 2 32 R Receive Signaling 3
1A R/W Common Control 2 33 R Receive Signaling 4
1B R/W Common Control 3 34 R Receive Signaling 5
1E R Synchronizer Status 35 R Receive Signaling 6
1F R Receive Non-Align Frame 36 R Receive Signaling 7
40 R/W Transmit Signaling 1 37 R Receive Signaling 8
41 R/W Transmit Signaling 2 38 R Receive Signaling 9
42 R/W Transmit Signaling 3 39 R Receive Signaling 10
43 R/W Transmit Signaling 4 3A R Receive Signaling 11
44 R/W Transmit Signaling 5 3B R Receive Signaling 12
45 R/W Transmit Signaling 6 3C R Receive Signaling 13
46 R/W Transmit Signaling 7 3D R Receive Signaling 14
47 R/W Transmit Signaling 8 3E R Receive Signaling 15
48 R/W Transmit Signaling 9 3F R Receive Signaling 16
49 R/W Transmit Signaling 10
4A R/W Transmit Signaling 11
4B R/W Transmit Signaling 12
4C R/W Transmit Signaling 13
4D R/W Transmit Signaling 14
4E R/W Transmit Signaling 15
4F R/W Transmit Signaling 16
Note: Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure proper operation.
DS2153Q
3 PARALLEL PORT The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14
for more details. The multiplexed bus on the DS2153Q saves pins because the address information and
data information share the same signal paths. The addresses are presented to the pins in the first portion of
the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses
must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from
the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS
or WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions
high in Intel timing or as DS transitions low in Motorola timing.
DS2153Q
CONTROL AND TEST REGISTERS The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers
are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the
control registers only need to be accessed when there is a change in the system configuration. There are
two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),
and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described
in this section. The LICR is described in Section 13.
The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power-
up, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)
(MSB) (LSB) RSMF RSM RSIO — — FRC SYNCE RESYNC
SYMBOL
POSITION NAME AND DESCRIPTION RSMF RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR1.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSM RCR1.6
RSYNC Mode Select. 0 = frame mode (see the timing in Section 14)
1 = multiframe mode (see the timing in Section 14)
RSIO RCR1.5
RSYNC I/O Select. 0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled) (Note:
this bit must be set to 0 when RCR2.1 = 0)
— RCR1.4
Not Assigned. Should be set to 0 when written. — RCR1.3
Not Assigned. Should be set to 0 when written. FRC RCR1.2
Frame Resync Criteria. 0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
SYNCE RCR1.1
Sync Enable. 0 = auto resync enabled
1 = auto resync disabled
RESYNC RCR1.0
Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
DS2153Q
Table 4-1. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA RESYNC CRITERIA ITU SPEC FAS
FAS present in frames N
and N + 2, and FAS not
present in frame N + 1.
Three consecutive incorrect FAS received.
Alternate (RCR1.2 = 1) the above criteria
is met or three consecutive incorrect bit 2
of non-FAS received.
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms.
915 or more CRC4 codewords out of 1000
received in error.
G.706
4.2
4.3.2
CAS
Valid MF alignment word
found and previous time slot
16 contains code other than
all 0s.
Two consecutive MF alignment words
received in error. G.732
5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB) (LSB) Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE —
SYMBOL
POSITION NAME AND DESCRIPTION Sa8S RCR2.7
Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin; set to 0 to not report the Sa8 bit.
Sa7S RCR2.6
Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin; set to 0 to not report the Sa7 bit.
Sa6S RCR2.5
Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin; set to 0 to not report the Sa6 bit.
Sa5S RCR2.4
Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin; set to 0 to not report the Sa5 bit.
Sa4S RCR2.3
Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin; set to 0 to not report the Sa4 bit.
RSCLKM RCR2.2
Receive Side SYSCLK Mode Select. 0 = if SYSCLK is 1.544MHz
1 = if SYSCLK is 2.048MHz
RESE RCR2.1
Receive Side Elastic Store Enable. 0=elastic store is bypassed
1=elastic store is enabled
DS2153Q
TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex)
(MSB) (LSB) — TFPT T16S TUA1 TSiS TSA1 TSM TSIO
SYMBOL
POSITION NAME AND DESCRIPTION — TCR1.7
Not Assigned. Should be set to 0 when written to. TFPT TCR1.6
Transmit Time Slot 0 Pass Through. 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
T16S TCR1.5
Transmit Time Slot 16 Data Select. 0 = sample time slot 16 at TSER pin
1 = source time slot 16 from TS1 to TS16 registers
TUA1 TCR1.4
Transmit Unframed All Ones. 0 = transmit data normally
1 = transmit an unframed all ones code at TPOS and TNEG
TSiS TCR1.3
Transmit International Bit Select. 0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1 TCR1.2
Transmit Signaling All Ones. 0 = normal operation
1 = force time slot 16 in every frame to all ones
TSM TCR1.1
TSYNC Mode Select. 0 = frame mode (see the timing in Section 14)
1 = CAS and CRC4 multiframe mode (see the timing in Section 14)
TSIO TCR1.0
TSYNC I/O Select. 0 = TSYNC is an input
1 = TSYNC is an output
Note: For details about how the Transmit Control Registers affect the operation of the DS2153Q, see Figure 14-9.
DS2153Q
TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex)
(MSB) (LSB) Sa8S Sa7S Sa6S Sa5S Sa4S — AEBE P16F
SYMBOL
POSITION NAME AND DESCRIPTION Sa8S TCR2.7
Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK pin; set to 0 to not source the Sa8 bit.
Sa7S TCR2.6
Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK pin; set to 0 to not source the Sa7 bit.
Sa6S TCR2.5
Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK pin; set to 0 to not source the Sa6 bit.
Sa5S TCR2.4
Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK pin; set to 0 to not source the Sa5 bit.
Sa4S TCR2.3
Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK pin; set to 0 to not source the Sa4 bit.
— TCR2.2
Not Assigned. Should be set to 0 when written. AEBE TCR2.1
Automatic E-Bit Enable. 0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
P16F TCR2.0
Function of Pin 16. 0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
DS2153Q
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)
(MSB) (LSB) FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4
SYMBOL
POSITION NAME AND DESCRIPTION FLB CCR1.7
Framer Loopback. 0 = loopback disabled
1 = loopback enabled
THDB3 CCR1.6
Transmit HDB3 Enable. 0 = HDB3 disabled
1 = HDB3 enabled
TG802 CCR1.5
Transmit G.802 Enable. See Figure 14-7 for details. 0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
TCRC4 CCR1.4
Transmit CRC4 Enable. 0 = CRC4 disabled
1 = CRC4 enabled
RSM CCR1.3
Receive Signaling Mode Select. 0 = CAS signaling mode
1 = CCS signaling mode
RHDB3 CCR1.2 Receive HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
RG802 CCR1.1
Receive G.802 Enable. See Figure 14-7 for details. 0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
RCRC4 CCR1.0
Receive CRC4 Enable. 0 = CRC4 disabled
1 = CRC4 enabled
DS2153Q
CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex)
(MSB) (LSB) ECUS VCRFS AAIS ARA RSERC LOTCMC RLB LLB
SYMBOL
POSITION NAME AND DESCRIPTION ECUS CCR2.7
Error Counter Update Select. 0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
VCRFS CCR2.6
VCR Function Select. 0 = count Bipolar Violations (BPVs)
1 = count Code Violations (CVs)
AAIS CCR2.5
Automatic AIS Generation. 0 = disabled
1 = enabled
ARA CCR2.4
Automatic Remote Alarm Generation. 0 = disabled
1 = enabled
RSERC CCR2.3
RSER Control. 0 = allow RSER to output data as received under all conditions
1 = force RSER to 1 under loss of frame alignment conditions
LOTCMC CCR2.2
Loss of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present RCLK
if the TCLK should fail to transition (see Figure 1-1).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
RLB CCR2.1
Remote Loopback. 0 = loopback disabled
1 = loopback enabled
LLB CCR2.0
Local Loopback. 0 = loopback disabled
1 = loopback enabled
DS2153Q
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB) (LSB) TESE TCBFS TIRFS ESR LIRST — TSCLKM —
SYMBOL
POSITION NAME AND DESCRIPTION TESE CCR3.7
Transmit Elastic Store Enable. 0 = elastic store is disabled
1 = elastic store is enabled
TCBFS CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select. 0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
TIRFS CCR3.5
Transmit Idle Registers (TIR) Function Select. 0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
ESR CCR3.4
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be set and cleared
again for a subsequent reset. Do not leave this bit set high.
LIRST CCR3.3
Line Interface Reset. Setting this bit from a 0 to a 1 will initiate an internal reset that affects the slicer, AGC, clock recovery state
machine, and jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent
reset.
— CCR3.2
Not Assigned. Should be set to 0 when written. TSCLKM CCR3.1
Transmit Backplane Clock Select. Must be set like RCR2.2. 0 = 1.544MHz
1 = 2.048MHz
— CCR3.0
Not Assigned. Should be set to 0 when written. DS2153Q
4.1 Local Loopback When CCR2.0 is set to a 1, the DS2153Q will be forced into Local Loopback (LLB). In this loopback,
data will continue to be transmitted as normal through the transmit side of the SCT. Data being received
at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator. See Figure 1-1 for more details.
4.2 Remote Loopback When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote Loopback (RLB). In this loopback,
data recovered off the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line
(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to
pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be
ignored. Data in this loopback will pass through the jitter attenuator. See Figure 1-1 for more details.
4.3 Framer Loopback When CCR1.7 is set to a 1, the DS2153Q will enter a Framer Loopback (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted at TTIP and TRING.
2) Data off the E1 line at RTIP and RRING will be ignored.
The RCLK output will be replaced with the TCLK input.
4.4 Automatic Alarm Generation When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of
the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
DS2153Q will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be
transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1
at the same time.
4.5 Power-Up Sequence On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to
all of the internal registers (this includes setting the Test Register) since the contents of the internal
registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the
line interface circuitry (it will take the DS2153Q about 40ms to recover from the LIRST being toggled).
Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0
(this step can be skipped if the elastic stores are disabled).
DS2153Q
STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real-time status of the DS2153Q:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically ANDed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2153Q with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2),
respectively.
DS2153Q
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB) (LSB) TESF TESE JALT RESF RESE CRCRC FASRC CASRC
SYMBOL
POSITION NAME AND DESCRIPTION TESF RIR.7
Transmit Elastic Store Full. Set when the elastic store fills and a frame is deleted.
TESE RIR.6
Transmit Elastic Store Empty. Set when the elastic store
empties and a frame is repeated.
JALT RIR.5
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RESF RIR.4
Elastic Store Full. Set when the elastic store buffer fills and a frame is deleted.
RESE RIR.3
Elastic Store Empty. Set when the elastic store buffer empties and a frame is repeated.
CRCRC RIR.2
CRC Resync Criteria Met. Set when 915/1000 codewords are received in error.
FASRC RIR.1
FAS Resync Criteria Met. Set when three consecutive FAS words are received in error.
CASRC RIR.0
CAS Resync Criteria Met. Set when two consecutive CAS MF alignment words are received in error.
DS2153Q
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)
(MSB) (LSB) CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA
SYMBOL
POSITION NAME AND DESCRIPTION CSC5 SSR.7
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CSC4 SSR.6
CRC4 Sync Counter Bit 4. CSC3 SSR.5
CRC4 Sync Counter Bit 3. CSC2 SSR.4
CRC4 Sync Counter Bit 2. CSC0 SSR.3
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB bit is not accessible. This bit will toggle each time the
CRC4 MF search times out at 8ms.
FASSA SSR.2
FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level.
CASSA SSR.1
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word.
CRC4SA SSR.0
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word.
5.1 CRC4 Sync Counter The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is
cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the
amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of
CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then
the search should be abandoned and proper action taken. The CRC4 sync counter will rollover.
DS2153Q
SR1: STATUS REGISTER 1 (Address = 06 Hex)
(MSB) (LSB) RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS
SYMBOL
POSITION NAME AND DESCRIPTION RSA1 SR1.7
Receive Signaling All 1s. Set when the contents of time slot 16 contains less than three 0s over 16 consecutive frames. This alarm
is not disabled in the CCS signaling mode.
RDMA SR1.6
Receive Distant MF Alarm. Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm
is not disabled in the CCS signaling mode.
RSA0 SR1.5
Receive Signaling All 0s. Set when over a full MF, time slot 16 contains all 0s.
RSLIP SR1.4
Receive Elastic Store Slip Occurrence. Set when the elastic store has either repeated or deleted a frame of data.
RUA1 SR1.3
Receive Unframed All 1s. Set when an unframed all 1s code is received at RTIP and RRING.
RRA SR1.2
Receive Remote Alarm. Set when a remote alarm is received at RTIP and RRING.
RCL SR1.1
Receive Carrier Loss. Set when 255 consecutive 0s have been detected at RTIP and RRING.
RLOS SR1.0
Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream.
DS2153Q
Table 5-1. Alarm Set and Clear Criteria
ALARM SET CRITERIA CLEAR CRITERIA CCITT
SPEC.
RSA1 (receive signaling
all 1s)
Over 16 consecutive frames (one full
MF) time slot 16 contains less than
three 0s
Over 16 consecutive frames (one full
MF) time slot 16 contains three or more
0s
G.732
4.2
RSA0 (receive signaling
all 0s)
Over 16 consecutive frames (one full
MF) time slot 16 contains all 0s
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single 1
G.732
5.2
RDMA (receive distant
multiframe alarm)
Bit 6 in time slot 16 of frame 0 set to
1 for two consecutive MF
Bit 6 in time slot 16 of frame 0 set to 0
for a two consecutive MF O.162
2.1.5
RUA1 (receive unframed
all 1s)
Less than three 0s in two frames
(512 bits)
More than two 0s in two frames (512
bits) O.162
1.6.1.2
RRA (receive remote
alarm)
Bit 3 of non-align frame set to 1 for
three consecutive occasions
Bit 3 of non-align frame set to 0 for
three consecutive occasions O.162
2.1.4
RCL (receive carrier
loss)
255 consecutive 0s received In 255-bit times, at least 32 1s are
received G.775
DS2153Q
SR2: STATUS REGISTER 2 (Address = 07 Hex)
(MSB) (LSB) RMF RAF TMF SEC TAF LOTC RCMF TSLIP
SYMBOL
POSITION NAME AND DESCRIPTION RMF SR2.7
Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used
to alert the host that signaling data is available.
RAF SR2.6
Receive Align Frame. Set every 250ms at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the
RAF and RNAF registers.
TMF SR2.5
Transmit Multiframe. Set every 2µs (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host
that signaling data needs to be updated.
SEC SR2.4
1-Second Timer. Set on increments of 1 second based on RCLK. If CCR2.7 = 1, then this bit will be set every 62.5ms instead of once a
second.
TAF SR2.3
Transmit Align Frame. Set every 250µs at the beginning of align frames. Used to alert the host that the TAF and TNAF registers
need to be updated.
LOTC SR2.2
Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9µs). Will force pin 16 high
if enabled via TCR2.0. Based on RCLK.
RCMF SR2.1
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbitrary boundary if CRC4
is disabled.
TSLIP SR2.0
Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data.
DS2153Q
IMR1: INTERRUPT MASK REGISTER1 (Address = 16 Hex)
(MSB) (LSB) RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS
SYMBOL
POSITION NAME AND DESCRIPTION RSA1 IMR1.7
Receive Signaling All 1s. 0 = interrupt masked
1 = interrupt enabled
RDMA IMR1.6
Receive Distant MF Alarm. 0 = interrupt masked
1 = interrupt enabled
RSA0 IMR1.5
Receive Signaling All 0s. 0 = interrupt masked
1 = interrupt enabled
RSLIP IMR1.4
Receive Elastic Store Slip Occurrence. 0 = interrupt masked
1 = interrupt enabled
RUA1 IMR1.3
Receive Unframed All 1s. 0 = interrupt masked
1 = interrupt enabled
RRA IMR1.2
Receive Remote Alarm. 0 = interrupt masked
1 = interrupt enabled
RCL IMR1.1
Receive Carrier Loss. 0 = interrupt masked
1 = interrupt enabled
RLOS IMR1.0
Receive Loss of Sync. 0 = interrupt masked
1 = interrupt enabled
DS2153Q
IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex)
(MSB) (LSB) RMF RAF TMF SEC TAF LOTC RCMF TSLIP
SYMBOL
POSITION NAME AND DESCRIPTION RMF IMR2.7
Receive CAS Multiframe. 0 = interrupt masked
1 = interrupt enabled
RAF IMR2.6
Receive Align Frame. 0 = interrupt masked
1 = interrupt enabled
TMF IMR2.5
Transmit Multiframe. 0 = interrupt masked
1 = interrupt enabled
SEC IMR2.4
1-Second Timer. 0 = interrupt masked
1 = interrupt enabled
TAF IMR2.3
Transmit Align Frame. 0 = interrupt masked
1 = interrupt enabled
LOTC IMR2.2
Loss Of Transmit Clock. 0 = interrupt masked
1 = interrupt enabled
RCMF IMR2.1
Receive CRC4 Multiframe. 0 = interrupt masked
1 = interrupt enabled
TSLIP IMR2.0
Transmit Side Elastic Store Slip. 0 = interrupt masked
1 = interrupt enabled
DS2153Q
ERROR COUNT REGISTERS There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4
SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either 1-second boundaries (CCR2.7 = 0) or every 62.5ms
(CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5ms. The user can use the interrupt
from the timer to determine when to read these registers. The user has a full second (or 62.5ms) to read
the counters before the data is lost.
6.1 BPV or Code Violation Counter Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either Bipolar Violations (BPVs) or Code Violations (CVs). If CCR2.6 = 0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 codewords
are not counted as BPVs. If CCR2.6 = 1, then the VCR counts code violations as defined in CCITT
O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most
applications, the DS2153Q should be programmed to count BPVs when receiving AMI code and to count
CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync
conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would
have to be greater than 10**-2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address = 00
Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address = 01
Hex)
(MSB) (LSB) V15 V14 V13 V12 V11 V10 V9 V8 VCR1
V7 V6 V5 V4 V3 V2 V1 V0 VCR2
SYMBOL
POSITION NAME AND DESCRIPTION V15 VCR1.7 MSB of the 16-bit bipolar or code violation count.
V0 VCR2.0 LSB of the 16-bit bipolar or code violation count.
DS2153Q
6.2 CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address = 02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address = 03 Hex)
(MSB) (LSB) (See note) (See note) (See note) (See note) (See note) (See note) CRC9 CRC8 CRCCR1
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 CRCCR2
SYMBOL
POSITION NAME AND DESCRIPTION CRC9 CRCCR1.1 MSB of the 10-bit CRC4 error count.
CRC0 CRCCR2.0 LSB of the 10-bit CRC4 error count.
Note: The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.
6.3 E-Bit Counter E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address = 04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address = 05 Hex)
(MSB) (LSB) (See note) (See note) (See note) (See note) (See note) (See note) EB9 EB8 EBCR1
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBCR2
SYMBOL
POSITION NAME AND DESCRIPTION EB9 EBCR1.1 MSB of the 10-bit E-bit count.
EB0 EBCR2.0 LSB of the 10-bit E-bit count.
Note: The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter. DS2153Q
6.4 FAS Bit Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is
disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error
count in a 1-second period is 4000, this counter cannot saturate.
FASCR1: FAS BIT COUNT REGISTER 1 (Address = 02 Hex)
FASCR2: FAS BIT COUNT REGISTER 2 (Address = 04 Hex)
(MSB) (LSB) FAS11 FAS10 FAS9 FAS8 FAS7 FAS6 (Note 1) (Note 1) FASCR1
FAS5 FAS4 FAS3 FAS2 FAS1 FAS0 (Note 2) (Note 2) FASCR2
SYMBOL
POSITION NAME AND DESCRIPTION FAS11 FASCR1.7 MSB of the 12-bit FAS error count.
FAS0 FASCR2.2 LSB of the 12-bit FAS error count.
Note 1: The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter.
Note 2: The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter. DS2153Q
Sa DATA LINK CONTROL AND OPERATION The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit
positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and
TNAF) or via two external pins (RLINK and TLINK).
On the receive side, the Sa bits are always reported in the internal RNAF register (see Section 12 for more
details). All five Sa bits are always output at the RLINK pin. See Section 14 for detailed timing. Via
RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the
user to create a clock that can be used to capture the needed Sa bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register
(TCR1.6 = 0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source
any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through
the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via
the TLINK pin and the TLINK pin should be tied to the TSER pin. See the timing diagrams and the
transmit data flow diagram in Section 14 for examples.
DS2153Q
8 SIGNALING OPERATION The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parentheses are the channel associated with a
particular signaling bit. The channel numbers have been assigned as described in the ITU documents. For
example, channel 1 is associated with time slot 1 and channel 30 is associated with time slot 31. There is
a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to
TS16). The signaling registers are detailed below.
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex)
(MSB) (LSB)
0 0 0 0 X Y X X RS1 (30)
A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) RS2 (31)
A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) RS3 (32)
A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18) RS4 (33)
A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19) RS5 (34)
A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20) RS6 (35)
A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21) RS7 (33)
A(7) B(7) C(7) D(7) A(22) B(22) C(22) D(22) RS8 (37)
A(8) B(8) C(8) D(8) A(23) B(23) C(23) D(23) RS9 (38)
A(9) B(9) C(9) D(9) A(24) B(24) C(24) D(24) RS10 (39)
A(10) B(10) C(10) D(10) A(25) B(25) C(25) D(25) RS11 (3A)
A(11) B(11) C(11) D(11) A(26) B(26) C(26) D(26) RS12 (3B)
A(12) B(12) C(12) D(12) A(27) B(27) C(27) D(27) RS13 (3C)
A(13) B(13) C(13) D(13) A(28) B(28) C(28) D(28) RS14 (3D)
A(14) B(14) C(14) D(14) A(29) B(29) C(29) D(29) RS15 (3E)
A(15) B(15) C(15) D(15) A(30) B(30) C(30) D(30) RS16 (3F)
SYMBOL POSITION NAME AND DESCRIPTION X RS1.0/1/3
Spare Bits Y RS1.2
Remote Alarm Bit (integrated and reported in SR1.6) A(1) RS2.7
Signaling Bit A for Channel 1 D(30) RS16.0
Signaling Bit D for Channel 30 Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been
